DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Claims 1-20 are pending. Claims 1 and 6 have been amended as per Applicants' request.
Papers Submitted
It is hereby acknowledged that the following papers have been received and placed of record in the file:
Amended Claims as filed on June 04, 2026
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: “a package stocker configured to store a plurality of components”, “a package transport device configured to transport” in claim 1, and “the package stocker is further configured to store a plurality of trays” in claim 6.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification in at least paragraph [0095] and [0101] as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1-5 and 15-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wilson et al. (US 2005/0055601) (hereinafter Wilson) (published March 10, 2005) in view of YOSHIMIZU (US 2021/0149568) (hereinafter Yoshimizu) (published May 20, 2021).
Regarding Claim 1, Wilson discloses a storage system comprising: a package stocker configured to store a plurality of components, each of the plurality of components including one or more nonvolatile memory;
“Referring first to FIG. 1, there is shown a robotically assisted disk (RAD) system or data storage system generally indicated by reference numeral 10. RAD system 10 has a frame or cabinet 12. The cabinet 12 includes a data storage station 14. The data storage station 14 has a number of storage shelves 16 or storing locations in each of which a storage element (SE), i.e., memory device 18 such as HDD is received while it is electrically disconnected from a power supply not shown” (Wilson [0034])
a drive including at least one socket on which a components among the plurality of components is able to be detachably mounted;
“The cabinet 12 also includes a centralized interface area or drive station 20 having at least one storage docking location (SDL) 22. SDL 22 is designed to receive and thereby electrically energize the memory device 18 so that data can be recorded therein and retrieved therefrom as required” (Wilson [0034])
a host apparatus communicatively connected to the drive and configured to execute reading or writing data from or to the one or more nonvolatile memory of the component mounted on the socket; and
“A control station 24 has a system controller 26 for powering the memory device 18 in SDL 22, thereby recording data into the memory device 18 received in SDL 22 and retrieving the same therefrom in response to a request from a server system 28” (Wilson [0034])
a package transport device configured to transport each of the plurality of components between the package stocker and the drive,
“In order to transport each memory device 18 between the storage shelf 16 of storage station 14 and SDL 22 of drive station 20, a pick and place mechanism 30 is provided in the cabinet 12, which will be described in detail later” (Wilson [0034])
wherein the host apparatus is further configured to: determine a first component that includes a first nonvolatile memory to be accessed, among the plurality of components;
“The storage element (SE) movement for docking/undocking from the dock location (SDL) or switching operation can be initiated by the AIT system or communication derived from a host computer with the system controller through one or more communication interfaces” (Wilson [0074] the memory needed to be accessed will be docked)
when the first component is mounted on the socket of the drive, execute a first operation of reading or writing data from or to the first nonvolatile memory; and
“The cabinet 12 also includes a centralized interface area or drive station 20 having at least one storage docking location (SDL) 22. SDL 22 is designed to receive and thereby electrically energize the memory device 18 so that data can be recorded therein and retrieved therefrom as required” (Wilson [0034] when the memory device is electrically energized it is mounted on the socket)
when the first component is not mounted on the socket of the drive, cause the package transport device to transport the first component to the drive, and to mount the first component on the socket of the drive.
“In the event that a data access is made by the host system on the virtual drive which data is not currently available from currently docked/switched SE in the virtual drive set, SMM communicates the need for the correct SE containing the requested data to be docked into an SDL or to be switched by the system controller prior to the actual data being returned to the host system” (Wilson [0082])
But does not explicitly state the component being semiconductor packages and nonvolatile memory being nonvolatile memory dies.
Yoshimizu discloses the component being semiconductor packages and nonvolatile memory being nonvolatile memory dies
“The storage stocker 30 stores the plurality of semiconductor wafers 40, respectively. The storage stocker 30 includes a plurality of wafer storage locations” (Yoshimizu [0056] the storage stocker 30 would be the same as the data storage station of Wilson)
“The semiconductor wafer 40 includes a plurality of nonvolatile memory dies 70” (Yoshimizu [0072])
It would have been obvious before the effective filing date of the invention to one of ordinary skill in the art to substitute the storage elements of hard drives in Wilson with the semiconductor wafers having non-volatile dies. The motivation for doing so would be faster access speeds and lower power use compared to disk storage.
Regarding Claim 2, Wilson and Yoshimizu further discloses wherein the host apparatus is further configured to: when the first semiconductor package is not mounted on the socket of the drive and the drive includes an empty socket, cause the package transport device to transport the first semiconductor package to the drive, and to mount the first semiconductor package on the empty socket of the drive; and
“In the event that a data access is made by the host system on the virtual drive which data is not currently available from currently docked/switched SE in the virtual drive set, SMM communicates the need for the correct SE containing the requested data to be docked into an SDL or to be switched by the system controller prior to the actual data being returned to the host system” (Wilson [0082] the storage element is docked into an empty slot)
“The semiconductor wafer 40 includes a plurality of nonvolatile memory dies 70” (Yoshimizu [0072] the semiconductor wafer is the storage element)
when the first semiconductor package is not mounted on the socket of the drive and the drive includes no empty socket, cause the package transport device to detach a second semiconductor package from the socket of the drive, and cause the package transport device to transport the first semiconductor package to the drive, and to mount the first semiconductor package on the socket of the drive from which the second semiconductor package has been detached.
“In the event that a data access is made by the host system on the virtual drive which data is not currently available from currently docked/switched SE in the virtual drive set, SMM communicates the need for the correct SE containing the requested data to be docked into an SDL or to be switched by the system controller prior to the actual data being returned to the host system” (Wilson [0082] the storage element is switched with another storage element that was docked)
Regarding Claim 3, Wilson and Yoshimizu further discloses wherein the host apparatus is further configured to: manage a priority of each of the plurality of semiconductor packages; and control a location where each of the plurality of semiconductor packages is present, based on the priority of each of the plurality of semiconductor packages, such that:
“In the RAD system, the central pick and place mechanism 30 is used for transporting each addressed storage element (SE) or memory device 18 from its shelf 14 to the centralized interface area 20 or power/communication interface location for data reading/writing of memory device. At the interface area 22 the storage element (SE) is powered up, allowing data to be written therein and retrieved therefrom. Preferably, SDL resides in the same plane as and adjacent to storage shelves (SS), allowing the pick and place mechanism to perform the pick and place operation in a short time, minimizing a time necessary for data reading and retrieving” (Wilson [0072] the priority of the storage elements would be based on the time necessary for data reading and writing)
“The semiconductor wafer 40 includes a plurality of nonvolatile memory dies 70” (Yoshimizu [0072] the semiconductor wafer is the storage element)
a semiconductor package having a priority of a first level is mounted on the socket of the drive; a semiconductor package having a priority of a second level lower than the priority of the first level is held in the package transport device; and a semiconductor package having a priority of a third level lower than the priority of the second level is stored in the package stocker.
“Provided around the pick and place mechanism 30 are plural memory device storage stations 14 and the docking station 20. In this embodiment, three storage stations 14 and one drive station 20 are arranged at regular intervals about the pick and place mechanism 30. Each storage station 14 has a number of storage shelves 16 for supporting memory devices” (Wilson [0038] there are three possible locations for the storage elements and the time necessary for data reading and writing would differ based on where the storage element is; the storage element in the docking station would have a first level of priority since it is ready to be accessed; the storage element in the pick and place mechanism would have a second level of priority since it is in transit and can be mounted for access; the storage element in the storage station would have a third level of priority since it is it is not ready accessed until it chosen to be mounted)
“In the RAD system, the central pick and place mechanism 30 is used for transporting each addressed storage element (SE) or memory device 18 from its shelf 14 to the centralized interface area 20 or power/communication interface location for data reading/writing of memory device. At the interface area 22 the storage element (SE) is powered up, allowing data to be written therein and retrieved therefrom. Preferably, SDL resides in the same plane as and adjacent to storage shelves (SS), allowing the pick and place mechanism to perform the pick and place operation in a short time, minimizing a time necessary for data reading and retrieving” (Wilson [0072] the priority of the storage elements would be based on the time necessary for data reading and writing)
Regarding Claim 4, Wilson and Yoshimizu further discloses wherein the package stocker includes a first storage location and a second storage location, and the host apparatus is configured to control the location where each of the plurality of semiconductor packages is present, based on the priority of each of the plurality of semiconductor packages, such that:
“The data storage station 14 has a number of storage shelves 16 or storing locations in each of which a storage element (SE), i.e., memory device 18 such as HDD is received while it is electrically disconnected from a power supply not shown” (Wilson [0034])
“Preferably, SDL resides in the same plane as and adjacent to storage shelves (SS), allowing the pick and place mechanism to perform the pick and place operation in a short time, minimizing a time necessary for data reading and retrieving” (Wilson [0072] by controlling where the storage elements are placed the time to retrieve them would differ)
“The semiconductor wafer 40 includes a plurality of nonvolatile memory dies 70” (Yoshimizu [0072] the semiconductor wafer is the storage element)
the semiconductor package having the priority of the third level is stored in the first storage location of the package stocker; and a semiconductor package having a priority of a fourth level lower than the priority of the third level is stored in the second storage location of the package stocker.
“In the RAD system, the central pick and place mechanism 30 is used for transporting each addressed storage element (SE) or memory device 18 from its shelf 14 to the centralized interface area 20 or power/communication interface location for data reading/writing of memory device. At the interface area 22 the storage element (SE) is powered up, allowing data to be written therein and retrieved therefrom. Preferably, SDL resides in the same plane as and adjacent to storage shelves (SS), allowing the pick and place mechanism to perform the pick and place operation in a short time, minimizing a time necessary for data reading and retrieving” (Wilson [0072] the priority of the storage elements would be based on the time necessary for data reading and writing; the location with a longer time necessary would have a lower priority)
Regarding Claim 5, Wilson further discloses wherein a distance between the first storage location and the package transport device is shorter than a distance between the second storage location and the package transport device.
“The data storage station 14 has a number of storage shelves 16 or storing locations in each of which a storage element (SE), i.e., memory device 18 such as HDD is received while it is electrically disconnected from a power supply not shown” (Wilson [0034] the further the location is from the pick and place mechanism/packet transport, the longer time it take to retrieve and would have lower priority)
Regarding Claim 15, Yoshimizu further discloses wherein each of the plurality of semiconductor packages includes a plurality of nonvolatile memory dies.
“The semiconductor wafer 40 includes a plurality of nonvolatile memory dies 70” (Yoshimizu [0072])
Regarding Claim 16, Yoshimizu further discloses wherein each of the plurality of semiconductor packages includes a first surface, a second surface opposite to the first surface, and a plurality of ball-type metal terminals disposed on the second surface, and the plurality of ball-type metal terminals are connected to channel terminals of the plurality of nonvolatile memory dies.
“The semiconductor wafer 40 includes a plurality of electrodes (hereinafter, referred to as pads) 41 that can be connected to the outside. More specifically, the plurality of pads 41 are a group of pads included in each of the plurality of nonvolatile memory dies in the semiconductor wafer 40. Each of the plurality of pads 41 is used to supply a power supply voltage and input/output a signal” (Yoshimizu [0038] the wafer has two sides and on one side is the group of pad/terminals exposed for communication and power, the channel terminals include input/output terminals)
Regarding Claim 17, Wilson further discloses wherein the host apparatus includes a processor configured to execute a first program for managing an amount of data stored in at least one of the plurality of semiconductor packages stored in the package stocker.
“For causing the server system 28 to control RAD system 10, the server system 28 is installed with necessary applications or softwares including a suitable operating system such as MS Windows or Linux. Another applications installed in the servers are those required for controlling a number of memory devices, including "Zfs" available from NTT-IT Corporation in Japan, "AMASS" Virtual from Advanced Digital Information Corporation, or "MagnaVault" from BakBone Software In” (Wilson [0036])
“Such software causes the server system 28 to recognize the FAD system to be seen as one or more large memory devices actually consisting of a multiplicity of memory devices 18 not only received in SDL 22 but also stored in the storage shelf 16 as logically and electrically connected to the system controller 26” (Wilson [0037])
Regarding Claim 18, Yoshimizu further discloses wherein each of the plurality of semiconductor packages stores a package identifier, and
“The identification information may use any identifier (also referred to as a wafer ID) that can uniquely identify each semiconductor wafer” (Yoshimizu [0040])
the host apparatus is further configured to: read the package identifier from the first semiconductor package mounted on the socket of the drive by the package transport device;
“When the correspondence between the read identification information and the read check code is correct, the host computer 2 determines whether the read identification information matches the identification information (wafer ID #13) of the storage #3 managed by the host computer 2 to confirm that the semiconductor wafer conveyed to the stage 12 is the semiconductor wafer (here, storage #3) to be written” (Yoshimizu [0197])
determine whether the read package identifier coincides with the package identifier of the first semiconductor package; and
“When the read identification information matches the identification information (wafer ID #13) of the storage #3 managed by the host computer 2, it is confirmed that the semiconductor wafer conveyed to the stage 12 is the storage #3” (Yoshimizu [0197])
in response to determining that the read package identifier coincides with the package identifier of the first semiconductor package, execute reading or writing data from or to the first nonvolatile memory die.
“In this case, the host computer 2 is allowed to perform the “additional write processing” on the storage #3, that is, write data to the first memory area of the storage #3 with the identification information” (Yoshimizu [0197])
Claims 6-9 and 12-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wilson (published March 10, 2005) and Yoshimizu (published May 20, 2021) as applied to claim 1 above, and further in view of DAVIS et al. (US 2011/0219158) (hereinafter Davis) (published September 08, 2011).
Regarding Claim 6, the combination of Wilson and Yoshimizu disclosed the system of claim 1 but does not explicitly state wherein the package stocker is further configured to store a plurality of trays, each of the plurality of trays accommodating a first number of semiconductor packages, the first number being two or more, the drive includes the first number of sockets on which the first number of semiconductor packages accommodated in one of the plurality of trays are able to be collectively and detachably mounted, and the host apparatus is further configured to: identify a first tray that accommodates the first semiconductor package, among the plurality of trays; when the first number of semiconductor packages accommodated in the first tray are mounted on the first number of sockets of the drive, execute reading or writing data from or to the first nonvolatile memory die; and when the first number of semiconductor packages accommodated in the first tray are not mounted on the first number of sockets of the drive, cause the package transport device to transport the first tray to the drive, and to mount the first number of semiconductor packages accommodated in the first tray on the first number of sockets of the drive.
Davis, Yoshimizu, and Wilson discloses wherein the package stocker is further configured to store a plurality of trays, each of the plurality of trays accommodating a first number of semiconductor packages, the first number being two or more,
“the storage system comprises two or more storage devices such as hard disk drives of any appropriate size arranged on the sled connected to the physical expander. The sled is then connected to the midplane such that the use of a single physical expander on the sled enables plural disk drives to be provided in the footprint usually only required for a single disk drive” (Davis [0028] see Fig. 5, two storage units are fit into the area of the sled)
“The semiconductor wafer 40 includes a plurality of nonvolatile memory dies 70” (Yoshimizu [0072] the storage would be the semiconductor wafers instead of the hard drives)
the drive includes the first number of sockets on which the first number of semiconductor packages accommodated in one of the plurality of trays are able to be collectively and detachably mounted, and
“A midplane 32 is shown as part of the storage assembly. A standard connector 34 is provided on the midplane 32 such that the sled connects to the midplane in the same physical way as if there was only a single disk drive on the sled” (Davis [0086] see Fig. 5 the sled being mounted would cause both of the storage elements to be mounted)
“The semiconductor wafer 40 includes a plurality of nonvolatile memory dies 70” (Yoshimizu [0072] the semiconductor wafer is the storage being mounted on the tray)
the host apparatus is further configured to: identify a first tray that accommodates the first semiconductor package, among the plurality of trays;
“The storage element (SE) movement for docking/undocking from the dock location (SDL) or switching operation can be initiated by the AIT system or communication derived from a host computer with the system controller through one or more communication interfaces” (Wilson [0074] the storage element needed to be accessed will be identified and docked)
“The assembly comprises two hard disk drives 26.sub.1 and 26.sub.2 arranged on a sled or carrier 28” (Davis [0085] the identified tray with the data needed to be accessed)
“The semiconductor wafer 40 includes a plurality of nonvolatile memory dies 70” (Yoshimizu [0072] the semiconductor wafer is the storage being mounted on the tray)
when the first number of semiconductor packages accommodated in the first tray are mounted on the first number of sockets of the drive, execute the first operation; and
“The cabinet 12 also includes a centralized interface area or drive station 20 having at least one storage docking location (SDL) 22. SDL 22 is designed to receive and thereby electrically energize the memory device 18 so that data can be recorded therein and retrieved therefrom as required” (Wilson [0034] when the memory device is electrically energized it is mounted on the socket)
“The assembly comprises two hard disk drives 26.sub.1 and 26.sub.2 arranged on a sled or carrier 28” (Davis [0085] the identified tray with the data being accessed)
when the first number of semiconductor packages accommodated in the first tray are not mounted on the first number of sockets of the drive, cause the package transport device to transport the first tray to the drive, and to mount the first number of semiconductor packages accommodated in the first tray on the first number of sockets of the drive.
“In the event that a data access is made by the host system on the virtual drive which data is not currently available from currently docked/switched SE in the virtual drive set, SMM communicates the need for the correct SE containing the requested data to be docked into an SDL or to be switched by the system controller prior to the actual data being returned to the host system” (Wilson [0082])
“The assembly comprises two hard disk drives 26.sub.1 and 26.sub.2 arranged on a sled or carrier 28” (Davis [0085] the identified tray with the data need to be docked and then accessed)
“The semiconductor wafer 40 includes a plurality of nonvolatile memory dies 70” (Yoshimizu [0072] the semiconductor wafer is the storage being mounted on the tray)
It would have been obvious before the effective filing date of the invention to one of ordinary skill in the art to combine the tray holding multiple drives in Davis with the system in the combination of Wilson and Yoshimizu. The motivation for doing so would be improve space efficiency and adaptability by being able to fit more drives and different sized drives on the trays.
Regarding Claim 7, Wilson, Davis, and Yoshimizu further discloses wherein the host apparatus is further configured to: manage a priority of each of the plurality of trays, the priority of each of the plurality of trays being determined based on a priority of each of the plurality of semiconductor packages; and control a location where each of the plurality of trays is present, based on the priority of each of the plurality of trays, such that:
“In the RAD system, the central pick and place mechanism 30 is used for transporting each addressed storage element (SE) or memory device 18 from its shelf 14 to the centralized interface area 20 or power/communication interface location for data reading/writing of memory device. At the interface area 22 the storage element (SE) is powered up, allowing data to be written therein and retrieved therefrom. Preferably, SDL resides in the same plane as and adjacent to storage shelves (SS), allowing the pick and place mechanism to perform the pick and place operation in a short time, minimizing a time necessary for data reading and retrieving” (Wilson [0072] the priority of the storage elements would be based on the time necessary for data reading and writing)
“The assembly comprises two hard disk drives 26.sub.1 and 26.sub.2 arranged on a sled or carrier 28” (Davis [0085] the sled/tray has the storage element mounted on it)
“The semiconductor wafer 40 includes a plurality of nonvolatile memory dies 70” (Yoshimizu [0072] the semiconductor wafer is the storage being mounted on the tray)
the first number of semiconductor packages accommodated in a tray having a priority of a first level are mounted on the first number of sockets of the drive; a tray having a priority of a second level lower than the priority of the first level is held in the package transport device; a tray having a priority of a third level lower than the priority of the second level is stored in a first storage location of the package stocker; and a tray having a priority of a fourth level lower than the priority of the third level is stored in a second storage location of the package stocker.
“Provided around the pick and place mechanism 30 are plural memory device storage stations 14 and the docking station 20. In this embodiment, three storage stations 14 and one drive station 20 are arranged at regular intervals about the pick and place mechanism 30. Each storage station 14 has a number of storage shelves 16 for supporting memory devices” (Wilson [0038] there are three possible locations for the storage elements and the time necessary for data reading and writing would differ based on where the storage element is; the storage element in the docking station would have a first level of priority since it is ready to be accessed; the storage element in the pick and place mechanism would have a second level of priority since it is in transit and can be mounted for access; the storage element in the storage station would have a third level of priority since it is it is not ready accessed until it chosen to be mounted; the storage element in the storage station further from the pick and place mechanism than the storage element with the third level of priority would have a fourth level of priority since it is it is not ready accessed until it chosen to be mounted and would take longer than the third level priority to be accessed)
“In the RAD system, the central pick and place mechanism 30 is used for transporting each addressed storage element (SE) or memory device 18 from its shelf 14 to the centralized interface area 20 or power/communication interface location for data reading/writing of memory device. At the interface area 22 the storage element (SE) is powered up, allowing data to be written therein and retrieved therefrom. Preferably, SDL resides in the same plane as and adjacent to storage shelves (SS), allowing the pick and place mechanism to perform the pick and place operation in a short time, minimizing a time necessary for data reading and retrieving” (Wilson [0072] the priority of the storage elements would be based on the time necessary for data reading and writing)
“The assembly comprises two hard disk drives 26.sub.1 and 26.sub.2 arranged on a sled or carrier 28” (Davis [0085] the sled/tray has the storage element mounted on it)
“The semiconductor wafer 40 includes a plurality of nonvolatile memory dies 70” (Yoshimizu [0072] the semiconductor wafer is the storage being mounted on the tray)
Regarding Claim 8, Wilson further discloses wherein a distance between the first storage location and the package transport device is shorter than a distance between the second storage location and the package transport device.
“The data storage station 14 has a number of storage shelves 16 or storing locations in each of which a storage element (SE), i.e., memory device 18 such as HDD is received while it is electrically disconnected from a power supply not shown” (Wilson [0034] the further the location is from the pick and place mechanism/packet transport, the longer time it take to retrieve and would have lower priority)
Regarding Claim 9, Yoshimizu further discloses wherein the package stocker includes a tray loading/unloading slot configured to be used to:
“The storage conveyance mechanism 20 operates to convey the semiconductor wafer 40 between the storage stocker 30 and the stage 12 under the control of the host computer 2” (Yoshimizu [0052] load/unload internally)
“The storage stocker 30 includes a plurality of wafer storage locations. A user can add a new semiconductor wafer 40 to a vacant wafer storage location of the storage stocker 30 as needed” (Yoshimizu [0056] load/unload externally)
add one of the plurality of trays to the package stocker from an outside of the package stocker; and
“When the writing or reading of data to or from the semiconductor wafer 40 to be accessed is completed, the storage device 3 can store the semiconductor wafer 40 on the stage 12 in the wafer storage location in the storage stocker 30” (Yoshimizu [0061] the stage is outside the stocker)
“The “wafer addition processing” means processing of adding management information necessary to manage the new semiconductor wafer immediately after the shipment from the factory which is added to the storage stocker 30 by the user” (Yoshimizu [0147])
eject one of the plurality of trays from the package stocker to the outside of the package stocker.
“Upon receiving the conveyance request, the storage conveyance mechanism 20 of the storage device 3 conveys the semiconductor wafer 40 of the designated wafer storage location in the storage stocker 30 to the reader & writer (prober) 10 and mounts the semiconductor wafer 40 on the stage 12” (Yoshimizu [0060] the stage is outside the stocker)
“The “wafer removal processing” means processing of deleting the management information corresponding to the semiconductor wafer removed by the user from the storage stocker 30” (Yoshimizu [0148])
Regarding Claim 12, Yoshimizu and Davis further discloses wherein each of the plurality of semiconductor packages includes a first surface, a second surface opposite to the first surface, and a plurality of ball-type metal terminals disposed on the second surface, and
“The semiconductor wafer 40 includes a plurality of electrodes (hereinafter, referred to as pads) 41 that can be connected to the outside. More specifically, the plurality of pads 41 are a group of pads included in each of the plurality of nonvolatile memory dies in the semiconductor wafer 40. Each of the plurality of pads 41 is used to supply a power supply voltage and input/output a signal” (Yoshimizu [0038] the wafer has two sides and on one side is the group of pad exposed for communication and power)
each of the plurality of trays has a surface in which an opening through which the plurality of ball-type metal terminals of each of the first number of semiconductor packages are exposed is formed.
“The semiconductor wafer 40 includes a plurality of electrodes (hereinafter, referred to as pads) 41 that can be connected to the outside. More specifically, the plurality of pads 41 are a group of pads included in each of the plurality of nonvolatile memory dies in the semiconductor wafer 40. Each of the plurality of pads 41 is used to supply a power supply voltage and input/output a signal” (Yoshimizu [0038])
“The assembly comprises two hard disk drives 26.sub.1 and 26.sub.2 arranged on a sled or carrier 28” (Davis [0085] the semiconductor wafers on the sled/carrier would be mounted such that an exposed side would be able to be the connection side)
Regarding Claim 13, Yoshimizu and Davis wherein each of the plurality of semiconductor packages includes a first surface, a second surface opposite to the first surface, and a plurality of ball-type metal terminals disposed on the second surface,
“The semiconductor wafer 40 includes a plurality of electrodes (hereinafter, referred to as pads) 41 that can be connected to the outside. More specifically, the plurality of pads 41 are a group of pads included in each of the plurality of nonvolatile memory dies in the semiconductor wafer 40. Each of the plurality of pads 41 is used to supply a power supply voltage and input/output a signal” (Yoshimizu [0038] the wafer has two sides and on one side is the group of pad exposed for communication and power)
the drive further includes a board on which at least the first number of sockets are disposed, the board includes one or more first recessed portions, and
“A plurality of probe pins 51 are located on the surface 11A. Each probe pin 51 is used to supply an electrical signal to a pad 41 of the semiconductor wafer 40 mounted on the stage 12 or receive an electrical signal from the pad 41” (Yoshimizu [0047] the probe pins are the sockets, see the stage and probe card in Fig. 1)
each of the plurality of trays has a lower surface in which an opening through which the plurality of ball-type metal terminals of each of the first number of semiconductor packages are exposed is formed, and the lower surface of each of the plurality of trays includes one or more first protrusions configured to fit into the one or more first recessed portions of the board of the drive.
“The assembly comprises two hard disk drives 26.sub.1 and 26.sub.2 arranged on a sled or carrier 28” (Davis [0085] the semiconductor wafers on the sled/carrier would be mounted such that an exposed side would be able to be the connection side)
“The probe pin 51 is also referred to as a probe or a probe needle. The total number of probe pins 51 arranged on the surface 11A may be the same as the total number of pads 41 in the semiconductor wafer 40. In this case, the reader & writer (prober) 10 can be collectively connected to the pads 41 in the semiconductor wafer 40 via the probe card 11. This makes it possible to increase the number of nonvolatile memory dies that can be accessed in parallel” (Yoshimizu [0047] the exposed side of the carrier would be interfacing with the prober to connect to the wafer)
Claims 10 and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wilson (published March 10, 2005), Yoshimizu (published May 20, 2021), and Davis (published September 08, 2011) as applied to claim 9 above, and further in view of Frink et al. (US 2012/0243170) (hereinafter Frink) (published September 27, 2012).
Regarding Claim 10, the combination of Wilson, Yoshimizu, and Davis disclosed the system of claim 9 but does not explicitly state wherein the package stocker includes at least a pair of rails extending in parallel to each other and on which one of the plurality of trays is able to be placed, and the one of the plurality of trays placed on the pair of rails is movable along the pair of rails.
Frink and Davis discloses wherein the package stocker includes at least a pair of rails extending in parallel to each other and on which one of the plurality of trays is able to be placed, and the one of the plurality of trays placed on the pair of rails is movable along the pair of rails.
“Guide rims 249 may serve as guides for hard disk drives 226” (Frink [0086] the guide rims are the rails which extends from the back towards the front where the drives can be taken out)
“The assembly comprises two hard disk drives 26.sub.1 and 26.sub.2 arranged on a sled or carrier 28” (Davis [0085] the sled/carrier/tray would move along the guide rims)
It would have been obvious before the effective filing date of the invention to one of ordinary skill in the art to combine rails in Frinks with the system in the combination of Wilson, Yoshimizu, and Davis. The motivation for doing so would be improve ease of use and spatial optimization by guiding the trays into preoptimized storage locations.
Regarding Claim 11, Wilson and Frink further discloses wherein the package transport device is opposed to the tray loading/unloading slot, and
“The pick and place mechanism 30 further includes a transport device or handler 42 for the transportation of memory device between the storage shelf (SS) 16 and the drive station SDL 22. The handler 42 is drivingly connected to a motor mounted therein (not shown) so that, when the motor is energized, the transport device moves vertically up or down on shaft 32. Provided around the pick and place mechanism 30 are plural memory device storage stations 14 and the docking station 20” (Wilson [0038] see Fig. 3 the openings of the storage shelf are facing the pick and place mechanism)
the pair of rails of the package stocker extends in a direction from the tray loading/unloading slot toward the package transport device.
“Guide rims 249 may serve as guides for hard disk drives 226” (Frink [0086] the guide rims are the rails which extends from the back towards the front where the drives can be taken out)
“The pick and place mechanism 30 further includes a transport device or handler 42 for the transportation of memory device between the storage shelf (SS) 16 and the drive station SDL 22. The handler 42 is drivingly connected to a motor mounted therein (not shown) so that, when the motor is energized, the transport device moves vertically up or down on shaft 32. Provided around the pick and place mechanism 30 are plural memory device storage stations 14 and the docking station 20” (Wilson [0038] see Fig. 3 the openings of the storage shelf are facing the pick and place mechanism)
Claim 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wilson (published March 10, 2005), Yoshimizu (published May 20, 2021), and Davis (published September 08, 2011) as applied to claim 13 above, and further in view of Bennett, II et al. (US 2016/0353600) (hereinafter Bennett) (published December 01, 2016).
Regarding Claim 14, the combination of Wilson, Yoshimizu, and Davis disclosed the system of claim 13 but does not explicitly state further comprising: a lid member that includes one or more second recessed portions, wherein each of the plurality of trays has an upper surface opposite to the lower surface, the upper surface includes one or more second protrusions, and at least one of the plurality of trays placed on the board is covered with the lid member such that the one or more second recessed portions of the lid member are fitted with the one or more second protrusions of the upper surface of the at least one of the plurality of trays.
Bennett discloses further comprising: a lid member that includes one or more second recessed portions, wherein each of the plurality of trays has an upper surface opposite to the lower surface, the upper surface includes one or more second protrusions, and at least one of the plurality of trays placed on the board is covered with the lid member such that the one or more second recessed portions of the lid member are fitted with the one or more second protrusions of the upper surface of the at least one of the plurality of trays.
“The carriers 118 and dividers may have features (e.g., latches) that mechanically hold the hard disk drives 116 in place after installment, e.g., to prevent the drives from sliding back out of the enclosure 110. Instead or in addition, the carriers 118 may have protrusions that interface with a cover 120. In such a case, the cover 120 holds the hard disk drives 116 against the connectors 114 when fastened to the enclosure 100” (Bennett [0016] the cover would be opposite of the side that is used for the connections, see fig. 3 and 4 which shows the protrusions)
It would have been obvious before the effective filing date of the invention to one of ordinary skill in the art to combine lid in Bennett with the system in the combination of Wilson, Yoshimizu, and Davis. The motivation for doing so would be improve the stability of the system by keeping the components in the carrier/tray held in place.
Claims 19 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wilson (published March 10, 2005), Yoshimizu (published May 20, 2021), and Davis (published September 08, 2011) as applied to claim 6 above, and further in view of MATSUSHITA et al. (US 2024/0015942) (hereinafter Matsushita) (PCT filed December 25, 2020).
Regarding Claim 19, the combination of Wilson, Yoshimizu, and Davis disclosed the system of claim 6, and Yoshimizu further discloses wherein each of the plurality of semiconductor packages stores a package identifier,
“The identification information may use any identifier (also referred to as a wafer ID) that can uniquely identify each semiconductor wafer” (Yoshimizu [0040])
determine whether the read package identifier coincides with the package identifier of the first semiconductor package; and
“When the read identification information matches the identification information (wafer ID #13) of the storage #3 managed by the host computer 2, it is confirmed that the semiconductor wafer conveyed to the stage 12 is the storage #3” (Yoshimizu [0197])
in response to determining that the read package identifier coincides with the package identifier of the first semiconductor package, execute reading or writing data from or to the first nonvolatile memory die.
“In this case, the host computer 2 is allowed to perform the “additional write processing” on the storage #3, that is, write data to the first memory area of the storage #3 with the identification information” (Yoshimizu [0197])
But does not explicitly state each of the plurality of trays includes a tray identifier, and the host apparatus is further configured to: read the tray identifier from the first tray transported to the drive by the package transport device; determine whether the read tray identifier coincides with the package identifier of the first tray; and in response to determining that the read tray identifier coincides with the tray identifier of the first tray, read the package identifier from the first semiconductor package accommodated in the first tray.
Matsushita and Yoshimizu discloses each of the plurality of trays includes a tray identifier, and
“As shown in FIG. 2A, a tray 42 houses a plurality of components 41 arranged in a matrix. The tray 42 is given a component ID 41d that is a barcode for identifying the component 41 housed in the tray 42, and a tray ID 42d that is a barcode for identifying the tray 42” (Matsushita [0044])
the host apparatus is further configured to: read the tray identifier from the first tray transported to the drive by the package transport device;
“The ID reader 371 is a barcode scanner for reading the above-described IDs (component ID 41d, tray ID 42d, magazine ID 44d) composed of the barcodes, and is attached to the end effector 361 of the working robot 36” (Matsushita [0053])
determine whether the read tray identifier coincides with the package identifier of the first tray; and in response to determining that the read tray identifier coincides with the tray identifier of the first tray, read the package identifier from the first semiconductor package accommodated in the first tray;
“For example, when the tray 42 is placed in the loading section 31, the control unit 391 causes the ID reader 371 to read the component ID 41d and the tray ID 42d given to this tray 42, and then inserts this tray 42 into the tray shelf of the tray storage rack 32 using the end effector 361. Moreover, the control unit 391 registers these component ID 41d, tray ID 42d and the number of this tray shelf with the storage information Is in association with each other” (Matsushita [0057] the storage information includes the linking of tray ID to component ID)
“When the correspondence between the read identification information and the read check code is correct, the host computer 2 determines whether the read identification information matches the identification information (wafer ID #13) of the storage #3 managed by the host computer 2 to confirm that the semiconductor wafer conveyed to the stage 12 is the semiconductor wafer (here, storage #3) to be written” (Yoshimizu [0197])
It would have been obvious before the effective filing date of the invention to one of ordinary skill in the art to combine identification tray ID and levels of organization in Matsushita with the system in the combination of Wilson, Yoshimizu, and Davis. The motivation for doing so would be lower the chances of proximity errors by an extra check to match the parent location (tray) before the child (component/wafer that’s on the tray).
Regarding Claim 20, Yoshimizu and Matsushita further discloses wherein at least one of the one or more nonvolatile memory dies included in each of the plurality of semiconductor packages includes an information storage area to store the package identifier, the tray identifier of each of the plurality of trays is represented by a barcode,
“The semiconductor wafer comprises electrodes connectable to the probe pins; a first memory area that can store user data; and a second memory area that can store identification information for identification of the semiconductor wafer and a check code for checking integrity of the identification information” (Yoshimizu [0031])
“As shown in FIG. 2A, a tray 42 houses a plurality of components 41 arranged in a matrix. The tray 42 is given a component ID 41d that is a barcode for identifying the component 41 housed in the tray 42, and a tray ID 42d that is a barcode for identifying the tray 42” (Matsushita [0044] tray id would also be stored as identification information)
the drive includes a controller and a barcode reader, and
“The controller is capable of reading the identification information and the check code from the second memory area” (Yoshimizu [0031])
“The ID reader 371 is a barcode scanner for reading the above-described IDs (component ID 41d, tray ID 42d, magazine ID 44d) composed of the barcodes, and is attached to the end effector 361 of the working robot 36” (Matsushita [0053])
the host apparatus is configured to: read the package identifier from the information storage area of the at least one of the one or more nonvolatile memory dies included in the first semiconductor package using the controller of the drive; and
“When the correspondence between the read identification information and the read check code is correct, the host computer 2 determines whether the read identification information matches the identification information (wafer ID #13) of the storage #3 managed by the host computer 2 to confirm that the semiconductor wafer conveyed to the stage 12 is the semiconductor wafer (here, storage #3) to be written” (Yoshimizu [0197])
read the tray identifier from the first tray using the barcode reader of the drive.
“The ID reader 371 is a barcode scanner for reading the above-described IDs (component ID 41d, tray ID 42d, magazine ID 44d) composed of the barcodes, and is attached to the end effector 361 of the working robot 36” (Matsushita [0053])
Response to Arguments
The Rejection of Claims 6-14, 19, and 20 under 35 U.S.C. § 112(b) or second paragraph
Applicant’s arguments, see page 12 of remarks, filed June 04, 2026, with respect to claims 6-14, 19, and 20 have been fully considered and are persuasive. The 35 U.S.C. § 112(b) rejection of claims 6-14, 19, and 20 has been withdrawn.
The Prior Art Rejections
Applicant's arguments filed June 04, 2026 have been fully considered but they are not persuasive.
Applicant Argues:
a) (page 14 top) The outstanding rejection notes Yoshimizu discloses semiconductor wafer 40. Applicant submits in Yoshimizu that semiconductor wafer 40 itself is used as the storage medium, as clear for example from [0037] of Yoshimizu that states: … Applicant submits the above-noted disclosure in Yoshimizu that "Normally on the other hand in fact teaches away from using a nonvolatile memory die instead of the semiconductor wafer 40 itself as a storage medium. Applicant submits Yoshimizu does not disclose or suggest the above-noted highlighted claim features in independent claim 1 to use "a nonvolatile memory die" as a storage medium, and thereby no combination of teachings of Yoshimizu to Wilson would have disclosed such features. Applicant thereby submits that combination of teachings does not meet the above-noted features highlighted in amended independent claim 1 as currently written.
With respect to (a), Applicant's contention that Yoshimizu teaches away from using a nonvolatile memory die as a storage medium is not persuasive. Yoshimizu [0037] does not discourage or criticize the use of a nonvolatile memory die as storage. Rather, Yoshimizu expressly states that “normally, a nonvolatile memory die formed on the semiconductor wafer is cut out as a chip by dicing and used as the storage,” and then describes an alternative in which the semiconductor wafer itself is used as the storage. Thus, Yoshimizu expressly recognizes both die-level and wafer-level storage implementations. The statement that the semiconductor wafer itself may be used as storage therefore does not constitute a teaching away from the use of the individual nonvolatile memory dies.
Moreover, Yoshimizu expressly discloses that semiconductor wafer 40 includes a plurality of nonvolatile memory dies 70 and that each nonvolatile memory die 70 includes pads 41 that can be connected to the outside in paragraph [0072]. Accordingly, Yoshimizu provides an express teaching that the individual nonvolatile memory dies are storage-capable devices that can be externally connected. The fact that Yoshimizu also permits the wafer containing those dies to be handled as the storage does not negate or discourage the disclosed die-level storage arrangement. At most, the disclosure identifies two alternative implementations of the storage medium.
Further, when Yoshimizu is considered in combination with Wilson, the claimed host-side read/write functionality is taught or suggested. Wilson [0034] expressly discloses that control station 24 includes system controller 26 for powering memory device 18 in SDL 22, recording data into the memory device 18, and retrieving data therefrom in response to a request from server system 28. Yoshimizu, meanwhile, provides a plurality of nonvolatile memory dies 70 having externally connectable pads 41 and identifies those dies as storage devices. Thus, one of ordinary skill in the art would have had reason to apply Wilson's controller and read/write functionality to the nonvolatile memory dies disclosed by Yoshimizu. In such a combination, the host/controller of Wilson would be configured to communicate with and perform reading and writing operations on the nonvolatile memory dies of Yoshimizu.
Accordingly, Applicant's assertion that Yoshimizu teaches away from the claimed limitation is not supported by the reference. Yoshimizu does not express a preference against, criticism of, or incompatibility with using a nonvolatile memory die as storage; instead, [0037] expressly identifies use of a nonvolatile memory die as storage as the normal arrangement. Therefore, in view of the teachings of Yoshimizu and Wilson, the Examiner maintains that the combination teaches or suggests the limitation of “a host apparatus communicatively connected to the drive and configured to execute reading or writing data from or to the one or more nonvolatile memory dies of the semiconductor package mounted on the socket.”
b) (page 15 middle) With respect to claim 3 applicant submits Wilson and Yoshimizu do not meet the above-noted claim features. Applicant submits Wilson merely discloses that the latency of data reading and retrieving is shortened by "SDL (storage docking location, 22) resides in the same plane as and adjacent to storage shelves SS, 16)" … Applicant submits Wilson does not disclose or suggest setting a priority for each of the memory devices. In addition, Wilson does not disclose or suggest changing the location of each of the memory devices in accordance with the priority either. Applicant submits Yoshimizu also does not disclose or suggest such features.
With respect to (b), Applicant's contention that Wilson does not disclose or suggest setting a priority for each memory device is not persuasive. Wilson [0038] discloses that the memory devices are maintained at different locations, including storage shelves 16, the pick and place mechanism 30, and docking station 20, and that the pick and place mechanism transports an addressed memory device from a storage shelf to the docking station for data reading and writing. Wilson [0072] further expressly identifies minimizing the time necessary for data reading and retrieving as a purpose of the disclosed arrangement. Accordingly, Wilson recognizes that the location of a memory device directly affects its readiness for access and the time required to retrieve data. In view of this teaching, it would have been obvious to assign different priority levels to memory devices based on their respective access status and the time required to make them available for reading or writing.
Wilson also teaches controlling the location of the memory devices in accordance with their access requirements. A memory device positioned at the docking station is powered and immediately available for data reading and writing, whereas a memory device being transported by the pick and place mechanism is in the process of being made available for access, and a memory device remaining on a storage shelf has not yet been selected for access. Thus, the disclosed arrangement provides an ordered progression of locations corresponding to different levels of access readiness. In light of Wilson's stated objective of minimizing data access time, one of ordinary skill in the art would have found it obvious to prioritize memory devices and use the pick and place mechanism to control their locations according to those priorities, for example, maintaining a higher-priority device at the docking station, moving a next-priority device through the pick and place mechanism, and retaining a lower-priority device at a storage shelf until needed.
Therefore, Wilson's disclosure is not merely a statement that different locations exist; it provides a reason and functional relationship for using those locations to manage access time. The disclosed movement of an addressed memory device from a storage shelf to the docking station, together with the express objective of minimizing reading and retrieving time, would have suggested the claimed priority-based location control. Applicant's assertion that Wilson does not disclose or suggest changing the location of each memory device in accordance with priority is therefore not persuasive.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SIDNEY LI whose telephone number is (571)270-5967. The examiner can normally be reached Monday to Friday 10:00 AM to 6:00 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Arpan P Savla can be reached at (571) 272-1077. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/S.L./Examiner, Art Unit 2137
/PRASITH THAMMAVONG/Primary Examiner, Art Unit 2137
Prosecution Insights