Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-6 and 10-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1, 10 and 16 were each amended to disclose the plurality of internal electrodes comprises a plurality of first internal electrodes and a plurality of second internal electrodes. Each claim also maintained language indicating a connection electrode penetrates and is connected to the plurality of internal electrodes. It is unclear if the connection electrode is penetrating and connected to either one of the plurality of first internal electrodes and the plurality of second internal electrodes, or both of the plurality of first internal electrodes and the plurality of second internal electrodes; or if the claim needs to be further amended to recite a first connection electrode for the plurality of first internal electrodes and a second connection electrode for the plurality of second internal electrodes. For the purpose of examination, the connection electrode is considered is just considered to penetrate the plurality of first internal electrodes. Claims 2-6, 11-15 and 17-20 are considered to inherit the deficiency of the independent claims.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-7, and 9-20 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 20190066922) in view of Sakurai et al. (US 20200135400).
In regards to claim 1, Lee discloses an electronic component comprising: a capacitor body (110 – FIG. 2; [0036]) comprising: a dielectric layer (110 – FIG. 2; [0036]; noting that the dielectric of the capacitor body as a whole or any portion thereof is being considered the “dielectric layer”); a plurality of internal electrodes comprising a plurality of first internal electrodes and a plurality of second internal electrodes (121, 122 – FIG. 2; [0036]) alternately positioned in a stacking direction (Z – FIG. 2) and spaced apart from one another with the dielectric layer interposed therebetween (FIG. 2); and a first surface, a second surface, a third surface, and a fourth surface, wherein the first and second surfaces (respectively, downward and upward surfaces of 110 as seen in FIG. 2) face each other in the stacking direction; both of the third and the fourth surface are outermost are outermost surfaces of the capacitor body (respectively, leftward and rightward surfaces of 110 as seen in FIG. 2); a connection electrode (131, 133, 135 – FIG. 2; [0036], [0043]) comprising: a main junction portion (131 – FIG. 2) extending in the stacking direction and configured to penetrate the plurality of internal electrodes (FIGs. 2-3); a bypass portion (133 – FIG. 2) connected to the main junction portion and extending in a planar direction in the dielectric layer (FIG. 2); and an end (downward end of 135 – FIG. 2; [0043]) extending from the first surface, wherein the connection electrode is connected to the plurality of internal electrodes in the capacitor body (FIG. 2); and an external electrode (141 – FIG. 2; [0036]) positioned on the first surface and connected to the connection electrode (FIG. 2).
Lee fails to disclose the plurality of first internal electrodes extend from the third surface and the plurality of second internal electrodes extend from the fourth surface.
Sakurai discloses a capacitor body (4 – FIG. 1C), a plurality of internal electrodes comprising a plurality of first internal electrodes and a plurality of second internal electrodes (12 – FIG. 1C; [0044]) alternately positioned in a stacking direction (Z – FIG. 1C) and spaced apart from one another with the dielectric layer interposed therebetween (FIG. 1C); a first surface, a second surface, a third surface, and a fourth surface, wherein the first and second surfaces (respectively, 4d and 4c as seen in FIG. 1C) face each other in the stacking direction; both of the third and the fourth surface are outermost are outermost surfaces of the capacitor body (respectively, 4a and 4b as seen in FIG. 1C), the plurality of first internal electrodes extend from the third surface (12a extending from 4a as seen in FIG. 1C) and the plurality of second internal electrodes extend from the fourth surface (12b extend from 4b as seen in FIG. 1C).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to utilize the extended internal electrodes of Sakurai with the capacitor of Lee for the purpose of adding a reinforcement layer to improve strength, without increasing the size of the capacitor ([108]-[110]).
In regards to claim 2, Lee further discloses wherein: the capacitor body comprises a lowermost end dielectric layer (113; or alternatively portion of 110 downward from lowermost internal electrode layer – FIG. 2; [0038]) configured to adjoin the first surface (FIG. 2), and the bypass portion is positioned in the lowermost end dielectric layer (FIG. 2).
In regards to claim 3, Lee further discloses wherein: the lowermost end dielectric layer (portion of dielectric layer 110 downward from lowermost internal electrode layer – FIG. 2) has a larger thickness than the dielectric layer positioned between the plurality of internal electrodes (FIG. 2).
In regards to claim 4, Lee further discloses wherein: the connection electrode further comprises a conductive portion (135 – FIG. 2; [0036]) connected to the bypass portion (FIG. 2), and the conductive portion extends in the stacking direction in the lowermost end dielectric layer (113; or alternatively portion of 110 downward from lowermost internal electrode layer – FIG. 2), extends to the first surface, and is in contact with the external electrode (FIG. 2).
In regards to claim 5, Lee further discloses wherein: the planar direction comprises first and second directions (respectively, y and x – FIG. 4) orthogonal to each other, and the third and fourth (respectively, leftward and rightward surfaces of 110 as seen in FIG. 2) face each other in the first direction (FIGs. 2, 4).
In regards to claim 6, Lee further discloses, the bypass portion is positioned to extend in the second direction (FIG. 2, 4 – it should be noted that the bypass portion connects vias 131 and 135, and as shown in figure 4, a connection pattern between both vias would inherently have a length in the X-direction, and could therefore be said to extend in the second direction).
In regards to claim 7, Lee further discloses wherein: the plurality of first internal electrodes is positioned at a distance from the fourth surface (FIG. 2), the plurality of second internal electrodes is positioned at a distance from the third surface (FIG. 2), the connection electrode includes: a first connection electrode (131, 133, 135 – FIG. 2) connected to the plurality of first internal electrodes (FIG. 2), the first connection electrode comprises a first main junction portion (131 – FIG. 2) positioned between the third surface and the plurality of second internal electrodes (seen in FIG. 2, and Sakurai FIG. 1C); and a second connection electrode (132, 134, 136 – FIG. 2) connected to the plurality of second internal electrodes (FIG. 2), the second connection electrode comprises a second main junction (132 – FIG. 2) portion positioned between the fourth surface and the plurality of first internal electrodes (seen in FIG. 2, and Sakurai FIG. 1C).
In regards to claim 9, Lee further discloses wherein: the capacitor body further comprises an insulation layer (111 – FIG. 2; [0038]) configured to cover the third surface and the fourth surface (FIG. 2).
In regards to claim 10, Lee discloses an electronic component comprising: a capacitor body (110 – FIG. 2; [0036]) comprising: a dielectric layer (110 – FIG. 2; [0036]; noting that the dielectric of the capacitor body as a whole or any portion thereof is being considered the “dielectric layer”); a plurality of internal electrodes comprising a plurality of first internal electrodes and a plurality of second internal electrodes (121, 122 – FIG. 2; [0036]) alternately positioned in a stacking direction (Z – FIG. 2) and spaced apart from one another with the dielectric layer interposed therebetween (FIG. 2); and a first surface, a second surface, a third surface, and a fourth surface, wherein the first and second surfaces (respectively, downward and upward surfaces of 110 as seen in FIG. 2) face each other in the stacking direction; both of the third and the fourth surface are outermost are outermost surfaces of the capacitor body (respectively, leftward and rightward surfaces of 110 as seen in FIG. 2); a connection electrode (131, 133, 135 – FIG. 2; [0036], [0043]) configured to penetrate the plurality of internal electrodes and connected to the plurality of internal electrodes (FIGs. 2-3), the connection electrode comprising at least one bent portion (portion connecting 131 and 133 as seen in FIG. 2) in the capacitor body and an end (downward end of 135 – FIG. 2) extending from the first surface (FIG. 2); and an external electrode (141 – FIG. 2; [0036]) positioned on the first surface and connected to the connection electrode (FIG. 2).
Lee fails to disclose the plurality of first internal electrodes extend from the third surface and the plurality of second internal electrodes extend from the fourth surface.
Sakurai discloses a capacitor body (4 – FIG. 1C), a plurality of internal electrodes comprising a plurality of first internal electrodes and a plurality of second internal electrodes (12 – FIG. 1C; [0044]) alternately positioned in a stacking direction (Z – FIG. 1C) and spaced apart from one another with the dielectric layer interposed therebetween (FIG. 1C); a first surface, a second surface, a third surface, and a fourth surface, wherein the first and second surfaces (respectively, 4d and 4c as seen in FIG. 1C) face each other in the stacking direction; both of the third and the fourth surface are outermost are outermost surfaces of the capacitor body (respectively, 4a and 4b as seen in FIG. 1C), the plurality of first internal electrodes extend from the third surface (12a extending from 4a as seen in FIG. 1C) and the plurality of second internal electrodes extend from the fourth surface (12b extend from 4b as seen in FIG. 1C).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to utilize the extended internal electrodes of Sakurai with the capacitor of Lee for the purpose of adding a reinforcement layer to improve strength, without increasing the size of the capacitor ([108]-[110]).
In regards to claim 11, Lee further discloses wherein: the at least one bent portion includes a first bent portion (portion connecting 131 and 133 as seen in FIG. 2), and the connection electrode further comprises: a main junction portion (131 – FIG. 2; [0036]) extending in the stacking direction and configured to penetrate the plurality of internal electrodes (FIGs. 2-3); and a bypass portion (133 – FIG. 2; [0043]) connected to the main junction portion by the first bent portion and extending in a planar direction in the dielectric layer (FIG. 2).
In regards to claim 12, Lee further discloses wherein: the at least one bent portion further includes a second bent portion (portion connecting 133 and 135 as seen in FIG. 2), and the connection electrode further comprises a conductive portion (135 – FIG. 2; [0036]) connected to the bypass portion by the second bent portion (FIG. 2), where the conductive portion extends in the stacking direction in the dielectric layer (FIG. 2), extends to the first surface, and is in contact with the external electrode (FIG. 2).
In regards to claim 13, Lee further discloses wherein: the capacitor body further comprises a lowermost end dielectric layer (113 – FIG. 2; [0038]; or alternatively, portion of dielectric layer 110 downward from lowermost internal electrode layer – FIG. 2) configured to adjoin the first surface (FIG. 2), and the bypass portion and the conductive portion are positioned in the lowermost end dielectric layer (FIG. 2).
In regards to claim 14, Lee further discloses wherein: the lowermost end dielectric layer (portion of dielectric layer 110 downward from lowermost internal electrode layer – FIG. 2) has a larger thickness than the dielectric layer positioned between the plurality of internal electrodes (seen in FIG. 2).
In regards to claim 15, Lee further discloses wherein: the connection electrode includes a plurality of connection electrodes (131, 132 – FIG. 2) spaced apart from each other (FIG. 2).
In regards to claim 16, Lee discloses an electronic component comprising: a capacitor body (110 – FIG. 2; [0036]) comprising: a dielectric layer (110 – FIG. 2; [0036]; noting that the dielectric of the capacitor body as a whole or any portion thereof is being considered the “dielectric layer”); a plurality of internal electrodes comprising a plurality of first internal electrodes and a plurality of second internal electrodes (121, 122 – FIG. 2; [0036]) alternately positioned in a stacking direction (Z – FIG. 2) and spaced apart from one another with the dielectric layer interposed therebetween (FIG. 2); and a first surface, a second surface, a third surface, and a fourth surface, wherein the first and second surfaces (respectively, downward and upward surfaces of 110 as seen in FIG. 2) face each other in the stacking direction; both of the third and the fourth surface are outermost are outermost surfaces of the capacitor body (respectively, leftward and rightward surfaces of 110 as seen in FIG. 2); a connection electrode (131, 133, 135 – FIG. 2; [0036], [0043]) comprising: a main junction portion (131 – FIG. 2) extending in the stacking direction and configured to penetrate the plurality of internal electrodes (FIGs. 2-3); a bypass portion (133 – FIG. 2) connected to the main junction portion and extending in a direction substantially crossing the stacking direction (rightward in FIG. 2); and an end (lowermost end of 135 – FIG. 2; [0043]) extending from the first surface (FIG. 2), wherein the connection electrode is connected to the plurality of internal electrodes in the capacitor body (FIGs. 2-3); and an external electrode (141 – FIG. 2; [0036]) positioned on the first surface and connected to the connection electrode (FIG. 2).
Lee fails to disclose the plurality of first internal electrodes extend from the third surface and the plurality of second internal electrodes extend from the fourth surface.
Sakurai discloses a capacitor body (4 – FIG. 1C), a plurality of internal electrodes comprising a plurality of first internal electrodes and a plurality of second internal electrodes (12 – FIG. 1C; [0044]) alternately positioned in a stacking direction (Z – FIG. 1C) and spaced apart from one another with the dielectric layer interposed therebetween (FIG. 1C); a first surface, a second surface, a third surface, and a fourth surface, wherein the first and second surfaces (respectively, 4d and 4c as seen in FIG. 1C) face each other in the stacking direction; both of the third and the fourth surface are outermost are outermost surfaces of the capacitor body (respectively, 4a and 4b as seen in FIG. 1C), the plurality of first internal electrodes extend from the third surface (12a extending from 4a as seen in FIG. 1C) and the plurality of second internal electrodes extend from the fourth surface (12b extend from 4b as seen in FIG. 1C).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to utilize the extended internal electrodes of Sakurai with the capacitor of Lee for the purpose of adding a reinforcement layer to improve strength, without increasing the size of the capacitor ([108]-[110]).
In regards to claim 17, Lee further discloses wherein: the connection electrode further comprises a conductive portion (portion connecting portion 133 and lowermost end of 135 as seen in FIG. 2) connected to the bypass portion (FIG. 2), in a cross-section of the electronic component in the stacking direction and a direction orthogonal to the stacking direction (cross-section of, for example FIG. 2), a central axis of the main junction portion along the stacking direction is offset from a central axis of the conductive portion along the stacking direction (seen in FIG. 2).
In regards to claim 18, Lee further discloses wherein: in a cross-section of the electronic component in the stacking direction and a direction orthogonal to the stacking direction (cross-section of, for example FIG. 2), the main junction portion and the end do not overlap each other along the stacking direction (seen in FIG. 2).
In regards to claim 19, Lee further discloses wherein the main junction portion penetrates through at least one internal electrode among the plurality of internal electrodes (FIGs. 2-3).
In regards to claim 20, Lee as modified discloses the limitations of claims 1, but fails to explicitly disclose wherein: a second internal electrode among the plurality of second internal electrode includes a first end and a second end opposing the first end, the first end is disposed closer to the third surface than the second end, and the main junction portion is positioned between the third surface and the first end.
Sakurai discloses a second internal electrode (12b – FIG. 1C) among the plurality of second internal electrode includes a first end (FIG. 1C, end facing 4a) and a second end (FIG. 1C, end at fourth surface 4b) opposing the first end, the first end is disposed closer to the third surface than the second end (FIG. 1C), and the main junction portion (52 – FIG. 1C) is positioned between the third surface and the first end (FIG. 1C).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to utilize the configuration of Sakurai with the capacitor of Lee for the purpose of providing easy manufacturing, whereby a via hole of a single size may be used to connect the connection electrode with the proper internal electrode layers.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 20190066922) in view of Sakurai et al. (US 20200135400) and further in view of Seo et al. (US 20180233287).
In regards to claim 8, Lee as modified fails to expressly disclose, in entirety, wherein: the first connection electrode includes a plurality of first connection electrodes, the second connection electrode includes a plurality of second connection electrodes, the plurality of first connection electrodes is spaced apart from each other in the second direction, and the plurality of second connection electrodes is spaced apart from each other in the second direction.
Seo teaches wherein: the first connection electrode includes a plurality of first connection electrodes (121 – FIG. 1; [0021]), the second connection electrode includes a plurality of second connection electrodes (122 – FIG. 1; [0021]), the plurality of first connection electrodes is spaced apart from each other in the second direction (Y – FIG. 1), and the plurality of second connection electrodes is spaced apart from each other in the second direction (seen in FIG. 1).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Seo with Lee as modified to incorporate the first connection electrode includes a plurality of first connection electrodes, the second connection electrode includes a plurality of second connection electrodes, the plurality of first connection electrodes is spaced apart from each other in the second direction, and the plurality of second connection electrodes is spaced apart from each other in the second direction as taught by Seo in the structure taught by Lee as modified, as one having ordinary skill in the art would have been motivated to do this with a reasonable expectation of success because such a combination and/or modification allows for providing a capacitor component with improved equivalent series inductance (ESL) and equivalent series resistance (ESR) values (Seo: [0010]).
Response to Arguments
Applicant's arguments filed April 06, 2026 have been fully considered but they are not persuasive.
Applicant’s arguments with respect to the claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Applicant’s arguments centered around the amended claim language. The amendment overcame the 102 rejection, but led to a 103 rejection using Sakurai as the secondary reference, as shown above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Timothy J Dole whose telephone number is (571)272-2229. The examiner can normally be reached M-F 6:30am-2:30pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrea Wellington can be reached at (571)272-4483. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Timothy J. Dole/ Supervisory Patent Examiner, Art Unit 2847
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