Prosecution Insights
Last updated: October 01, 2026
Application No. 18/592,860

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE

Non-Final OA §103
Filed
Mar 01, 2024
Priority
Mar 20, 2023 — JP 2023-044617
Examiner
MORA, ONASIS
Art Unit
4100
Tech Center
4100
Assignee
KIOXIA Corporation
OA Round
1 (Non-Final)
Grant Probability
Favorable
1-2
OA Rounds

Examiner Intelligence

Grants only 0% of cases
0%
Career Allowance Rate
0 granted / 0 resolved
-60.0% vs TC avg
Minimal +0% lift
Without
With
+0.0%
Interview Lift
resolved cases with interview
Typical timeline
Avg Prosecution
13 currently pending
Career history
5
Total Applications
across all art units
This examiner has no resolved cases yet (career too new); statute-level performance unavailable. The Grant Probability card shows Tech Center averages instead.

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Priority Acknowledgment is made of applicant's claim for foreign priority based on an application filed in Japan on March 20, 2023. It is noted, however, that applicant has not filed a certified copy of the JP2023-044617 application as required by 37 CFR 1.55. Election/Restrictions Applicant’s election without traverse of Species A, NS Subspecies 2, A1, and AA1 in the reply filed on July 14, 2026 is acknowledged. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-6, 9 -11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wimplinger et al (US 20250153481) in view of Kakehata (US 7781306). Regarding Claim 1, Wimplinger teaches a method for manufacturing a semiconductor device (no associated element number, Fig.1a-5f, para [0001]-[0002]), the method comprising: preparing a first substrate (6, Fig. 4b, para [0175]) provided with a first film (14, Fig. 4b, para [0175]); forming a second substrate (1, Fig. 4b, para [0175])); forming a third film (2, Fig. 4b, para [0175]) on or above the second film; forming a fourth film (14, Fig. 4b, para [0175]) on or above the third film (2, Fig. 4b, para [0175]); forming a stacked body by bonding a main surface of the first film (14, Fig. 4c, para [0176]) and a main surface of the fourth film (14, Fig. 4c, para [0176]); performing irradiation with a laser beam (10 &11, Fig. 4h, para [0181]) from a side of the second substrate of the stacked body (1, Fig. 4h, para [0181] &[0034]); and separating the second substrate (1, Fig. 4h, para [0181]), wherein the fourth film (14, Fig. 4b, para [0175]) each includes a first material (14, Fig. 1b, para [0054]), and the third film (2, Fig. 4b, para [0175]) includes a second material (2, Fig. 1a, para [0080]-[0086]) different from the first material, the fourth film (14, Fig. 4b, para [0175]) and the third film (2, Fig. 4b, para [0175]) have different composition (14, para [0054]; 2, para [0080]-[0086]). Wimplinger does not explicitly teach wherein a forming a second film on or above a second substrate wherein the second film and the third film have different composition wherein the removal of the second substrate includes at least portion of the second film. However, Kakehata, in a similar field of bonding and debonding substrates with use of laser teaches examples of bonding of substrates each having multiple film layers (Kakehata, Fig. 4A-4C, para (78)-(85)), as well as the debonding of substrates wherein the removal of a substrate can also include multiple attached film portions (Kakehata, Fig. 6C, para (104)). Kakehata also teaches embodiments of bonding of substrates not having multiple film layers (Kakehata, Fig. 2A-2C, para (34)-(41), and wherein the removal of a substrate can also include multiple attached film portions. Kakehata also teaches the use of a barrier film (Kakehata, 122, Fig. 2B, para (83)) to block metal diffusion impurities. Therefore, it would have been prima facie obvious to one of ordinary skill at the time of the effective filing date of the application, to add a second film on or above a second substrate with a different composition than the third film wherein the removal of the second substrate includes at least a portion of the second film, to Wimplinger in view of Kakehata for the purpose of blocking metal impurities diffusing onto the substrate and ultimately making the step of recycling the substrate more efficient. Regarding Claim 2, Wimplinger teaches the method for manufacturing a semiconductor device according to claim 1 (no associated element number, Fig. 1a-5f, para [0001]-[0002]), wherein a linear expansivity of the second material (2, Fig. 1a, para [0080]-[0086]) is larger than a linear expansivity (Fig. 1a-5f, para [0107]; linear expansion is entirely dependent on thermal expansion) of the first material (14, Fig. 1b, para [0054]). Regarding Claim 3, the combination of Wimplinger and Kakehata teaches the method for manufacturing a semiconductor device according to claim 1 (no associated element number, Fig.1a-5f, para [0001]-[0002]). The combination of Wimplinger and Kakehata does not explicitly teach wherein thermal conductivity of the second material is higher than thermal conductivity of the first material. However, the examiner notes that Wimplinger explicitly discloses that the first material is an oxide, most preferably of a silicon oxide (para [0054]) and that the second material is “semiconductors, in particular Ge [0083] metals, in particular [0084] Ti, W, Al, Ta, Cu [0085] nitrides, in particular [0086] TiN, TaN, WN, W.sub.2N, WN.sub.2,” para [0080]-[0086]). Therefore, the same materials are treated the same way and therefore, the same results would be obtained. Accordingly, the combination of Wimplinger and Kakehata inherently discloses a material combination wherein thermal conductivity of the second material is higher than the thermal conductivity of the first material. Regarding Claim 4, Wimplinger teaches the method for manufacturing a semiconductor device according to claim 1 (no associated element number, Fig.1a-5f, para [0001]-[0002]). The combination of Wimplinger and Kakehata does not explicitly teach wherein thermal diffusivity of the second material is larger than thermal diffusivity of the first material. However, the examiner notes that Wimplinger explicitly discloses that the first material is an oxide, most preferably of a silicon oxide (para [0054]) and that the second material is “semiconductors, in particular Ge [0083] metals, in particular [0084] Ti, W, Al, Ta, Cu [0085] nitrides, in particular [0086] TiN, TaN, WN, W.sub.2N, WN.sub.2,” para [0080]-[0086]). Therefore, the same materials are treated the same way and therefore, the same results would be obtained. Accordingly, the combination of Wimplinger and Kakehata inherently discloses a material combination wherein thermal diffusivity of the second material is higher than the thermal diffusivity of the first material. Regarding Claim 5, Wimplinger teaches the method for manufacturing a semiconductor device according to claim 1 (no associated element number, Fig.1a-5f, para [0001]-[0002]), wherein the first material (14, Fig. 1b, para [0054]) includes a semiconductor oxide (para [0162]), and the second material (2, Fig. 1a, para [0080]-[0086]) includes, as a main component, a material including at least one of a semiconductor (para [0080]-[0086]), a semiconductor nitride, a metal (para [0080]-[0086]), a metal oxide, or a metal nitride (para [0080]-[0086]). Regarding Claim 6, the method for manufacturing a semiconductor device according to claim 5 (no associated element number, Fig.1a-5f, para [0001]-[0002]), wherein the first substrate (6, Fig. 3a, para [0053]; “wafer” where silicon wafer is implied) and the second substrate (1, fig. 1a, para [0030]) are silicon wafer. Wimplinger teaches various ranges that overlap the ranges of claim 6 (para [0038]) but does not explicitly teach wherein the wavelength of the laser beam is between 9.2 µm and 10.8 µm. However, “In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists (see MPEP2144.05, I). Therefore, it would have been obvious to one of ordinary skill at the time of the effective filing date of the application for Wimplinger to have a laser beam wavelength between 9.2 µm and 10.8 µm. Regarding Claim 9, Wimplinger teaches the method for manufacturing a semiconductor device according to claim 1 (no associated element number, Fig.1a-5f, para [0001]-[0002]), wherein the third film has repeated patterns when seen in plan view (no associated element number, Fig. 3d, Fig. 4h, Fig. 5d, para [0091). Regarding Claim 10, Wimplinger teaches the method for manufacturing a semiconductor device according to claim 9 (no associated element number, Fig.1a-5f, para [0001]-[0002]), wherein the pattern has a linear shape (Fig. 3d, Fig. 4h, Fig. 5d, para [0091]), a dot shape, a cross shape, an L shape, and a T shape in plan view. Regarding Claim 11, Wimplinger teaches the method for manufacturing a semiconductor device according to claim 1 (no associated element number, Fig.1a-5f, para [0001]-[0002]), and a second substrate (6, Fig. 6b, para [0175]). Wimplinger does not explicitly teach wherein the method comprising: before forming a second film on or above a second substrate; removing a fifth film from the second substrate; wherein the fifth film includes the first material and the fifth film and the third film have different composition. However, Kakehata, in a similar field of bonding and debonding substrates with use of laser teaches examples of bonding of substrates each having multiple film layers (Kakehata, Fig. 4A-4C, para (78)-(85)), as well as the debonding of substrates wherein the removal of a substrate can also include multiple attached film portions (Kakehata, Fig. 6C, para (104)). Kakehata also teaches embodiments of bonding of substrates not having multiple film layers (Kakehata, Fig. 2A-2C, para (34)-(41), and wherein the removal of a substrate can also include multiple attached film portions. Kakehata also teaches the use of a barrier film and bonding layer (Kakehata, 122 & 124, Fig. 2B, para (80)-(83)) to block metal diffusion impurities. Therefore, it would have been prima facie obvious to one of ordinary skill at the time of the effective filing date of the application, to add a second film and fifth film on or above a second substrate and both with a different composition than the third film wherein the fifth film includes the first material and wherein the removal of the second substrate includes at least a portion of the second film, to Wimplinger in view of Kakehata for the purpose of blocking metal impurities diffusing onto the substrate and ultimately making the step of recycling the substrate more efficient. PNG media_image1.png 202 450 media_image1.png Greyscale PNG media_image2.png 281 768 media_image2.png Greyscale Claim(s) 6-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wimplinger et al (US 20250153481) and Kakehata (US 7781306) as applied to claim 1-6, 9-11 above, and further in view of Shimoda et al (US 7285476). Regarding Claim 7, Wimplinger teaches the method for manufacturing a semiconductor device according to claim 5 (no associated element number, Fig.1a-5f, para [0001]-[0002]). Wimplinger does not explicitly teach wherein the second material includes at least one of a polycrystalline material of a semiconductor or amorphous material of a semiconductor. However, Shimoda in a field of similar endeavor of stacked semiconductor device substrates and debonding thin films using laser, discloses a second material (separation layer 2, para (31)) that includes an amorphous material of a semiconductor (para (31)-(39)). Therefore, it would have been obvious to one of ordinary skill at the time of the effective filing date of the application, to modify Wimplinger in view of Shimoda and include a material embodiment of an amorphous material of a semiconductor since the selection of a known material based on its suitability for its intended use supports a prima facie obviousness determination (MPEP 2144.07). Regarding Claim 8, Wimplinger teaches the method for manufacturing a semiconductor device according to claim 7 (no associated element number, Fig.1a-5f, para [0001]-[0002]), Wimplinger does not explicitly teach wherein the second material includes at least one of polysilicon or amorphous silicon. However, However, Shimoda in a field of similar endeavor of stacked semiconductor device substrates and debonding thin films using laser, discloses a second material (separation layer 2, para (31)) that includes amorphous silicon (para (31)-(39)). Therefore, it would have been obvious to one of ordinary skill at the time of the effective filing date of the application, to modify Wimplinger in view of Shimoda and include a material embodiment of amorphous silicon of a semiconductor since the selection of a known material based on its suitability for its intended use supports a prima facie obviousness determination (MPEP 2144.07). Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wimplinger et al (US 20250153481) and Kakehata (US 7781306) as applied to claim 1-6, 9-11 above, and further in view of Or-Bach (US 20120091587). Regarding Claim 12, Wimplinger teaches the method for manufacturing a semiconductor device according to claim 11 (no associated element number, Fig.1a-5f, para [0001]-[0002]). Wimplinger does not explicitly teach wherein the removing the fifth film However, Kakehata, in a similar field of bonding and debonding substrates with use of laser teaches examples of bonding of substrates each having multiple film layers (Kakehata, Fig. 4A-4C, para (78)-(85)), as well as the debonding of substrates wherein the removal of a substrate can also include multiple attached film portions (Kakehata, Fig. 6C, para (104)). Kakehata also teaches embodiments of bonding of substrates not having multiple film layers (Kakehata, Fig. 2A-2C, para (34)-(41), and wherein the removal of a substrate can also include multiple attached film portions. Kakehata also teaches the use of a barrier film and bonding layer (Kakehata, 122 & 124, Fig. 2B, para (80)-(83)) to block metal diffusion impurities. Therefore, it would have been prima facie obvious to one of ordinary skill at the time of the effective filing date of the application, to add fifth film on or above a second substrate, to Wimplinger in view of Kakehata for the purpose of blocking metal impurities diffusing onto the substrate and ultimately making the step of recycling the substrate more efficient. PNG media_image1.png 202 450 media_image1.png Greyscale PNG media_image2.png 281 768 media_image2.png Greyscale Wimplinger does not explicitly teach wet-etching the fifth film. However, in a field of similar endeavor of semiconductor fabrication using stacking methods including debonding and sacrificial substrates Or-Bach teaches a method of wet chemistry treatments to etch a donor substrate to be reused for more layer transfers (para [0446]). Therefore, it would have been obvious to one of ordinary skill at the time of the effective filing date of the application, to modify Wimplinger in view of Or-Bach and use wet-etching techniques on the fifth film for the further advantage of creating a reusable donor substrate, saving costs and material in the process. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Thermal atomic layer etching: A review NPL document used to show that certain etching techniques and certain materials coinciding with etching techniques are common in the art for one of ordinary skill. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ONASIS MORA whose telephone number is (571)270-0786. The examiner can normally be reached Monday-Friday 9am-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at (571) 272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ONASIS MORA/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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Prosecution Timeline

Mar 01, 2024
Application Filed
Aug 25, 2026
Non-Final Rejection mailed — §103 (current)

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1-2
Expected OA Rounds
Grant Probability
Low
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