DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is sent in response to Applicant’s Communication received 3/1/2024 for application number 18/593,059. The Office hereby acknowledges receipt of the following and placed of record in file: Specification, Drawings, Abstract, Oath/Declaration, claims, and certified copy of foreign priority application.
Claims 11 – 30 are presented for examination.
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Drawings
Examiner contends that the drawings filed 3/1/2024 are acceptable for examination proceedings.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 11-12, 14-16, 20, 23-24, and 26-27 is/are rejected under 35 U.S.C. 103 as being unpatentable over Seok et al. (hereinafter as Seok) PGPUB 2021/0271276, and further in view of Brown USPAT 11,262,834 and Zakaria et al. (hereinafter as Zakaria) PGPUB 2017/0006003.
As per claim 11, Seok teaches an apparatus comprising:
a plurality of circuit domains, each domain including logic circuitry to perform one or more tasks in response to inputs, and to operate under power conditions that are different than power conditions under which another domain of the plurality of domains operates [0009, 0028, 0029, 0046, and 0048-0051: (application processor (AP) have a plurality of power domains that operate at different voltages, each having processing circuitry to perform respective tasks; AP receives input from the PMIC through system interface 12))]; and
power management circuitry configured to operate the plurality of circuit domains, including controlling the sequence of respective operations carried out by each domain of the plurality of circuit domains, by a sequence corresponding to both a programmed counter value and a counter circuit output value [0110: (PMIC performs power on or power off sequence in power domains of AP; generation order of output voltages may be set in an order corresponding to a counting value and a counting operation by a counter)].
Seok does not explicitly teach power management circuitry configured to output respective commands for operating the plurality of circuit domains, by issuing each of the commands in a sequence and a counter value assigned to each command. Seok’s PMIC provides input to the AP and controls voltages of the PMIC in sequence, but does not appear to provide commands for operating the power domains or providing a number or ID for each command.
Brown teaches a power controller that controls various power domain operations. Brown is thus similar to Seok. Brown further teaches power management circuitry configured to output respective commands for operating the plurality of circuit domains [col. 4 line 60 – col. 5 line 2 and col. 8 line 66 – col. 9 line 3: (power controller provides request to a controller/processor of power domain to prepare the power domain for a low power mode)].
The combination of Seok with Brown leads to Seok’s PMIC transmitting commands to each power domain to prepare for changes in power to each power domain.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Brown’s teachings of the PMIC transmitting request to a power domain when changing the power provided to a power domain in Seok. One of ordinary skill in the art would have been motivated to have a PMIC provide indication to the power domain prior to a change in power allocation to the power domain because removing the power to the power domain with no warning could result in components of the power domain being left in an unstable state and could result in data corruption or loss [Brown col. 4 lines 60-63.]
Seok and Brown do not explicitly teach a counter value assigned to each command. Seok and Brown describes a PMIC providing requests/commands to the power domain as part of a negotiation procedure for changing power allocation to the power domain, but Seok and Brown do not specify whether the requests/commands have a counter value assigned to them.
Zakaria teaches transmission of data for negotiation and providing requests. Zakaria is thus similar to Seok and Brown. Zakaria further teaches a counter value assigned to each command [0203: (each instance of command transmitted may be assigned a different request ID; incrementing a counter and using the counter value as the request ID)]. Zakaria teaches assigning an identifier to each request using a counter value.
The combination of Seok and Brown with Zakaria leads to the PMIC performing power on or off sequences of various power domains in an application processor in an order corresponding to a count value of a counter by transmitting requests, each request having an ID of the counter value, to processors of the corresponding power domains to prepare for changes in power.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Zakaria’s teachings of assigning counter value as an identifier of a request in Seok and Brown. One of ordinary skill in the art would have been motivated to assign a counter value as the request identifier in Seok and Brown because it allows the PMIC to better manage and handle the various requests to the different power domains according to an order of the counting value. In other words, it assists in referencing the sequence or order in which requests are provided to the different power domains to produce the generation order of output voltages to the power domains.
As per claim 12, Seok, Brown, and Zakaria teach the apparatus of claim 11, further including a counter circuit configured to output the counter circuit output value [Seok 0110: counter value of counter].
As per claim 14, Seok, Brown, and Zakaria teach the apparatus of claim 11, wherein each of the command inputs has a different programmed counter value, and the power management circuitry is configured to issue commands in a sequence corresponding to the counter values of each command beginning with a lowest counter value and continuing in sequence with respectively higher counter values [Zakaria 0102: increasing counter value; 0134: (counter value is incremented for each data packet); and 0203: (incremented counter and using the counter value as a request ID; thus different commands have different counter values and it starts with a lower value and increments for each command in sequence).
As per claim 15, Seok, Brown, and Zakaria teach the apparatus of claim 11, wherein the power management circuitry is configured and arranged with the circuit domains to power each circuit domain off and on separately from the other domains [Seok 0118: (power domain groups may be powered off randomly or simultaneously; thus power domains may be powered off individually (separately from other domains) or may be powered off together)].
As per claim 16, Seok, Brown and Zakaria teach the apparatus of claim 11, wherein the power management circuitry is configured and arranged with the circuit domains to power each circuit domain under a power condition that is different than a power condition at which another one of the domains is operated [Seok 0003: (PMIC output various output voltages to the rails for the different domains) and 0048: (voltage having various target levels)].
As per claim 20, Seok, Brown, and Zakaria teach the apparatus of claim 11, wherein the power management circuitry is configured to output the respective commands by outputting commands to independently power each of the circuit domains on and off by issuing commands in a sequence that causes the respective circuit domains to carry out power on and power off functions [Seok 0110 and 0118: (power domains are powered off in sequence and may be powered off independently) and Brown col. 4 line 60 – col. 5 line 2 and col. 8 line 66 – col. 9 line 3: (commands are provided prior to starting a power down of a power domain that causes the power domain to prepare for a reduction in power to the power domain)].
Claim 23 is similar in scope to claim 11 as addressed above and is thus rejected under the same rationale.
Claim 24 is similar in scope to claim 12 as addressed above and is thus rejected under the same rationale.
Claim 26 is similar in scope to claim 14 as addressed above and is thus rejected under the same rationale.
Claim 27 is similar in scope to claim 16 as addressed above and is thus rejected under the same rationale.
Claim(s) 17-19 and 28-29 is/are rejected under 35 U.S.C. 103 as being unpatentable over Seok et al. (hereinafter as Seok) PGPUB 2021/0271276 in view of Brown USPAT 11,262,834 and Zakaria et al. (hereinafter as Zakaria) PGPUB 2017/0006003, and further in view of Yokoyama et al. (hereinafter as Yokoyama) PGPUB 2010/0325469.
As per claim 17, Seok, Brown, and Zakaria teach the apparatus of claim 11.
Seok, Brown, and Zakaria do not teach wherein the power management circuitry is configured to store counter value data correlating each of the respective commands to a specific counter value, and for each of the respective commands to replace the stored counter value data with a new counter value in response to a reprogramming input specifying the new counter value and the command. Seok, Brown, and Zakaria describes a counter but does not describe the details for setting the counter value.
Yokoyama teaches setting an out-of-order instruction number as the value of a counter in clock circuitry that reduces power consumption in CPU. Yokoyama is thus similar to Seok, Brown, and Zakaria because they utilize counter values as part of their procedure to reduce power consumption at a CPU. Yokoyama further teaches store counter value data correlating each of the respective commands to a specific counter value, and for each of the respective commands to replace the stored counter value data with a new counter value in response to a reprogramming input specifying the new counter value and the command [0071, 0092, 0095, and 0150-0151: (counter stores a number, and when it reaches 0, set counter value as the out-of-order instruction number; thus the stored counter value is replaced with a new counter value in response to new instruction)].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Yokoyama’s teachings of setting counter values in Seok, Brown, and Zakaria. One of ordinary skill in the art would have been motivated to set and change counter values in Seok, Brown, and Zakaria because it would assist in out-of-order execution and assist with memory stalls [Yokoyama 0151].
As per claim 18, Seok, Brown, and Zakaria teach the apparatus of claim 11.
Seok, Brown, and Zakaria do not teach further including a clock circuit configured to output a clock signal on which the circuit domains operate, wherein the power management circuitry is configured to output respective commands for the clock circuit in response to a programmed counter value for the clock circuit command corresponding to the counter value. Although Seok describes clock circuitry in the PMIC, Seok does not mention providing clock signals to the CPU in the power domains.
Yokoyama teaches setting an out-of-order instruction number as the value of a counter in clock circuitry that reduces power consumption in CPU. Yokoyama is thus similar to Seok, Brown, and Zakaria because they utilize counter values as part of their procedure to reduce power consumption at a CPU. Yokoyama further teaches a clock circuit configured to output a clock signal on which the circuit domains operate [FIG. 2 clock control device 230], wherein the power management circuitry is configured to output respective commands for the clock circuit in response to a programmed counter value for the clock circuit command corresponding to the counter value [FIG. 2, 0072, 0094, and 0096: (based on comparison of counter to a particular counter value, low clock signal is provided to CPU)]
The combination of Seok, Brown, and Zakaria with Yokoyama leads to each PMIC including clock control circuitry that provides clock signals to the CPU in each power domain based on comparison of the counter values.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Yokoyama’s teachings of comparing counter value and providing a clock to a CPU based on the comparison in Seok, Brown, and Zakaria. One of ordinary skill in the art would have been motivated to provide the clock control circuitry in Seok, Brown, and Zakaria because it allows for further reduction in power reduction by controlling clocks provided to each domain of the application processor.
As per claim 19, Seok, Brown, Zakaria, and Yokoyama teach the apparatus of claim 18, wherein the power management circuitry is configured and arranged with the clock circuit to variably control the frequency of the clock signal by outputting respective clock circuit commands specifying different frequencies based on different counter values programmed for each of the respective clock signals and a counter value the counter circuit output value [Yokoyama 0070, 0096, 0098, 0100, and 0138: (frequency of clock signal may vary based on comparison to counter value)].
Claim 28 is similar in scope to claim 17 as addressed above and is thus rejected under the same rationale.
Claim 29 is similar in scope to claim 18 as addressed above and is thus rejected under the same rationale.
Allowable Subject Matter
Claims 13, 21-22, 25, and 30 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Applicant is reminded that in amending in response to a rejection of claims, the patentable novelty must be clearly shown in view of the state of the art disclosed by the references cited and the objections made. Applicant must also show how the amendments avoid such references and objections. See 37 CFR §1.111(c).
Lee et al. (PGPUB 2011/0276812) teaches a PMU controlling operation of multiple power domains through various finite state machines and a central sequencer for activation sequence of the finite state machines.
Mishra et al. (USPAT 11,106,620) teaches a unique identifier based on an output of the counter [claim 26].
Zhang et al. (PGPUB 2017/0150454) teaches power control commands numbered according to a sending sequence.
Byun et al. (PGPUB 2015/0033047) teaches PMU including a central sequencer that determines activation sequence or order of finite state machines for power domains.
More et al. (PGPUB 2011/0022859) teaches PMIC that provides sequencing control over power blocks for powering or depowering some power domains.
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/DANNY CHAN/Primary Examiner, Art Unit 2175