Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In view of the Appeal Brief filed on 05/05/2026, PROSECUTION IS HEREBY REOPENED. New grounds of rejection are set forth below. To avoid abandonment of the application, appellant must exercise one of the following two options:
(1) file a reply under 37 CFR 1.111 (if this Office action is non-final) or a reply under 37 CFR 1.113 (if this Office action is final); or,
(2) initiate a new appeal by filing a notice of appeal under 37 CFR 41.31 followed by an appeal brief under 37 CFR 41.37. The previously paid notice of appeal fee and appeal brief fee can be applied to the new appeal. If, however, the appeal fees set forth in 37 CFR 41.20 have been increased since they were previously paid, then appellant must pay the difference between the increased fees and the amount previously paid.
A Supervisory Patent Examiner (SPE) has approved of reopening prosecution by signing below.
/BORIS GORNEY/ Supervisory Patent Examiner, Art Unit 2154
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory obviousness-type double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the conflicting application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement.
Effective January 1, 1994, a registered attorney or agent of record may sign a terminal disclaimer. A terminal disclaimer signed by the assignee must fully comply with 37 CFR 3.73(b).
Claims 1, 2, 5, 8, 13, 14, 15, 18 and 20 are rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claims 1, 2, 6, 7, 11, 16, 17 and 18, respectively, of US Pat. 12,271,359. See table below.
US Patent 12,271,359
Instant Application
1. A storage system, comprising:
a primary storage node comprising a primary processing device and one or more authorities that determine types of erasure coding applied to data stored in the storage system, the primary storage node communicatively coupled to a secondary storage node, the secondary storage node comprising a secondary processing device and a set of non-volatile memory modules; and the primary processing device configured to: identify one or more storage operations to be performed on the set of non-volatile memory modules of the secondary storage node; and
transmit one or more instructions to the secondary storage node to perform the one or more storage operations, the one or more storage operations performed by the secondary processing device and the one or more instructions indicating one or more addresses in the set of non-volatile memory modules where the one or more storage operations are to be performed.
2. The storage system of claim 1, wherein the one or more storage operations are further performed by a set of device hosts of the secondary storage node and the set of device hosts manage the set of non-volatile memory modules of the secondary storage node.
6. The storage system of claim 1, wherein the secondary processing device has less processing power than the primary processing device.
7. The storage system of claim 1, wherein the secondary storage node lacks authorities.
11. A method, comprising: identifying, by a primary storage node comprising one or more authorities that determine types of erasure coding applied to data stored in a storage system, one or more storage operations to be performed on a set of non-volatile memory modules of a secondary storage node, the primary storage node communicatively coupled to the secondary storage node, the primary storage node comprising a primary processing device, and the secondary storage node comprising a secondary processing device; and
transmitting one or more instructions to the secondary storage node to perform the one or more storage operations, the one or more storage operations performed by the secondary processing device and the one or more instructions indicating one or more addresses in the set of non-volatile memory modules where the one or more storage operations are to be performed.
12. The method of claim 11, wherein the one or more storage operations are further performed by a set of device hosts of the secondary storage node and the set of device hosts manage the set of non-volatile memory modules of the secondary storage node.
16. The method of claim 11, wherein the secondary processing device has less processing power than the primary processing device.
17. The method of claim 11, wherein the secondary storage node lacks authorities.
18. A non-transitory computer readable storage medium storing instructions, which when executed, cause a processing device of a primary storage node to: identify, by the primary storage node comprising one or more authorities that determine types of erasure coding applied to data stored in a storage system, one or more storage operations to be performed on a set of non-volatile memory modules of a secondary storage node, the primary storage node communicatively coupled to the secondary storage node and the secondary storage node comprising a secondary processing device; and
transmit one or more instructions to the secondary storage node to perform the one or more storage operations, the one or more storage operations performed by the secondary processing device and the one or more instructions indicating one or more addresses in the set of non-volatile memory modules where the one or more storage operations are to be performed.
1. A storage system, comprising:
a primary storage node comprising a primary processing device and a first set of non-volatile memory modules; and
a secondary storage node comprising a secondary processing device a second set of non-volatile memory modules, the second storage node communicatively coupled to the primary storage node, the secondary storage node performs storage operations based on instructions received from the primary storage node; the primary processing device to: receive a request to access one or more of the first set of non-volatile memory modules and the second set of non-volatile memory modules; and
transmit a set of instructions to perform a set of storage operations to the secondary storage node based on the request.
2. The storage system of claim 1, wherein the one or more storage operations are further performed by a set of device hosts of the secondary storage node and the set of device hosts manage the set of non-volatile memory modules of the secondary storage node.
5. The storage system of claim 1, wherein the secondary processing device has less processing power than the primary processing device.
8. The storage system of claim 7, wherein the secondary storage node lacks authorities.
13. A method, comprising: receiving, by a primary storage node comprising a primary processing device and a first set of non-volatile memory modules, a request to access one or more of the first set of non-volatile memory modules and a second set of non-volatile memory modules; and
transmitting a set of instructions to perform a set of storage operations to a secondary storage node based on the request, the secondary storage node comprising a secondary processing device the second set of non-volatile memory modules, the second storage node communicatively coupled to the primary storage node, the secondary storage node performs storage operations based on the set of instructions received from the primary storage node.
14. The method of claim 13, wherein the one or more storage operations are further performed by a set of device hosts of the secondary storage node and the set of device hosts manage the set of non-volatile memory modules of the secondary storage node.
15. The method of claim 13, wherein the secondary processing device has less processing power than the primary processing device.
18. The method of claim 17, wherein the secondary storage node lacks authorities.
20. A non-transitory computer readable storage medium storing instructions, which when executed, cause a processing device of a primary storage node to: receive a request to access one or more of a first set of non-volatile memory modules of the primary storage node and a second set of non-volatile memory modules; and
transmit a set of instructions to perform a set of storage operations to a secondary storage node based on the request, the secondary storage node comprising a secondary processing device and the second set of non-volatile memory modules, the second storage node communicatively coupled to the primary storage node, the secondary storage node performs storage operations based on the set of instructions received from the primary storage node.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103(a) as being unpatentable over Mehra (US Pub. 2023/0195926) in view of Pagenberg (DE 2022002976U1).
Regarding claim 1, Mehta discloses a storage system, comprising: a primary storage node comprising a primary processing device and a first set of non-volatile memory modules (Fig. 1); and
a secondary storage node comprising a secondary processing device a second set of non-volatile memory modules, the second storage node communicatively coupled to the primary storage node, the secondary storage node performs storage operations based on instructions received from the primary storage node, the primary processing device to (¶ [0255]; be configured to receive client write and read requests from the primary storage subsystem, and direct those requests to the secondary storage for servicing):
receive a request to access one or more of the first set of non-volatile memory modules and the second set of non-volatile memory modules (¶ [0255]; receiving a request from the primary storage); and
transmit a set of instructions to perform a set of storage operations to the secondary storage node based on the request (¶ [0255] directing those requests to the secondary storage for servicing).
Mehta does not explicitly disclose a non-volatile memory; however, Pagenberg discloses at least a non-volatile memory for storage(¶ [0017]; including double data rate DRAM (DDR, DDR2, DDR3, DDR4 DRAM, etc.), non-volatile memory, graphics DRAM)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Pagenberg into Mehta for memory operation (¶ [0017]).
Regarding claim 2, Mehta in view of Pagenberg discloses the storage system of claim 1, wherein the one or more storage operations are further performed by a set of device hosts of the secondary storage node and the set of device hosts manage the set of non-volatile memory modules of the secondary storage node (Mehta: Fig. 1; Pagenberg, ¶ [0017]).
Regarding claim 3, Mehta in view of Pagenberg discloses the storage system of claim 1, wherein the primary storage node and the secondary storage node are located within a chassis (Mehta, Fig. 2B).
Regarding claim 4, Mehta in view of Pagenberg discloses the storage system of claim 1, wherein the primary storage node and the secondary storage node are located in different chassis (Fig. 1).
Regarding claim 5, Mehta in view of Pagenberg discloses the storage system of claim 1, wherein the secondary processing device has less processing power than the primary processing device (Pagenberg discloses “the memory devices F28 may be placed in a lower power mode (e.g., DRAM devices may be placed in a self-refresh mode in which the devices internally generate refresh operations to retain data, but are not accessible from the SOC F10 until the self-refresh mode is exited”).
Regarding claim 6, Mehta in view of Pagenberg discloses the storage system of claim 1, wherein the first set of non-volatile memory modules and the second set of non-volatile memory modules comprise heterogenous storage devices (Pagenberg discloses the unified memory architecture includes a unified address space that allows the heterogeneous agents in the system).
Regarding claim 7, Mehta in view of Pagenberg discloses the storage system of claim 1, wherein the primary storage node further comprises one or more authorities for managing data stored in the storage system (Mehta, ¶ [0289], Reseller who is authorized to view the raw results).
Regarding claim 8, Mehta in view of Pagenberg discloses the storage system of claim 7, wherein the secondary storage node lacks authorities (¶ [0290], Tenant’s data and prevents secondary copies (e.g., backup copies, archive copies, disaster recovery copies, etc.) from being viewed by or restored to unauthorized devices – meaning lacks authorities).
Regarding claim 9, Mehta in view of Pagenberg discloses the storage system of claim 1, wherein the secondary storage node is configured to operate as a primary storage node for a period of time (Mehta, ¶ [0218], data retained for a period).
Regarding claim 10, Mehta in view of Pagenberg discloses the storage system of claim 1, wherein the secondary storage node is coupled to the primary storage node via a network (Fig. 1).
Regarding claim 11, Mehta in view of Pagenberg discloses the storage system of claim 1, wherein the secondary storage node is coupled to the primary storage node directly via an interconnect (Mehta, ¶ [0076]).
Regarding claim 12, Mehta in view of Pagenberg discloses the storage system of claim 1, wherein the secondary storage node does not receive requests to access data (¶ [0255], the request is being directed to the secondary storage from the primary).
Regarding claims 13-19, see claims 1-2 and 5-9, respective, for the same reason of rejection.
Regarding claim 20, see discussion of claim 1 for the same reason of rejection.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TUANKHANH D PHAN whose telephone number is (571)270-3047. The examiner can normally be reached on Mon-Fri, 10:00am-18:00pm.
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/TUANKHANH D PHAN/ Examiner, Art Unit 2154
Prosecution Insights