DETAILED ACTION
This office action is responsive to claims 1 - 8 filed in this application Schedler, U.S. Patent Application No. 18/593244, (Filed March 1, 2024) claiming priority to EP23189912.1 (8/7/2023) and DE102023105179.2 (3/2/2023) (“Schedler”).
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement(s) (IDS) filed on June 28, 2024 in compliance with the provisions of 37 CFR 1.97, 1.98 and MPEP § 609. The references listed therein have been considered, and placed in the application file.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO internet Web site contains terminal disclaimer forms which may be used. Please visit http://www.uspto.gov/forms/. The filing date of the application will determine what form should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to http://www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1 and 8 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over the following claims of U.S. Applications: Claims 1 and 2 of 16/950,422. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the Application(s) anticipate the claims of the instant Application.
Claims 2 – 7 are provisionally rejected on the ground of obviousness type double patenting as being unpatentable over the previous claims and applications in view of the prior art used below. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims are obvious in view of the Applications cited and the art used infra to teach the dependent claims and associated motivation.
This is a provisional obviousness double patenting rejection because the conflicting claims have not in fact been patented.
cited and the art used infra to teach the dependent claims and associated motivation.
Claim Objections
Claim 1 is objected to for the following informality: “(5)” appears in the claim at line 2 and should be deleted.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claim 8 is rejected under 35 U.S.C. 101 because the claimed inventions are directed to non-statutory subject matter. The claimed inventions do not fall within a statutory category of invention because they are neither a process, machine, manufacture, nor composition of matter.
Claim 8 covers a computer program per se, and fail to recite any device or structure comprising the invention because under the broadest reasonable interpretation they include purely software embodiments. See Interim Guidance on Subject Matter Eligibility, U.S. Patent and Trademark Off. (December 16, 2014) available at http://www.gpo.gov/fdsys/pkg/FR-2014-12-16/pdf/2014-29414.pdf; see also MPEP 2106(I); see also Interim Examination Instructions for Evaluating Subject Matter Eligibility Under 35 U.S.C. § 101, U.S. Patent and Trademark Off. (Aug. 24, 2009), available at http://www.uspto.gov/web/offices/pac/dapp/opla/2009-08-25_interim_101_instructions.pdf.
Claim Rejections 35 U.S.C. §103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1 – 8 are rejected under 35 U.S.C. 103 as being unpatentable over Schedler et al., United States Patent Application Publication No. 2021/0081585 (Published March 18, 2021, filed November 17, 2020) (“Schedler”) in view of Ma et al., United States Patent Application Publication No. 2018/0225143 (Published August 9, 2018, filed April 6, 2018) (“Ma”), and Morrison et al., United States Patent Application Publication No. 2012/0072423 (Published March 22, 2012, filed September 20, 2010) (“Morrison”).
Claims 1 and 8
With respect to claims 1 and 8, Schedler teaches the invention as claimed including a computer-implemented method to test an execution of at least one control unit function of a control unit via at least one computing unit (5) of a simulation environment on a simulator, the control unit function being executed with a zero-time assumption of a discretely advancing simulation time between successive simulation steps in an event-oriented discrete simulation on the simulator, the method comprising:
comparing, via an observation service that is operated on the simulator, an advance of a discrete simulation time with an advance of a simulator real time; creating at least indirectly, if the advance of the simulator real time beyond the advance of the discrete simulation time {A control unit zero-time event-based simulator tracks time differences between simulation time and the real time of the simulator being executed and when the time difference reaches a threshold amount, such as “the time difference between these two simulation times – the past and the new simulation step” the method advances the simulation time to the real time to allow simulations to be performed in real time without the constraint of adhering to the original simulation time. Schedler at ¶¶ 0006, 0007, 0011, 0014 – 0018, 0038, 0040 -0042, 0049.}
However, Schedler doesn’t explicitly teach the limitation:
[time] exceeds a predetermined limit value, {Ma does teach this limitation. Ma teaches that staggering updates in light of errors, as taught in Schedler, may include where a watchdog timer may be used as a mechanism to set a threshold amount of time difference between two events such that the watchdog may trigger a non-maskable interrupt to save stack a trace when the threshold amount to of time is reached. Ma at Abstract; id. at ¶¶ 0058 – 0061, 0070, 0107, 0109; id. at ¶¶ 00065 – 0067 (non-maskable interrupt stack trace).
Schedler and Ma are analogous art because they are from the “same field of endeavor” and are both from the same “problem-solving area.” Specifically, they are both from the field of software monitoring, and both are trying to solve the problem of how collect software performance data.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine a software simulator, as taught in Schedler with using an interrupt to collect software performance data at intervals, as taught in Ma. Ma teaches that a non-masking interrupt is needed to ensure data collection is performed. Id. at ¶ 0005. Therefore, one having ordinary skill in the art would have been motivated to combine a software simulator, as taught in Schedler with using an interrupt to collect software performance data at intervals, as taught in Ma, for the purpose of using a known method of collecting performance data with a simulator that requires collecting performance data.}
However, Schedler and Ma doesn’t explicitly teach the limitation:
a plurality of stack traces of the at least one computing unit; identifying, in an analysis step, at least the most frequent control unit function that the at least one computing unit has executed most frequently at the time of creation of the respective stack trace by analysis of the stack traces; and displaying and/or further processing the identified most frequent control unit function. {Morrison does teach this limitation. Morrison teaches that staggering updates in light of errors, as taught in Schedler and Ma, may include using a simulator by a code profiler to run code and use operating system interrupt to collect stack traces of function calls, identify the “hottest” or most frequently called functions, and display the frequencies of the executed functions. Morrison at ¶¶ 0001 – 0003, 0021 – 0024, 0157, 0191, 0192; id. at ¶ 0151 (function node count is the number of incoming arcs to the node, i.e. number of times called).
Schedler, Ma, and Morrison are analogous art because they are from the “same field of endeavor” and are both from the same “problem-solving area.” Specifically, they are both from the field of software monitoring, and both are trying to solve the problem of how collect software performance data.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine a software simulator that collects stack data, as taught in Schedler and Ma with using a simulator to collect and display data from stack traces, as taught in Morrison. Morrison teaches that interrupts may be used for collecting stack trace information from a simulator. Id. at ¶ 0002. Therefore, one having ordinary skill in the art would have been motivated to combine a software simulator that collects stack data, as taught in Schedler and Ma with using a simulator to collect and display data from stack traces, as taught in Morrison, for the purpose of using a known method for collecting and display stack trace data from simulators with a system that collects stack trace data from a simulator.}
Claim 2
With respect to claim 2, Schedler, Ma, and Morrison, teach the invention as claimed including:
wherein the observation service is executed as a component of the simulation environment. {A control unit zero-time event-based simulator tracks time differences between simulation time and the real time of the simulator being executed and when the time difference reaches a threshold amount, such as “the time difference between these two simulation times – the past and the new simulation step” the method advances the simulation time to the real time to allow simulations to be performed in real time without the constraint of adhering to the original simulation time. Schedler at ¶¶ 0006, 0007, 0011, 0014 – 0018, 0038, 0040 -0042, 0049.}
Claim 3
With respect to claim 3, Schedler, Ma, and Morrison, teach the invention as claimed including:
wherein the observation service either triggers at least one non-maskable interrupt of the computing unit of the simulation environment, which triggers the creation of the plurality of stack traces of the at least one computing unit of the simulation environment, or wherein the observation service triggers a non-maskable interrupt of the computing unit of the simulation environment multiple times, each of which triggers the creation of a stack trace of the at least one computing unit of the simulation environment so that a plurality of stack traces is also created. {A non-maskable interrupt may be triggered to save stack a trace. Ma at Abstract; id. at ¶¶ 00065 – 0067 (non-maskable interrupt stack trace).}
Claim 4
With respect to claim 4, Schedler, Ma, and Morrison, teach the invention as claimed including:
wherein the observation service unconditionally records the plurality of stack traces one after another, or records at fixed intervals of simulator real time. {A watchdog timer may be used as a mechanism to set a threshold amount of time difference between two events such that the watchdog may trigger a non-maskable interrupt to save stack a trace when the threshold amount to of time is reached. Ma at Abstract; id. at ¶¶ 0058 – 0061, 0070, 0107, 0109; id. at ¶¶ 00065 – 0067 (non-maskable interrupt stack trace).}
Claim 5
With respect to claim 5, Schedler, Ma, and Morrison, teach the invention as claimed including:
wherein the plurality of stack traces are created for all computing units of the simulation environment, and wherein, in the analysis step, the stack traces of all computing units are analyzed together and the most frequently executed control unit function is identified and is displayed. {A simulator is used by a code profiler to run code and use operating system interrupt to collect stack traces of function calls, identify the “hottest” or most frequently called functions, and display the frequencies of the executed functions. Morrison at ¶¶ 0001 – 0003, 0021 – 0024, 0157, 0191, 0192; id. at ¶ 0151 (function node count is the number of incoming arcs to the node, i.e. number of times called).}
Claim 6
With respect to claim 6, Schedler, Ma, and Morrison, teach the invention as claimed including:
wherein, in the analysis step, the n most frequent control unit functions that the at least one computing unit has executed most frequently at the time of the creation of the respective stack trace are identified, and/or wherein the identified n most frequent control unit functions are displayed. {A simulator is used by a code profiler to run code and use operating system interrupt to collect stack traces of function calls, identify the “hottest” or most frequently called functions, and display the frequencies of the executed functions. Morrison at ¶¶ 0001 – 0003, 0021 – 0024, 0157, 0191, 0192; id. at ¶ 0151 (function node count is the number of incoming arcs to the node, i.e. number of times called).}
Claim 7
With respect to claim 7, Schedler, Ma, and Morrison, teach the invention as claimed including:
wherein at least the most frequent control unit function that the respective computing unit has executed most frequently at the time of the creation of the respective stack trace is identified for multiple computing units in the analysis step, and wherein the identified most frequent control unit function for the respective computing unit is displayed and/or at least the most frequent control unit function is identified for all computing units. {A simulator is used by a code profiler to run code and use operating system interrupt to collect stack traces of function calls, identify the “hottest” or most frequently called functions, and display the frequencies of the executed functions. Morrison at ¶¶ 0001 – 0003, 0021 – 0024, 0157, 0191, 0192; id. at ¶ 0151 (function node count is the number of incoming arcs to the node, i.e. number of times called).}
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THEODORE E HEBERT whose telephone number is (571)270-1409. The examiner can normally be reached on Monday to Friday 9:00 a.m. to 6:00 p.m..
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lewis Bullock can be reached on 571-272-3759. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
//T.H./ January 10, 2026
Examiner, Art Unit 2199
/LEWIS A BULLOCK JR/Supervisory Patent Examiner, Art Unit 2199