DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1 – 20 are pending.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 11, and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over US Patent Application Publication No. 2023/0031226 (hereinafter Lee) in view of US Patent Application Publication No. 2022/0058237 (hereinafter Wang), and further in view of US Patent No. 11,194,753 (hereinafter Marolia).
As per claims 1, 11, and 17, Lee teaches an apparatus comprising a networking bus (Lee; Figure 1 Item 110, Figure 2 Item 210, Figure 5 Item 510); a plurality of accelerators (Lee; Figure 1 Items 130_1 – 130_n, Figure 2 Items 230_1 – 230_n, and Figure 5 Items 540_1 – 540_n) connected to the networking bus to accelerate operations (Lee; Paragraphs [0056] and [0057]); a plurality of components connected to the networking bus, the components configured to: run a plurality of applications (Lee; Paragraph [0051]); and generate, in the applications, tasks of the acceleration operations (Lee; Paragraphs [0051], [0059], [0060], [0066], and [0067]).
Lee does not teach that the networking bus is a time sensitive networking bus and that the accelerators accelerate multiplication and accumulation operations.
However, Wang teaches a deep learning accelerator (Wang; Figure 2 Item 200) that accelerates multiplication and accumulation operations (Wang; Paragraphs [0024] and [0039]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of Lee to include the multiply and accumulate operations because doing so allows for acceleration of commonly accelerated operations in deep learning accelerators.
Lee in combination with Wang does not teach that the networking bus is a time sensitive networking bus.
However, Marolia teaches an accelerator system in which accelerators (Marolia; Figure 3 Items 306-1 and 306-2) are connected to a time sensitive networking bus (Marolia; Figure 3 “HPI (UPI)” and “PCIe”, Col 14 Lines 13 – 20).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of Lee in combination with Wang to include the time sensitive networking bus because doing so allows for communications over a low latency interconnect (Marolia; Col 14 Lines 13 – 20).
Allowable Subject Matter
Claims 2 – 10, 12 – 16, and 18 – 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claims 2 – 10 would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record fails to teach or suggest alone or in combination wherein the components are further configured to: allocate virtual channels over the time sensitive networking bus from the applications to the accelerators based on timing data of the applications; and wherein each of the virtual channels has a deterministic timing of communication between a component, among the plurality of components, and an accelerator, as required by dependent claim 2, in combination with the other claimed limitations (emphasis added). The prior art of record teaches allocating virtual channels for accelerator traffic over a time sensitive networking bus (Marolia; Col 7 Lines 14 – 47) but does not specifically teach the combination of the allocation of the virtual channels from the applications to the accelerators based on timing data of the applications and the virtual channels having deterministic timing of communication between the components and accelerators, as required by dependent claim 2.
Claims 3 – 10 are also allowable because of their dependence, either directly or indirectly, upon allowable dependent claim 2.
Claims 12 – 16 would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record fails to teach or suggest alone or in combination allocating, over the time sensitive networking bus, virtual channels from the applications to the accelerators based on timing data of the applications; and wherein each of the virtual channels has a deterministic timing of communication between a component, among the plurality of components, and an accelerator, as required by dependent claim 12, in combination with the other claimed limitations (emphasis added). The prior art of record teaches allocating virtual channels for accelerator traffic over a time sensitive networking bus (Marolia; Col 7 Lines 14 – 47) but does not specifically teach the combination of the allocation of the virtual channels from the applications to the accelerators based on timing data of the applications and the virtual channels having deterministic timing of communication between the components and accelerators, as required by dependent claim 12.
Claims 13 – 16 are also allowable because of their dependence, either directly or indirectly, upon allowable dependent claim 12.
Claims 18 – 20 would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record fails to teach or suggest alone or in combination allocating, responsive to the requests and over the time sensitive networking bus, virtual channels to the accelerators based on timing data of the applications; wherein each of the virtual channels has a deterministic timing of communication between a component, among the plurality of components, and an accelerator, and wherein the requests include the timing data specifying timing requirements for the tasks and urgency levels of the tasks, as required by dependent claim 18, in combination with the other claimed limitations (emphasis added). The prior art of record teaches allocating virtual channels for accelerator traffic over a time sensitive networking bus (Marolia; Col 7 Lines 14 – 47) and determining urgency levels of acceleration tasks (Lee; Paragraph [0070]) but does not specifically teach the combination of the allocation of the virtual channels from the applications to the accelerators based on timing data of the applications, the virtual channels having deterministic timing of communication between the components and accelerators, and the requests including timing data with timing requirements and urgency levels of the tasks, as required by dependent claim 18.
Claims 19 and 20 are also allowable because of their dependence, either directly or indirectly, upon allowable dependent claim 18.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RICHARD B FRANKLIN whose telephone number is (571)272-0669. The examiner can normally be reached M-F 8:30am-5pm.
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/RICHARD B FRANKLIN/ Examiner, Art Unit 2181
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