DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending in this application.
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application filed in India on 02/19/2024. It is noted, however, that applicant has not filed a certified copy of the Indian application as required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement(s) (IDS) submitted on 03/02/2024 is/are in compliance with the provisions of 37 C.F.R. § 1.97. Accordingly, the IDS has/have been considered by the examiner.
Drawings
Figures 1-3 should be designated by a legend such as --Prior Art-- because only that which is old is illustrated. See MPEP § 608.02(g). Corrected drawings in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. The replacement sheet(s) should be labeled “Replacement Sheet” in the page header (as per 37 CFR 1.84(c)) so as not to obstruct any portion of the drawing figures. If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claim 1 is objected to because of the following informalities: Claim 1 recites the limitation “an electronic device” in line 2 of the claim. This appears to mean “the electronic device”. Appropriate correction is required.
Claims 4-6 and 18-20 are objected to because of the following informalities: Claims 4-6 and 18-20 recite the limitation “the plurality of diodes comprises” in line 1 of each claim. This appears to mean “the protection circuit comprises”. Appropriate correction is required.
Claim 10 is objected to because of the following informalities: Claim 10 recites the limitation “electrical circuit of claim 1 wherein the MOSFET comprises” in line 1 of the claim. This appears to mean “electrical circuit of claim 8 wherein the MOSFET comprises” since no MOSFET is claimed in claim 1, but a MOSFET is claimed in claim 8. Appropriate correction is required.
Claim 11 is objected to because of the following informalities: Claim 11 recites the limitation “the regulator” in line 6 of the claim. This appears to mean “the shunt regulator”. Appropriate correction is required.
Claim 15 is objected to because of the following informalities: Claim 15 recites the limitation “the MOSFET” in line 1 of the claim. This appears to mean “the semiconductor switch”. Appropriate correction is required.
Claim Rejections - 35 USC § 112
Claims 2 and 17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The term "low" in claims 2 and 17 is a relative term which renders the claim indefinite. The term "low" is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. The limitation "low reverse leakage current” has been rendered indefinite by the use of the term “low” because without a reference, any reverse leakage current can be explained as low. For the purposes of examination, the examiner has interpreted "low reverse leakage current" to be any reverse leakage current under 100 microamps since similar claim 12 has the low reverse leakage current in the order of tens of microamps and tens of microamps is interpreted to be any number of microamps below 100 microamps.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 8-10, 16, and 17 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Rapsinski et al. U.S. Patent Application 2002/0109952 (hereinafter “Rapsinski”).
Regarding claim 1, Rapsinski teaches an electrical circuit (refer to fig.1) for protecting an electronic device (i.e. battery 28 and load 26)(fig.1), comprising: a protection circuit (i.e. over voltage protection circuit 24)(fig.1) for an electronic device (implicit), wherein the protection circuit includes a plurality of diodes (i.e. zener diodes 70 and 58)(fig.2) and at least one field effect transistor (i.e. P-channel MOSFET 50)(fig.2); and an energy storage device (i.e. battery 28)(fig.1) associated with the electronic device (implicit), wherein the field effect transistor is electrically connected to the plurality of diodes (implicit), wherein a reference voltage of the protection circuit is tunable to trigger the protection circuit at a threshold voltage (refer to [0008]), which when triggered activates the at least one field effect transistor to protect the energy storage device from an over voltage condition or an over charging condition until the over voltage condition or the overcharging condition is no longer present (refer to [0008]).
Regarding claim 2, Rapsinski teaches the electrical circuit of claim 1 wherein the protection circuit protects the energy storage device (implicit)(refer to [0008]) and enhances a performance and a life of the electronic device by maintaining a low reverse leakage current consumption (implicit)(P-channel MOSFETs inherently have a low reverse leakage current consumption and the low reverse leakage current consumption enhances the performance and life of the electronic device by being more efficient).
Regarding claim 3, Rapsinski teaches the electrical circuit of claim 1 wherein the protection circuit comprises a shunt regulator circuit (i.e. zener diode 58, resistors 60 and 68, and NPN transistor 62)(fig.2).
Regarding claim 8, Rapsinski teaches the electrical circuit of claim 1 wherein the field effect transistor comprises a MOSFET (i.e. P-channel MOSFET 50)(fig.2).
Regarding claim 9, Rapsinski teaches the electrical circuit of claim 1 wherein the protection circuit further comprises a semiconductor switch (i.e. PNP transistor 66)(fig.2) comprising at least one of: MOSFET, a PNP/NPN transistor, or an electronically controlled load switch (i.e. PNP transistor 66)(fig.2).
Regarding claim 10, Rapsinski teaches the electrical circuit of claim 8 wherein the MOSFET comprises a P-Channel MOSFET (i.e. P-channel MOSFET 50)(fig.2).
Regarding claim 16, Rapsinski teaches a method of protecting an electronic device (refer to overvoltage protection circuit 24)(fig.1)(refer also to [0008]), the method comprising: electronically connecting a protection circuit (i.e. over voltage protection circuit 24)(fig.1) to an electronic device (i.e. load 26 and battery 28)(fig.1), wherein the protection circuit includes a plurality of diodes (i.e. zener diodes 58 and 70)(fig.2) and at least one field effect transistor (i.e. P-channel MOSFET 50)(fig.2), wherein the field effect transistor is electrically connected to the plurality of diodes (implicit); and tuning a reference voltage associated with the protection circuit to trigger the protection circuit at a threshold voltage (refer to [0008]), which when triggered activates the at least one field effect transistor to protect an energy storage device associated with the electronic device from an over voltage condition or an over charging condition until the over voltage condition or the overcharging condition is no longer present (refer to [0008]).
Regarding claim 17, Rapsinski teaches the method of claim 16 wherein the protection circuit protects the energy storage device and enhances a performance and a life of the electronic device by maintaining a low reverse leakage current consumption (implicit)(refer to [0008]) and enhances a performance and a life of the electronic device by maintaining a low reverse leakage current consumption (implicit)(P-channel MOSFETs inherently have a low reverse leakage current consumption and the low reverse leakage current consumption enhances the performance and life of the electronic device by being more efficient).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 4-6, 11-15, and 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Rapsinski as applied to claims 1 or 16 above, and further in view of Lee et al. U.S. Patent Application 2021/0104886 (hereinafter “Lee”).
Regarding claim 4, Rapsinski teaches the electrical circuit of claim 1; however, Rapsinski does not teach wherein the protection circuit comprises a triplet of diodes, shunt regulators and MOSFET switches for Zone 0/ Class I Division 1 deployments in hazardous location (HAZLOC) areas. However, Lee teaches the duplication of voltage restriction stages (refer to [0023] and [0029]) according to the needs of the circuit to meet HAZLOCK standards (refer to [0023] and [0029]). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify electrical circuit of Rapsinski to include the multiples of the over voltage protection circuit of Lee to provide the advantage of meeting the requirements for properly protecting the electronic device. Therefore, Rapsinski and Lee teach wherein the protection circuit comprises a triplet of diodes, shunt regulators and MOSFET switches for Zone 0/ Class I Division 1 deployments in hazardous location (HAZLOC) areas (refer to Lee [0023] and [0029])(refer also to Lee figure 3)(refer also to Rapsinski figure 2).
Regarding claim 5, Rapsinski teaches the electrical circuit of claim 1; however, Rapsinski does not teach wherein the protection circuit comprises a duplet of diodes, shunt regulators and MOSFET switches for Zone 1/ Class I Division 1 deployments in hazardous location (HAZLOC) areas. However, Lee teaches the duplication of voltage restriction stages (refer to [0023] and [0029]) according to the needs of the circuit to meet HAZLOCK standards (refer to [0023] and [0029]). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify electrical circuit of Rapsinski to include the multiples of the over voltage protection circuit of Lee to provide the advantage of meeting the requirements for properly protecting the electronic device. Therefore, Rapsinski and Lee teach wherein the protection circuit comprises a duplet of diodes, shunt regulators and MOSFET switches for Zone 1/ Class I Division 1 deployments in hazardous location (HAZLOC) areas (refer to Lee [0023] and [0029])(refer also to Lee figure 3)(refer also to Rapsinski figure 2).
Regarding claim 6, Rapsinski teaches the electrical circuit of claim 1; however, Rapsinski does not teach wherein the protection circuit comprises a single set of diodes, shunt regulators and MOSFET switches for Zone 2/ Class I Division 2 deployments in hazardous location (HAZLOC) areas. However, Lee teaches the duplication of voltage restriction stages (refer to [0023] and [0029]) according to the needs of the circuit to meet HAZLOCK standards (refer to [0023] and [0029]). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify electrical circuit of Rapsinski to include the multiples of the over voltage protection circuit of Lee to provide the advantage of meeting the requirements for properly protecting the electronic device. Therefore, Rapsinski and Lee teach wherein the protection circuit comprises a single set of diodes, shunt regulators and MOSFET switches for Zone 2/ Class I Division 2 deployments in hazardous location (HAZLOC) areas (refer to Lee [0023] and [0029])(refer also to Lee figure 3)(refer also to Rapsinski figure 2).
Regarding claim 11, Rapsinski teaches a shunt protection circuit (refer to fig.2), comprising: a diode (i.e. zener diode 58)(fig.2) configured to shunt excess voltage above a predetermined threshold (implicit); an energy storing device (i.e. battery 28)(fig.1) connected in parallel with the diode (implicit); and a circuit (i.e. zener diode 58, resistors 60, 68, and 52, P-channel MOSFET 50, NPN transistor 62, and PNP transistor 66)(fig.2) situated between the diode and the energy storing device (implicit), the circuit comprising a semiconductor switch (i.e. P-channel MOSFET 50)(fig.2) and a shunt regulator (i.e. zener diode 58, resistors 60 and 68, and NPN transistor 62)(fig.2) with a reference voltage set to activate the regulator at a predetermined threshold voltage (refer to [0008]), wherein the shunt regulator conducts when the voltage across the diode reaches the predetermined threshold voltage (refer to [0008]), thereby activating the semiconductor switch to protect the energy storing device (refer to [0008]); however, Rapsinski does not teach wherein the circuit is a triplet circuit. However, Lee teaches wherein the circuit is a triplet circuit (refer to MOSFET switches 320-1 to 320-3)(fig.3). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the shunt protection circuit of Rapsinski to multiply it by three as in Lee to provide the advantage of meeting the requirements for properly protecting the electronic device.
Regarding claim 12, Rapsinski and Lee teach the shunt protection circuit of claim 11 wherein the shunt regulator maintains a low reverse leakage current in the order of tens of microamps when not triggered (implicit)(P-channel MOSFETs inherently have a low reverse leakage current consumption in the order of tens of microamps and the low reverse leakage current consumption enhances the performance and life of the electronic device by being more efficient).
Regarding claim 13, Rapsinski and Lee teach the shunt protection circuit of claim 11, however they do not teach wherein an overall system leakage current is maintained below 10 microamps, thereby minimizing drainage of the energy storing device and meeting performance requirements of an end application. However, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have wherein an overall system leakage current is maintained below 10 microamps, thereby minimizing drainage of the energy storing device and meeting performance requirements of an end application, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the shunt protection circuit of Rapsinski and Lee to include wherein an overall system leakage current is maintained below 10 microamps, thereby minimizing drainage of the energy storing device and meeting performance requirements of an end application to provide the advantage of meeting the requirements for hazardous locations as in Lee [0023][ and [0029] and maintaining a high efficiency.
Regarding claim 14, Rapsinski and Lee teach the shunt protection circuit of claim 11 wherein the semiconductor switch comprises at least one of: a MOSFET, a PNP/NPN transistor, or an electronically controlled load switch (i.e. Rapsinski P-channel MOSFET 50)(fig.2).
Regarding claim 15, Rapsinski and Lee teach the shunt protection circuit of claim 14 wherein the MOSFET comprises a P-Channel MOSFET (i.e. Rapsinski P-channel MOSFET 50)(fig.2).
Regarding claim 18, Rapsinski teaches the method of claim 16; however, Rapsinski does not teach wherein the protection circuit comprises a triplet of diodes, shunt regulators and MOSFET switches for Zone 0/ Class I Division 1 deployments in hazardous location (HAZLOC) areas. However, Lee teaches the duplication of voltage restriction stages (refer to [0023] and [0029]) according to the needs of the circuit to meet HAZLOCK standards (refer to [0023] and [0029]). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify method of Rapsinski to include the multiples of the over voltage protection circuit of Lee to provide the advantage of meeting the requirements for properly protecting the electronic device. Therefore, Rapsinski and Lee teach wherein the protection circuit comprises a triplet of diodes, shunt regulators and MOSFET switches for Zone 0/ Class I Division 1 deployments in hazardous location (HAZLOC) areas (refer to Lee [0023] and [0029])(refer also to Lee figure 3)(refer also to Rapsinski figure 2).
Regarding claim 19, Rapsinski teaches the method of claim 16; however, Rapsinski does not teach wherein the protection circuit comprises a duplet of diodes, shunt regulators and MOSFET switches for Zone 1/ Class I Division 1 deployments in hazardous location (HAZLOC) areas. However, Lee teaches the duplication of voltage restriction stages (refer to [0023] and [0029]) according to the needs of the circuit to meet HAZLOCK standards (refer to [0023] and [0029]). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Rapsinski to include the multiples of the over voltage protection circuit of Lee to provide the advantage of meeting the requirements for properly protecting the electronic device. Therefore, Rapsinski and Lee teach wherein the protection circuit comprises a duplet of diodes, shunt regulators and MOSFET switches for Zone 1/ Class I Division 1 deployments in hazardous location (HAZLOC) areas (refer to Lee [0023] and [0029])(refer also to Lee figure 3)(refer also to Rapsinski figure 2).
Regarding claim 20, Rapsinski teaches the method of claim 16; however, Rapsinski does not teach wherein the protection circuit comprises a single set of diodes, shunt regulators and MOSFET switches for Zone 2/ Class I Division 2 deployments in hazardous location (HAZLOC) areas. However, Lee teaches the duplication of voltage restriction stages (refer to [0023] and [0029]) according to the needs of the circuit to meet HAZLOCK standards (refer to [0023] and [0029]). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Rapsinski to include the multiples of the over voltage protection circuit of Lee to provide the advantage of meeting the requirements for properly protecting the electronic device. Therefore, Rapsinski and Lee teach wherein the protection circuit comprises a single set of diodes, shunt regulators and MOSFET switches for Zone 2/ Class I Division 2 deployments in hazardous location (HAZLOC) areas (refer to Lee [0023] and [0029])(refer also to Lee figure 3)(refer also to Rapsinski figure 2).
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Rapsinski as applied to claim 1 above, and further in view of Applicant Admitted Prior Art (hereinafter “AAPA”).
Regarding claim 7, Rapsinski teaches the electrical circuit of claim 1; however, Rapsinski does not teach wherein the electronic device comprises an energy harvesting device. However, AAPA teaches wherein the electronic device comprises an energy harvesting device (refer to Energy Harvester)(fig.1). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the electrical circuit of Rapsinski to include the energy harvesting device of AAPA to provide the advantage of powering the battery management circuit without excessively disturbing or depleting the power source.
Conclusion
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/KEVIN J COMBER/Primary Examiner, Art Unit 2838