DETAILED ACTION
The present application, filed 03/03/2024, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Drawings
The drawings are objected to because item numbers 110 and 152 are blank boxes and are not shown or labeled as to their use or purpose as described in the specification. Any structural detail that is essential for a proper understanding of the disclosed invention should be shown in the drawings. MPEP § 608.02(d). Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 and 11 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by van den Broeke et al. (“van den Broeke”, US 2017/0006675).
Re claim 1, van den Broeke teaches a power supply circuit [Fig 8], comprising: a power switch circuit [Q1] configured to generate an output current to an output terminal of the power switch circuit according to an input voltage [Vin] at an input terminal; a slew rate sensing circuit [R1, C1] configured to generate a sensing voltage [input to negative terminal of 827] according to an output voltage at the output terminal of the power switch circuit; a reference voltage generator circuit [R2, R3, R4] configured to generate a reference voltage [input to positive terminal of 827] according to the input voltage; and a first protection circuit [827] configured to generate a control voltage [output of 827] according to the reference voltage and the sensing voltage to control a turned-on degree of the power switch circuit.
Re claim 11, van den Broeke teaches a control method of a power supply circuit [Fig 8], comprising: generating, by a power switch circuit [Q1], an output current to an output terminal of the power switch circuit according to an input voltage [Vin] at an input terminal; generating, by a slew rate sensing circuit [R1, C1], a sensing voltage [input to negative terminal of 827] according to an output voltage at the output terminal of the power switch circuit; generating, by a reference voltage generator circuit [R2, R3, R4], a reference voltage [input to positive terminal of 827] according to the input voltage; and generating, by a first protection circuit [827], a control voltage [output of 827] according to the reference voltage and the sensing voltage to control a turned-on degree of the power switch circuit.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over van den Broeke in view of Lin et al (“Lin”, TW 202347074A, note: US 2023/0384813 is the US equivalent and will be relied on in this Office Action).
Re claim 3, van den Broeke teaches the limitations as applied to the claim above but does not teach wherein the reference voltage generator circuit comprises: a first resistor coupled between the input terminal and a reference node; a second resistor coupled between the reference node and a ground terminal; and a capacitor coupled between the reference node and the ground terminal, wherein the reference voltage is generated at the reference node.
Lin teaches a device [Fig 2] wherein the reference voltage generator circuit comprises: a first resistor [R3] coupled between the input terminal and a reference node [N2]; a second resistor coupled between the reference node and a ground terminal [GND]; and a capacitor [CX] coupled between the reference node and the ground terminal, wherein the reference voltage [VX] is generated at the reference node. It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of van den Broeke to include the features of Lin because it is used to produce a desired voltage for effective regulation, thus improving the utility of the device, which increases efficiency.
Re claim 13, van den Broeke teaches the limitations as applied to the claim above but does not teach generating, by the reference voltage generator circuit, the reference voltage at a reference node, wherein a first resistor in the reference voltage generator circuit is coupled between the input terminal and the reference node, a second resistor in the reference voltage generator circuit is coupled between the reference node and a ground terminal, and a capacitor in the reference voltage generator circuit is coupled between the reference node and the ground terminal.
Lin teaches generating, by the reference voltage generator circuit, the reference voltage at a reference node [N2], wherein a first resistor [R3] in the reference voltage generator circuit is coupled between the input terminal and the reference node, a second resistor [R4] in the reference voltage generator circuit is coupled between the reference node and a ground terminal [GND], and a capacitor [CX] in the reference voltage generator circuit is coupled between the reference node and the ground terminal. It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of van den Broeke to include the features of Lin because it is used to produce a desired voltage for effective regulation, thus improving the utility of the device, which increases efficiency.
Claims 4 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over van den Broeke in view of Jao et al. (“Jao”, US 2017/0196055).
Re claim 4, van den Broeke teaches the limitations as applied to the claim above but does not teach wherein the first protection circuit comprises: a comparator configured to compare the reference voltage with the sensing voltage to generate a comparison voltage; and a transistor coupled between an output terminal of the comparator, a ground terminal, and the power switch circuit, wherein the comparison voltage is configured to control a turned-on degree of the transistor.
Jao teaches a device [Fig 6] having a circuit comprising a comparator [A3] configured to compare the reference voltage [Vref4] with the sensing voltage [Vrd] to generate a comparison voltage; and a transistor [transistor of 4029] coupled between an output terminal of the comparator, a ground terminal, and the power switch circuit [401], wherein the comparison voltage is configured to control a turned-on degree of the transistor [4029 produces gate voltage for 401, paragraph 64]. It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of van den Broeke to include the features of Jao because it is used to produce a desired voltage for effective regulation, thus improving the utility of the device, which increases efficiency.
Re claim 14, van den Broeke teaches the limitations as applied to the claim above but does not teach comparing, by a comparator in the first protection circuit, the reference voltage with the sensing voltage to generate a comparison voltage; and controlling a turned-on degree of a transistor in the first protection circuit by the comparison voltage, wherein the transistor is coupled between an output terminal of the comparator, a ground terminal, and the power switch circuit.
Jao teaches a device [Fig 6] having a circuit comprising a comparator [A3] configured to compare the reference voltage [Vref4] with the sensing voltage [Vrd] to generate a comparison voltage; and a transistor [transistor of 4029] coupled between an output terminal of the comparator, a ground terminal, and the power switch circuit [401], wherein the comparison voltage is configured to control a turned-on degree of the transistor [4029 produces gate voltage for 401, paragraph 64]. It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of van den Broeke to include the features of Jao because it is used to produce a desired voltage for effective regulation, thus improving the utility of the device, which increases efficiency.
Claims 5 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over van den Broeke in view of Jao and Yamada et al. (“Yamada”, US 10,720,839).
Re claim 5, van den Broeke teaches the limitations as applied to the claim above but does not teach wherein the first protection circuit further comprises: a delay circuit configured to delay the comparison voltage to generate a delayed voltage and transmit the delayed voltage to a control terminal of the transistor to control the turned-on degree of the transistor.
Yamada teaches a device having a delay circuit [1110] configured to delay the comparison voltage to generate a delayed voltage and transmit the delayed voltage to a control terminal of the transistor to control the turned-on degree of the transistor. It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of van den Broeke to include the features of Yamada because it is used as an effective means to protect circuits from power surges, thus improving the utility of the device, which increases efficiency.
Re claim 15, van den Broeke teaches the limitations as applied to the claim above but does not teach delaying, by a delay circuit in the first protection circuit, the comparison voltage to generate a delayed voltage; and transmitting, by the delay circuit, the delayed voltage to a control terminal of the transistor to control the turned-on degree of the transistor.
Yamada teaches delaying, by a delay circuit [1110] in the first protection circuit, the comparison voltage to generate a delayed voltage; and transmitting, by the delay circuit, the delayed voltage to a control terminal of the transistor to control the turned-on degree of the transistor. It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of van den Broeke to include the features of Yamada because it is used as an effective means to protect circuits from power surges, thus improving the utility of the device, which increases efficiency.
Claims 9, 10, 19, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over van den Broeke in view of Wu (US 2019/0036521).
Re claim 9, van den Broeke teaches the limitations as applied to the claim above but does not teach wherein the power switch circuit comprises: a first power switch; and a second power switch connected to the first power switch back to back between the input terminal and the output terminal of the power switch circuit.
Wu teaches a device [Fig 2] wherein the power switch circuit comprises: a first power switch [Power MOSFET]; and a second power switch [Power MOSFET] connected to the first power switch back to back between the input terminal and the output terminal of the power switch circuit [as shown in Fig 2]. It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of van den Broeke to include the features of Wu because it is known for its cost savings, improved efficiency, reduced conduction losses, thus improving the utility of the device, which increases efficiency.
Re claim 10, van den Broeke teaches the limitations as applied to the claim above but does not teach wherein the first power switch and the second power switch are N-type transistors, and the power supply circuit further comprises: a charge pump circuit coupled to a control terminal of the first power switch and a control terminal of the second power switch.
Wu teaches wherein the first power switch and the second power switch are N-type transistors [as shown in Fig 2], and the power supply circuit further comprises: a charge pump circuit [220] coupled to a control terminal of the first power switch and a control terminal of the second power switch. It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of van den Broeke to include the features of Wu because it is known for its smaller size, lower cost, simplicity, and EMI reduction, thus improving the utility of the device, which increases efficiency.
Re claim 19, van den Broeke teaches the limitations as applied to the claim above but does not teach wherein the power switch circuit comprises: a first power switch; and a second power switch connected to the first power switch back to back between the input terminal and the output terminal of the power switch circuit.
Wu teaches a device [Fig 2] wherein the power switch circuit comprises: a first power switch [Power MOSFET]; and a second power switch [Power MOSFET] connected to the first power switch back to back between the input terminal and the output terminal of the power switch circuit [as shown in Fig 2]. It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of van den Broeke to include the features of Wu because it is known for its cost savings, improved efficiency, reduced conduction losses, thus improving the utility of the device, which increases efficiency.
Re claim 20, van den Broeke teaches the limitations as applied to the claim above but does not teach wherein the first power switch and the second power switch are N-type transistors, and the power supply circuit further comprises: a charge pump circuit coupled to a control terminal of the first power switch and a control terminal of the second power switch.
Wu teaches wherein the first power switch and the second power switch are N-type transistors [as shown in Fig 2], and the power supply circuit further comprises: a charge pump circuit [220] coupled to a control terminal of the first power switch and a control terminal of the second power switch. It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of van den Broeke to include the features of Wu because it is known for its smaller size, lower cost, simplicity, and EMI reduction, thus improving the utility of the device, which increases efficiency.
Allowable Subject Matter
Claims 2, 6-8, 12, and 16-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the prior art fails to teach or disclose:
Re claim 2 and its dependents thereof, the closet prior art (which has been made of record) fail to disclose (by themselves or in combination): “the slew rate sensing circuit comprises: a resistor coupled between the input terminal and a sensing node; and a capacitor coupled between the sensing node and the output terminal of the power switch circuit, wherein the sensing voltage is generated at the sensing node” in combination with the additionally claimed features, as are claimed by Applicant.
Re claim 6 and its dependents thereof, the closet prior art (which has been made of record) fail to disclose (by themselves or in combination): “further comprising: a second protection circuit, comprising: a first transient state protection circuit coupled between the input terminal and a sensing node; and a second transient state protection circuit coupled between the sensing node and a ground terminal, wherein the sensing voltage is generated at the sensing node” in combination with the additionally claimed features, as are claimed by Applicant.
Re claim 12 and its dependents thereof, the closet prior art (which has been made of record) fail to disclose (by themselves or in combination): “generating, by the slew rate sensing circuit, the sensing voltage at a sensing node, wherein a resistor in the slew rate sensing circuit is coupled between the input terminal and the sensing node, and a capacitor in the slew rate sensing circuit is coupled between the sensing node and the output terminal of the power switch circuit” in combination with the additionally claimed features, as are claimed by Applicant.
Re claim 16 and its dependents thereof, the closet prior art (which has been made of record) fail to disclose (by themselves or in combination): “generating, by the slew rate sensing circuit, the sensing voltage at a sensing node, wherein a first transient state protection circuit in a second protection circuit is coupled between the input terminal and the sensing node, and a second transient state protection circuit in the second protection circuit is coupled between the sensing node and a ground terminal” in combination with the additionally claimed features, as are claimed by Applicant.
Conclusion
Examiner's Note:
Examiner has cited particular columns and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAKAISHA JACKSON whose telephone number is (571)270-3111. The examiner can normally be reached on M-F 8:00-5:00.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, MONICA LEWIS can be reached on 571-272-1838. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/LaKaisha Jackson/
Examiner, Art Unit 2838