DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
2. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
4. Claim(s) 1-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ji (US 20210134597) in view of the following arguments.
Regarding Claim 1, Ji teaches a semiconductor device (100, Fig. 1, para [0028]), comprising: a substrate (101, Fig. 1, para [0029]) including a first active pattern (R1, Fig. 1, para [0028]) and a second active pattern (R2, Fig. 1, para [0028]) which are spaced apart from each other R1 & R2, Fig. 1, para [0028]); a first gate structure (120N, Fig. 1, para [0029]) disposed on the first active pattern (R1, Fig. 1, para [0028]); a second gate structure (120P, Fig. 1, para [0030]) disposed on the second active pattern (R2, Fig. 1, para [0030]) and a channel semiconductor pattern (103, Fig. 1, para [0031]) disposed between the second active pattern (R2, Fig. 1, para [0030]) and the second gate structure, wherein the first gate structure (120N, Fig. 1, para [0029]) comprises: a first insulating pattern (104N, Fig. 1, para [0029]), a second insulating pattern (106, Fig. 1, para [0030])) and a first high-k dielectric pattern (105N, Fig. 1, para [0029]), which are stacked on the first active pattern (R1, Fig. 1, para [0028]), wherein the second gate structure (120P, Fig. 1, para [0030]) comprises: a third insulating pattern (104P, Fig. 1, para [0030]) and a second high-k (105P, Fig. 1, para [0030]) dielectric pattern, which are stacked on the channel semiconductor pattern (103, Fig. 1, para [0031]).
Ji does not expressly disclose a thickness of the third insulating pattern ranges from 12Å to 13Å.
However, Ji does disclose a “deposition-type interface layer 14A may be formed in a thickness of approximately 10 Å or more para [0053]. The deposition-type interface layer 14A may be formed to a thickness of approximately 10 Å to 70 Å (Fig. 2B, para [0053]),” which overlaps the claimed thickness, and “In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. See MPEP2144.05, I.
Therefore, it would have been prima facie obvious to one of ordinary skill, in the art as of the effective filing date, to enable using the teachings of Ji to arrive at the recited thickness.
Regarding Claim 2, Ji teaches wherein the second active pattern includes a first semiconductor material (R2, Fig. 1, para [0028] and para [0029]), wherein the channel semiconductor pattern includes a second semiconductor material (103, Fig. 1, para [0031]), and wherein the first semiconductor material is different from the second semiconductor material (R2 & 103, Fig. 1, para [0028] through [0031]).
Regarding Claim 3, Ji teaches the semiconductor device of claim 1 (100, Fig. 1, para [0028]).
Ji also teaches wherein the p channel (13) is formed to a thickness of 100 angstroms or less ([0052]), wherein the first insulating pattern is formed to a thickness of 10 to 70 angstroms, and wherein the selection and amount of materials are selected in order to control the electrical properties of the device ([0020]).
Ji does not explicitly teach wherein a level of a top surface of the channel semiconductor is higher than a level of a top surface of the second insulating pattern.
However, it is well known in the art that in a FinFET it is possible to optimize the thicknesses of the various layers for the the well-known advantage of controlling electrical properties. Ji itself implies these principles (see para [0061] EOT value and para [0039] - [0043] effective work function related to the total resistance of the gate stacks) with the added information of material modification as the two main effective variables that one of ordinary skill in the art has the ability to modify.
Further, according to MPEP 2144.05, II ; “re Williams, 36 F.2d 436, 438, 4 USPQ 237 (CCPA 1929) ("It is a settled principle of law that a mere carrying forward of an original patented conception involving only change of form, proportions, or degree, or the substitution of equivalents doing the same thing as the original invention, by substantially the same means, is not such an invention as will sustain a patent, even though the changes of the kind may produce better results than prior inventions.").”
It would have been obvious to one of ordinary skill in the art at the time as of the effective filing date, to arrive at the recited limitations through routine optimization for the further advantage of optimizing the thickness ranges of the insulating patterns and channel semiconductor enough to define a height difference in order to optimize the flow of electron interaction with the gate structure.
Regarding Claim 4, Ji teaches wherein the first gate structure (120N, Fig. 1, para [0029]) further comprises: a first lower conductive pattern (107N, Fig. 1, para [0029]), a first upper conductive pattern (108N, Fig. 1, para [0029]) and a first capping pattern (109N, Fig. 1, para [0029]), which are stacked on the first high-k dielectric pattern (105N, Fig. 1, para [0029]), and wherein the second gate structure further comprises (120P, Fig. 1, para [0029]): a second lower conductive pattern (107P, Fig. 1, para [0030]), a second upper conductive pattern (108P, Fig. 1, para [0030]) and a second capping pattern (109P, Fig. 1, para [0030]), which are stacked on the second high-k dielectric pattern (105P, Fig. 1, para [0030]).
Regarding Claim 5, Ji teaches wherein the first and third insulating patterns include silicon oxide (104N & 104P, para [0009])
Ji does not explicitly teach a silicon oxide including pattern for the second insulating pattern. Instead it teaches a that the second insulating pattern may “be made of or include a rare earth metal of the lanthanide series…..include lanthanum” (para [0029]).
Element 16 in Ji is formed by diffusing lanthanum oxide into an interface between the top portion of silicon oxide dielectric layer 14 and bottom portion of high-k layer (see para [0062]). Further along the process, element 20 in Ji which is situated between element 16 and element 14, is made via a thermal treatment process (para [0066] – [0069]). It is well known in the art that an interface between two layers includes materials from the top and bottom layers. Therefore, a person of ordinary skill in the art understands that layer 160 will include silicon oxide. Accordingly, it appears that Ji teaches the recited limitations of the applicant.
Regarding Claim 6, Ji teaches a semiconductor device of claim 1 (100, Fig. 1, para [0028]).
Ji does not explicitly teach wherein a difference between a level of a top surface of the first gate structure and a level of a top surface of the second gate structure is 8nm or less.
Ji also teaches wherein the p channel (13) is formed to a thickness of 100 angstroms or less ([0052]), wherein the first insulating pattern is formed to a thickness of 10 to 70 angstroms, and wherein the selection and amount of materials are selected in order to control the electrical properties of the device ([0020]).
Ji does not explicitly teach wherein a level of a top surface of the channel semiconductor is higher than a level of a top surface of the second insulating pattern.
However, it is well known in the art that in a FinFET it is possible to optimize the thicknesses of the various layers for the well-known advantage of controlling electrical properties. Ji itself implies these principles (see para [0061] EOT value and para [0039] - [0043] effective work function related to the total resistance of the gate stacks) with the added information of material modification as the two main effective variables that one of ordinary skill in the art has the ability to modify.
Further, according to MPEP 2144.05, II ; “re Williams, 36 F.2d 436, 438, 4 USPQ 237 (CCPA 1929) ("It is a settled principle of law that a mere carrying forward of an original patented conception involving only change of form, proportions, or degree, or the substitution of equivalents doing the same thing as the original invention, by substantially the same means, is not such an invention as will sustain a patent, even though the changes of the kind may produce better results than prior inventions.").”
It would have been obvious to one of ordinary skill in the art at the time as of the effective filing date, to arrive at the recited limitations through routine optimization for the further advantage of optimizing the thickness ranges of the insulating patterns and channel semiconductor enough to define a height difference in order to optimize the flow of electron interaction with the gate structure.
Regarding Claim 7, Ji teaches wherein the channel semiconductor pattern includes silicon-germanium (SiGe) (103, Fig. 1, para [0020]), wherein the first active pattern includes (R1, Fig. 1, para [0029]): first dopant regions spaced apart from each other in a first direction (121N & 122N & R1, Fig. 1, para [0029]) with the first gate structure interposed between the first dopant regions (120N, Fig. 1, para [0029]), wherein the first direction is parallel to a top surface of the substrate (120N, Fig. 1, para [0029]), wherein the second active pattern includes (R2, Fig. 1, para [0030]): second dopant regions spaced apart from each other in the first direction ( 121P & 122P & R2, Fig. 1, para [0030]) with the second gate structure interposed between the second dopant regions (120P, Fig. 1, para [0030]), wherein the first dopant regions have a first conductivity type (T1, Fig. 1, para [0028]), wherein the second dopant regions have a second conductivity type (R2, Fig. 1, para [0028]), and wherein the first conductivity type is different from the second conductivity type (R1 & R2, Fig. 1, para [0028]).
If the same materials are treated the same way, the same result will be obtained. Regarding claim 8, Ji teaches wherein the first insulating pattern is made of silicon oxide, wherein the first active pattern is made of a silicon substrate and wherein the channel semiconductor pattern is made of SiGe with the connecting insulating pattern made of silicon oxide (104N & 103 & 101 & R1 & R2, Fig. 1, para [00280 through para [0030]).
Ji fails to expressly disclose a bond energy between the first active pattern and the first insulating pattern is greater than a bond energy between the channel semiconductor pattern and the third insulating pattern.
However, the examiner notes that the applicants’ disclosed specification teaches wherein the first active pattern is made of silicon, the first insulating pattern is made of silicon oxide, the channel semiconductor pattern is made of SiGe, and the third insulating pattern is made of silicon oxide.
Therefore, the same materials are treated the same way and therefore the same results would be obtained. Accordingly, the examiner respectfully submits that the claim bond energies are inherent in Ji (MPEP 2112.01 (I)).
Regarding Claim 9, Ji teaches a semiconductor device of claim 1 (100, Fig. 1, para [0028]).
Ji also teaches wherein the p channel (13) is formed to a thickness of 100 angstroms or less ([0052]), wherein the first insulating pattern is formed to a thickness of 10 to 70 angstroms, and wherein the selection and amount of materials are selected in order to control the electrical properties of the device ([0020]).
Ji does not explicitly teach wherein a sum of a thickness of the first insulating pattern and a thickness of the second insulating pattern is substantially equal to the thickness of the third insulating pattern
However, it is well known in the art that in a FinFET it is possible to optimize the thicknesses of the various layers for the well-known advantage of controlling electrical properties. Ji itself implies these principles (see para [0061] EOT value and para [0039] - [0043] effective work function related to the total resistance of the gate stacks) with the added information of material modification as the two main effective variables that one of ordinary skill in the art has the ability to modify.
Further, according to MPEP 2144.05, II ; “re Williams, 36 F.2d 436, 438, 4 USPQ 237 (CCPA 1929) ("It is a settled principle of law that a mere carrying forward of an original patented conception involving only change of form, proportions, or degree, or the substitution of equivalents doing the same thing as the original invention, by substantially the same means, is not such an invention as will sustain a patent, even though the changes of the kind may produce better results than prior inventions.").”
It would have been obvious to one of ordinary skill in the art at the time as of the effective filing date, to arrive at the recited limitations through routine optimization for the further advantage of optimizing the thickness ranges of the insulating patterns and channel semiconductor enough to define a height difference in order to optimize the flow of electron interaction with the gate structure.
Regarding Claim 10, Ji teaches a substrate (101, Fig. 1, para [0029]) including a first active pattern (R1, Fig. 1, para [0028]) and a second active pattern (R2, Fig. 1, para [0028]) which are spaced apart from each other; a first gate structure (120N, Fig. 1, para [0029]) disposed on the first active pattern (R1, Fig. 1, para [0028]); and a second gate structure (120P, Fig. 1, para [0030]) disposed on the second active pattern (R2, Fig. 1, para [0030]), wherein the first gate structure comprises (120N, Fig. 1, para [0029]): a first insulating pattern (104N, Fig. 1, para [0029]), a second insulating pattern (106, Fig. 1, para [0029]) , a first high-k dielectric pattern (105N, Fig. 1, para [0029]) and a first conductive pattern (107N, Fig. 1, para [0029], which are stacked on the first active pattern (R1, Fig. 1, para [0029], wherein the second gate structure (120P, Fig. 1, para [0030]) comprises: a third insulating pattern (104P, Fig. 1, para [0030]), a second high-k dielectric pattern (105P, Fig. 1, para [0030]) and a second conductive pattern (107P, Fig. 1, para [0030]), which are stacked on the second active pattern (R2, Fig. 1, para [0030]), wherein the first insulating pattern (104N, Fig. 1, para [0029]) is disposed between the first active pattern (R1, Fig. 1, para [0028]) and the second insulating pattern(106, Fig. 1, para [0029]) ,
Ji also teaches wherein the p channel (13) is formed to a thickness of 100 angstroms or less ([0052]), wherein the first insulating pattern is formed to a thickness of 10 to 70 angstroms, and wherein the selection and amount of materials are selected in order to control the electrical properties of the device ([0020]).
Ji does not explicitly teach wherein a thickness of the third insulating pattern is 30% or less of a thickness of the second high-k dielectric pattern.
However, it is well known in the art that in a FinFET it is possible to optimize the thicknesses of the various layers for the well-known advantage of controlling electrical properties. Ji itself implies these principles (see para [0061] EOT value and para [0039] - [0043] with effective work function related to the total resistance of the gate stacks) with the added information of material modification as the two main effective variables that one of ordinary skill in the art has the ability to modify.
Further, according to MPEP 2144.05, II ; “re Williams, 36 F.2d 436, 438, 4 USPQ 237 (CCPA 1929) ("It is a settled principle of law that a mere carrying forward of an original patented conception involving only change of form, proportions, or degree, or the substitution of equivalents doing the same thing as the original invention, by substantially the same means, is not such an invention as will sustain a patent, even though the changes of the kind may produce better results than prior inventions.").”
It would have been obvious to one of ordinary skill in the art at the time as of the effective filing date, to arrive at the recited limitations through routine optimization for the further advantage of optimizing the thickness ranges of the insulating patterns and channel semiconductor enough to define a height difference in order to optimize the flow of electron interaction with the gate structure.
Regarding Claim 11, Ji teaches a semiconductor device of claim 1 (100, Fig. 1, para [0028]).
Ji also teaches wherein the p channel (13) is formed to a thickness of 100 angstroms or less ([0052]), wherein the first insulating pattern is formed to a thickness of 10 to 70 angstroms, and wherein the selection and amount of materials are selected in order to control the electrical properties of the device ([0020]).
Ji does not explicitly teach wherein a difference between a level of a top surface of the first gate structure and a level of a top surface of the second gate structure is 8nm or less.
However, it is well known in the art that in a FinFET it is possible to optimize the thicknesses of the various layers for the well-known advantage of controlling electrical properties. Ji itself implies these principles (see para [0061] EOT value and para [0039] - [0043] effective work function related to the total resistance of the gate stacks) with the added information of material modification as the two main effective variables that one of ordinary skill in the art has the ability to modify.
Further, according to MPEP 2144.05, II ; “re Williams, 36 F.2d 436, 438, 4 USPQ 237 (CCPA 1929) ("It is a settled principle of law that a mere carrying forward of an original patented conception involving only change of form, proportions, or degree, or the substitution of equivalents doing the same thing as the original invention, by substantially the same means, is not such an invention as will sustain a patent, even though the changes of the kind may produce better results than prior inventions.").”
It would have been obvious to one of ordinary skill in the art at the time as of the effective filing date, to arrive at the recited limitations through routine optimization for the further advantage of optimizing the thickness ranges of the insulating patterns and channel semiconductor enough to define a height difference in order to optimize the flow of electron interaction with the gate structure.
Regarding Claim 12, Ji teaches semiconductor device of claim 10 (100, Fig. 1, para [0027]), further comprising: a channel semiconductor pattern (103, Fig. 1, para [0030]) disposed between the second active pattern (R2, Fig. 1, para [0030]) and the third insulating pattern (104P, Fig. 1, para [0030])
Ji also teaches wherein the p channel (13) is formed to a thickness of 100 angstroms or less ([0052]), wherein the first insulating pattern is formed to a thickness of 10 to 70 angstroms, and wherein the selection and amount of materials are selected in order to control the electrical properties of the device ([0020]).
Ji does not explicitly teach wherein a level of a top surface of the third insulating pattern is higher than a level of a top surface of the second insulating pattern
However, it is well known in the art that in a FinFET it is possible to optimize the thicknesses of the various layers for the well-known advantage of controlling electrical properties. Ji itself implies these principles (see para [0061] EOT value and para [0039] - [0043] effective work function related to the total resistance of the gate stacks) with the added information of material modification as the two main effective variables that one of ordinary skill in the art has the ability to modify.
Further, according to MPEP 2144.05, II ; “re Williams, 36 F.2d 436, 438, 4 USPQ 237 (CCPA 1929) ("It is a settled principle of law that a mere carrying forward of an original patented conception involving only change of form, proportions, or degree, or the substitution of equivalents doing the same thing as the original invention, by substantially the same means, is not such an invention as will sustain a patent, even though the changes of the kind may produce better results than prior inventions.").”
It would have been obvious to one of ordinary skill in the art at the time as of the effective filing date, to arrive at the recited limitations through routine optimization for the further advantage of optimizing the thickness ranges of the insulating patterns and channel semiconductor enough to define a height difference in order to optimize the flow of electron interaction with the gate structure.
Regarding Claim 13, Ji teaches wherein the first and third insulating patterns include silicon oxide (104N & 104P, para [0009])
Ji does not explicitly teach a silicon oxide including pattern for the second insulating pattern. Instead it teaches a that the second insulating pattern may “be made of or include a rare earth metal of the lanthanide series…. include lanthanum” (para [0029]).
Element 16 in Ji is formed by diffusing lanthanum oxide into an interface between the top portion of silicon oxide dielectric layer 14 and bottom portion of high-k layer (see para [0062]). Further along the process, element 20 in Ji which is situated between element 16 and element 14, is made via a thermal treatment process (para [0066] – [0069]). It is well known in the art that an interface between two layers includes materials from the top and bottom layers. Therefore, a person of ordinary skill in the art understands that layer 160 will include silicon oxide. Accordingly, it appears that Ji teaches the recited limitations of the applicant.
Regarding Claim 14, Ji teaches the semiconductor device of claim 10 (100, Fig. 1, para [0027]), further comprising: an interlayer insulating layer disposed on the first (109N, Fig. 1, para [0029]) and second active patterns (109P, Fig. 1, para [0030]), and covering the first gate structure and the second gate structure ( See Fig. 1 below for reference).
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Claim(s) 15-16, 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ji (US 20210134597) in view of Pandey (US 10756093).
Regarding Claim 15, Ji teaches
a first peripheral gate pattern (120N, Fig. 1, para [0029]) disposed on the first peripheral active pattern (R1, Fig. 1, para [0028]); a second peripheral gate pattern (120P, Fig. 1, para [0030]) disposed on the second peripheral active pattern (R2, Fig. 1, para [0030]); and a channel semiconductor pattern (103, Fig. 1, para [0030]) disposed between the second peripheral active pattern (R2, Fig. 1, para [0030]) and the second peripheral gate pattern (120P, Fig. 1, para [0030]), wherein the first peripheral gate pattern comprises (120N, Fig. 1, para [0029]): a first insulating pattern (104N, Fig. 1, para [0029]), a second insulating pattern (106, Fig. 1, para [0029]), a first high-k dielectric pattern ((105N, Fig. 1, para [0029]), a first lower conductive pattern (107N, Fig. 1, para [0029]), a first upper conductive pattern (108N, Fig. 1, para [0029]), and a first capping pattern (109N, Fig. 1, para [0029]), which are stacked on the first peripheral active pattern (R1, Fig. 1, para [0029]), wherein the second peripheral gate pattern (120P, Fig. 1, para [0030]) comprises: a third insulating pattern (104P, Fig. 1, para [0030]), a second high-k dielectric pattern (105P, Fig. 1, para [0030]), a second lower conductive pattern (107P, Fig. 1, para [0030]), a second upper conductive pattern (108P, Fig. 1, para [0030]) and a second capping pattern (109P, Fig. 1, para [0030]), which are stacked on the channel semiconductor pattern (103, Fig. 1, para [0030]).
Ji also teaches wherein the p channel (13) is formed to a thickness of 100 angstroms or less ([0052]), wherein the first insulating pattern is formed to a thickness of 10 to 70 angstroms, and wherein the selection and amount of materials are selected in order to control the electrical properties of the device ([0020]).
However, it does not disclose a substrate including cell active patterns on a cell region, and a first peripheral active pattern and a second peripheral active pattern spaced apart from each other on a peripheral region that is adjacent to the cell region; word lines disposed in the substrate and intersecting the cell active patterns; bit lines disposed on the substrate and intersecting the word lines; a bit line contact disposed on a central portion of each of the cell active patterns and connected to a corresponding one of the bit lines; storage node contacts disposed on end portions of each of the cell active patterns; a landing pad disposed on each of the storage node contacts; a capacitor disposed on the landing pad, a second insulating pattern, and a sum of a thickness of the first insulating pattern and a thickness of the second insulating pattern ranges from 90% to 110% of a thickness of the third insulating pattern.
Pandey does disclose; a substrate including cell active patterns on a cell region (Fig. 1C, para (18); Pandey uses the terms active patterns and active regions but since the reference is also defining an electronic storage method , i. e. a field of similar endeavor, we can treat it analogous to the limitations), and a first peripheral active pattern and a second peripheral active pattern spaced apart from each other on a peripheral region that is adjacent to the cell region (In at least Fig. 3B, para (69), (18), and (21)), word lines disposed in the substrate and intersecting the cell active patterns (Fig. 3B, 40, para (30); from the figure one can see that the word lines are disposed directly on the substrate even if it is not directly mentioned in the specification) bit lines disposed on the substrate and intersecting the word lines (Fig. 11B, 70, para (55); “digit lines” is the term Pandey uses to describe a concept that is analogous to bitline); a bit line contact disposed on a central portion of each of the cell active patterns and connected to a corresponding one of the bit lines (Fig. 11, Fig.11B, Fig. 12); storage node contacts disposed on end portions of each of the cell active patterns (Fig. 11, Fig. 11A, para (56-60)); a landing pad disposed on each of the storage node contacts (Fig. 5B, 44 & 50, the term “landing pad” is not used in the reference but the term “rails” is used to describe an analogous concept); a capacitor disposed on the landing pad (Fig. 5, Fig. 5B; describe the rails, however that is just the strongest description of the embodiment within the reference that contains the limitation. Fig. 11A and para (57) explain the relationship between the “storage-element-contact-regions” and the “storage elements”, in which the landing pad and capacitor terms in the limitation are analogous.).
The motivation for combining is to exhibit better voltage control of the memory module and make possible the creation of more dynamic memory module arrays, you are essentially combining a DRAM memory module to a CMOS. Pandey includes all the memory components and also includes the active regions, the active region disclosure in Ji allows a substitution of active regions which would give a benefit of greater voltage control of the gate regions with the possibility to run the device at lower voltages increasing the efficiency, a smaller possible physical profile, and if set up into arrays; the greater voltage control would allow for more strategic memory allocations. There is even a section disclosed in Ji in which it explains that “the technology of the present invention may be applied to memory devices, such as DRAM, FeRAM, 3D NAND, PCRAM, SU-RAM and the like. The technology of the present invention may also be applied to CMOSFETs in peripheral circuits,” (para [0154]).
Therefore, It would have been prima facie obvious to one of ordinary skill, in the art as of the effective filing date, to substitute the Ji active region into the Pandey peripherals.
Ji and Pandey teach all of the above, except for; a sum of a thickness of the first insulating pattern and a thickness of the second insulating pattern ranges from 90% to 110% of a thickness of the third insulating pattern.
However, it is well known in the art that in a FinFET it is possible to optimize the thicknesses of the various layers for the well-known advantage of controlling electrical properties. Ji itself implies these principles (see para [0061] EOT value and para [0039] - [0043] with effective work function related to the total resistance of the gate stacks) with the added information of material modification as the two main effective variables that one of ordinary skill in the art has the ability to modify.
Further, according to MPEP 2144.05, II ; “re Williams, 36 F.2d 436, 438, 4 USPQ 237 (CCPA 1929) ("It is a settled principle of law that a mere carrying forward of an original patented conception involving only change of form, proportions, or degree, or the substitution of equivalents doing the same thing as the original invention, by substantially the same means, is not such an invention as will sustain a patent, even though the changes of the kind may produce better results than prior inventions.").”
Therefore, with the combination of Ji and Pandey, it would have been obvious for one of ordinary skill in the art to meet the claimed limitations of claim 15.
Regarding claim 16, Ji teaches semiconductor device of claim 15 (100, Fig. 1, para [0028]), and wherein the channel semiconductor pattern includes silicon-germanium (SiGe) (103, Fig. 1, para [0030])).
Ji does not explicitly teach a silicon oxide including pattern for the second insulating pattern. Instead it teaches a that the second insulating pattern may “be made of or include a rare earth metal of the lanthanide series…..include lanthanum” (para [0029]).
Element 16 in Ji is formed by diffusing lanthanum oxide into an interface between the top portion of silicon oxide dielectric layer 14 and bottom portion of high-k layer (see para [0062]). Further along the process, element 20 in Ji which is situated between element 16 and element 14, is made via a thermal treatment process (para [0066] – [0069]). It is well known in the art that an interface between two layers includes materials from the top and bottom layers. Therefore, a person of ordinary skill in the art understands that layer 160 will include silicon oxide. Accordingly, it appears that Ji teaches the recited limitations of the applicant.
Regarding Claim 18, Ji teaches a semiconductor device of claim 1 (100, Fig. 1, para [0028]).
Ji also teaches wherein the p channel (13) is formed to a thickness of 100 angstroms or less ([0052]), wherein the first insulating pattern is formed to a thickness of 10 to 70 angstroms, and wherein the selection and amount of materials are selected in order to control the electrical properties of the device ([0020]).
Ji does not explicitly teach wherein a level of a top surface of the channel semiconductor is higher than a level of a top surface of the second insulating pattern.
However, it is well known in the art that in a FinFET it is possible to optimize the thicknesses of the various layers for the well-known advantage of controlling electrical properties. Ji itself implies these principles (see para [0061] EOT value and para [0039] - [0043] effective work function related to the total resistance of the gate stacks) with the added information of material modification as the two main effective variables that one of ordinary skill in the art has the ability to modify.
Further, according to MPEP 2144.05, II ; “re Williams, 36 F.2d 436, 438, 4 USPQ 237 (CCPA 1929) ("It is a settled principle of law that a mere carrying forward of an original patented conception involving only change of form, proportions, or degree, or the substitution of equivalents doing the same thing as the original invention, by substantially the same means, is not such an invention as will sustain a patent, even though the changes of the kind may produce better results than prior inventions.").”
It would have been obvious to one of ordinary skill in the art at the time as of the effective filing date, to arrive at the recited limitations through routine optimization for the further advantage of optimizing the thickness ranges of the insulating patterns and channel semiconductor enough to define a height difference in order to optimize the flow of electron interaction with the gate structure.
Regarding Claim 19, Ji does not expressly disclose wherein the sum of the thickness of the first insulating pattern and the thickness of the second insulating pattern ranges from 12Å to 13Å.
However, Ji does disclose a “deposition-type interface layer 14A may be formed in a thickness of approximately 10 Å or more para [0053]. The deposition-type interface layer 14A may be formed to a thickness of approximately 10 Å to 70 Å (Fig. 2B, para [0053]),” which overlaps the claimed thickness, and “In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. See MPEP2144.05, I.
Therefore, it would have been prima facie obvious to one of ordinary skill, in the art as of the effective filing date, to enable using the teachings of Ji to arrive at the recited thickness.
Regarding Claim 20, Ji teaches a semiconductor device of claim 1 (100, Fig. 1, para [0028]).
Ji also teaches wherein the p channel (13) is formed to a thickness of 100 angstroms or less ([0052]), wherein the first insulating pattern is formed to a thickness of 10 to 70 angstroms, and wherein the selection and amount of materials are selected in order to control the electrical properties of the device ([0020]).
Ji does not explicitly teach wherein a difference between a level of a top surface of the first peripheral gate pattern and a level of a top surface of the second peripheral gate pattern is 8nm or less.
However, it is well known in the art that in a FinFET it is possible to optimize the thicknesses of the various layers for the well-known advantage of controlling electrical properties. Ji itself implies these principles (see para [0061] EOT value and para [0039] - [0043] effective work function related to the total resistance of the gate stacks) with the added information of material modification as the two main effective variables that one of ordinary skill in the art has the ability to modify.
Further, according to MPEP 2144.05, II ; “re Williams, 36 F.2d 436, 438, 4 USPQ 237 (CCPA 1929) ("It is a settled principle of law that a mere carrying forward of an original patented conception involving only change of form, proportions, or degree, or the substitution of equivalents doing the same thing as the original invention, by substantially the same means, is not such an invention as will sustain a patent, even though the changes of the kind may produce better results than prior inventions.").”
It would have been obvious to one of ordinary skill in the art at the time as of the effective filing date, to arrive at the recited limitations through routine optimization for the further advantage of optimizing the thickness ranges of the insulating patterns and channel semiconductor enough to define a height difference in order to optimize the flow of electron interaction with the gate structure.
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ji (US 20210134597) and Pandey, as applied to claims 15-16, and 18-20, and further in view of Kobayashi (USPGPub US 20090212371).
Regarding Claim 17, Ji teaches the semiconductor device of claim 15 (100, Fig. 1, para [0028]), further comprising: an interlayer insulating layer disposed on the first peripheral gate pattern (106, Fig. 1, para [0029]) and second peripheral active pattern (104P, Fig. 1, para [0030]); and a peripheral capping layer disposed on the interlayer insulating layer (120N & 120P, Fig. 1, para [0029] & para [0030]).
Ji does not explicitly teach spacers on side surfaces of each of the first peripheral gate pattern and second peripheral gate pattern.
However, Kobayashi does teach spaces on side surfaces of the first peripheral gate pattern and second peripheral gate pattern (Fig. 10B, PMOS and NMOS region, 51, para [0074]; or Fig. 10B, 45, NMOS and PMOS region, para [0072]).
The use of spacers in FinFETS is well known in the art because of well-known advantages, such as; electrical current leakage suppression, more consistent electrostatic control, defining the effective channel length without changing the gate width. All of these reasons would be advantageous not only from an engineering perspective but also ultimately a commercial one; therefore, it would have been prima facie obvious to one of ordinary skill, in the art as of the effective filing date, to make use of sidewall spacers for the reasons discussed before.
Conclusion
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/ONASIS MORA/ Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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