Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Status
This instant application No. 18/594080 has claims
Claims 1 and 11 are amended.
Claims 1-20 pending. The effective filing date of this application is 03/17/2023.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on Jan. 21, 2026 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 2, 10-12 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al (2021/0042233) hereinafter Lee in view of Yeh (2011/0055457) hereinafter Yeh.
Regarding claim 1, Lee discloses A memory system (Lee: Fig. 1) comprising:
a nonvolatile memory including a second buffer and a memory cell array (Lee: Fig. 1: memory device 150; [0038]: “The memory device 150 may be a nonvolatile memory device which may retain stored data even though power is not supplied. The memory device 150 may store data provided from the host 102 through a write operation, and output data stored therein to the host 102 through a read operation. In an embodiment, the memory device 150 may include a plurality of memory dies (not shown), and each memory die may include a plurality of planes (not shown). Each plane may include a plurality of memory blocks, each of which may include a plurality of pages, each of which may include a plurality of memory cells coupled to a word line”), the second buffer being configured to receive second data for a next program operation during execution of the program operation to the memory cell array (Lee: [0059]: “The program manager 122 may buffer the program data for the write command in a page buffer while performing a program operation according to the previous command CMD_PRE”); and
a controller (Lee: Fig. 1: processor 134) configured to control the nonvolatile memory, wherein the controller is configured to:
measure an elapsed time from a start of the program operation (Lee: [0057]: “the command manager 124 may determine, in step S218, whether or not the time of programming the previous command CMD_PRE (T_PGM_PRE) has reached a threshold value”); and
start an operation of transferring the second data to the second buffer in the nonvolatile memory based on elapse of a first time from the start of the program operation such that (i) transfer of the second data to the second buffer in the nonvolatile memory is completed during execution of the program operation of the first data from the first buffer, and (ii) the transfer of the second data to the second buffer in the nonvolatile memory is started after the elapse of the first time from the start of the program operation of the first data (Lee: [0059]: “In step S222, when T_PGM_PRE reaches TH_CACHE (‘Y’ in step S218), the command manager 124 may dequeue the write command from the command queue 170 and provide it to the memory device 150. The program manager 122 may buffer the program data for the write command in a page buffer while performing a program operation according to the previous command CMD_PRE”)
Lee does not explicitly disclose the first buffer being configured to store first data for a program operation for writing the first data from the first buffer to the memory cell array.
However, Yeh discloses the first buffer being configured to store first data for a program operation for writing the first data from the first buffer to the memory cell array (Yeh: Fig. 3: first buffer area 404 and second buffer area 406; [0060]: “if the flash memory controller 204 receives two continuous host write commands from the host system 290 by using the NCQ protocol and accordingly is about to programming two pages of the 0.sup.th flash memory die 400, because the 0.sup.th flash memory die 400 has two buffer areas (i.e., the first buffer area 404 and the second buffer area 406)…. In particular, during the 0.sup.th flash memory die 400 programs the data of the first host write command from the second buffer area 406 into the storage area 402, the first buffer area 404 receives the data of the next program command (i.e., the second host write command). Namely, by using the "command W3", the memory management unit 208 can process the second host write command and transmit the data of the second host write command into the first buffer area 404 before the 0.sup.th flash memory die 400 finishes executing the first host write command”; <Examiner note: the first buffer area 404 is disclosed as the second buffer and second buffer area 406 disclosed as the first buffer>).
Examiner note: Lee discloses a memory system receives a write command from a host. It then determines whether a program operation for the previous write command has started. In response to the previous write command has started and has reached a time value, the program data for the write command is buffered in a page buffer while performing a program operation according to the previous write command. When the program operation according to the previous write command is completed, the program manager may control the memory device to program the buffered program data into memory blocks. As such Lee discloses the limitation that transfer of the second data to the buffer in the nonvolatile memory is started after the elapse of the first time from the start of the program operation, and the transfer of the second data to the buffer in the nonvolatile memory is completed during execution of the program operation. Lee does not explicitly teach the first buffer to store first data. However, Yeh teaches the limitations as cited above using another buffer.
Disclosures by Lee and Yeh are analogous because they are in the same field endeavor of memory access and control.
It would have been obvious to an ordinary person skilled in the art before the earliest effective filing date of the claimed invention to incorporate writing data of the next command during the program operation of the previous write command taught by Lee to include a buffer for storing data of the next command disclosed by Yeh. The motivation for including the page buffer for storing data corresponding to the nonvolatile memory by paragraph [0060] of Yeh is for executing time of the host write commands is shortened.
Regarding claim 11, these claims limitations are significantly similar to those of claim 1, and, therefore, are rejected on the same grounds.
Regarding claim 2, Lee combined further discloses The memory system according to claim 1, wherein the first time is determined based on a remaining time obtained by subtracting (i) a time required to transfer the second data to the nonvolatile memory from (ii) a program time required for the program operation (Lee: [0084]: “When a first program operation time T_PGM1, for a program operation performed in response to the first write command W1 reaches the threshold value TH_CACHE, the program manager 122 may control the memory device 150 to perform a second program operation for the second write command queue W2 by dequeuing the second write command W2 and providing it to the memory device 150….there may be a delay, i.e., a delay time T_DELAY, until the second program operation, which is the previous command operation, is completed may occur. The delay time T_DELAY may be as much as the difference between a sum of a maximum first program operation execution time T_PGM1 and a second program operation execution time T_PGM2 and a time taken from when PGM2 START, i.e., the second program operation, begins to when PGM1 END, i.e., the first program operation is completed”).
Regarding claim 12, these claims limitations are significantly similar to those of claim 2, and, therefore, are rejected on the same grounds.
Regarding claim 10, Lee combined further discloses The memory system according to claim 1, wherein the controller is configured to perform various processes by executing a firmware (Lee: [0046]: “The processor 134 may control overall operations of the memory system 110. The processor 134 may use firmware to control the overall operations of the memory system”), the various processes including the measuring the elapsed time (Lee: [0057]: “the command manager 124 may determine, in step S218, whether or not the time of programming the previous command CMD_PRE (T_PGM_PRE) has reached a threshold value”) and starting the operation of transferring the second data (Lee: [0059]: “In step S222, when T_PGM_PRE reaches TH_CACHE (‘Y’ in step S218), the command manager 124 may dequeue the write command from the command queue 170 and provide it to the memory device 150. The program manager 122 may buffer the program data for the write command in a page buffer while performing a program operation according to the previous command CMD_PRE”).
Regarding claim 20, these claims limitations are significantly similar to those of claim 10, and, therefore, are rejected on the same grounds.
Claims 3, 4, 13 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al (2021/0042233) hereinafter Lee in view of Yeh (2011/0055457) hereinafter Yeh as applied to claim 2 and 12 respectively above, and further in view of Choi et al (2022/0206714) hereinafter Choi.
Regarding claim 3, Lee and Yeh do not explicitly disclose exactly the limitations of claim 3.
However, Choi discloses The memory system according to claim 2, wherein the controller is configured to:
manage information indicating a correspondence relationship between (i) each of conditions of the program operation that cause the program time to change and (ii) each of the program times required for the program operation (Choi: Fig. 16: ‘table 219d’; [0118]: “T2, which is the time required for completing the processing of the second task T2 when the first memory cell and the second memory cell are adjacent to each other in the memory cell array 520, may be smaller than T2 which is the time required for completing the processing of the second task T2”); and
determine the program time corresponding to current conditions related to the program operation based on the information, before causing the nonvolatile memory to execute the program operation ([0119]: “the processing completion time T1 to Tk of the tasks included in the task execution time table 219d may be changed in consideration of whether to perform the internal operation of the non-volatile memory”).
Disclosures by Lee, Yeh and Choi are analogous because they are in the same field of endeavor of memory access and control.
It would have been obvious to an ordinary person skilled in the art before the earliest effective filing date of the claimed invention to incorporate writing data of the next command during the program operation of the previous write command taught by Lee/Yeh to include maintaining and updating the execution time of tasks in the table disclosed by Choi. The motivation for maintaining and updating the execution time of tasks using a task execution time table by paragraph [0010] of Choi is for selecting a second memory command based on the plurality of tasks processed information.
Regarding claim 13, these claims limitations are significantly similar to those of claim 3, and, therefore, are rejected on the same grounds.
Regarding claim 4, Lee combined further discloses The memory system according to claim 3, wherein the nonvolatile memory includes a plurality of nonvolatile memory chips, wherein each of the plurality of nonvolatile memory chips includes a plurality of blocks, each block being a unit of erasing operation, wherein each of the plurality of blocks includes a plurality of pages, each page corresponding to a plurality of word lines, wherein each of the plurality of pages is a unit of each of the program operation and a read operation (Lee: [0038]: “the memory device 150 may include a plurality of memory dies (not shown), and each memory die may include a plurality of planes (not shown). Each plane may include a plurality of memory blocks, each of which may include a plurality of pages, each of which may include a plurality of memory cells coupled to a word line”), and wherein the controller is configured to determine the program time corresponding to the current conditions related to the program operation based on (i) the number of current program/erase cycles of a block on which the program operation is executed, (ii) current temperature of the nonvolatile memory chip on which the program operation is executed, or (iii) a word line corresponding to a page on which the program operation is executed ([0038]: “The memory device 150 may store data provided from the host 102 through a write operation”; [0057]: “When the previous command CMD_PRE is a write command WRITE_CMD in step S210, the command manager 124 may determine, in step S218, whether or not the time of programming the previous command CMD_PRE (T_PGM_PRE) has reached a threshold value”).
Regarding claim 14, these claims limitations are significantly similar to those of claim 4, and, therefore, are rejected on the same grounds.
Claims 5, 7, 8, 15, 17 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al (2021/0042233) hereinafter Lee in view of Yeh (2011/0055457) hereinafter Yeh as applied to claims 1 and 11 respectively above, and further in view of Kondo (2019/0080773).
Regarding claim 5, Lee and Yeh do not explicitly disclose exactly the limitations of claim 5.
However, Kondo discloses The memory system according to claim 1, wherein the controller is configured to stop measuring the elapsed time while the program operation is suspended, when causing the nonvolatile memory to suspend the program operation and causing the nonvolatile memory to execute a read operation during suspension of the program operation (Kondo: Fig. 7: from step ST10 to ST26 and Fig. 8: from step ST28 to step ST36).
Disclosures by Lee, Yeh and Kondo are analogous because they are in the same field of endeavor of memory access and control.
It would have been obvious to an ordinary person skilled in the art before the earliest effective filing date of the claimed invention to incorporate writing data of the next command during the program operation of the previous write command taught by Lee/Yeh to include suspending the current program operation at the suspend permissible period disclosed by Kondo. The motivation for suspending the current program operation at the suspend permissible period by paragraph [0010] of Kondo is for performing a read command during the current program operation.
Regarding claim 15, these claims limitations are significantly similar to those of claim 5, and, therefore, are rejected on the same grounds.
Regarding claim 7, Lee and Yeh do not explicitly disclose exactly the limitations of claim 7.
However, Kondo further discloses The memory system according to claim 1, further comprising a write buffer having an area for temporarily storing data associated with a write command received from a host, wherein the controller is configured to release the area in which the data is stored in the write buffer based on completion of the transfer of data from the write buffer to the nonvolatile memory (Kondo: [0265]: “during the write operation, a memory controller 10 transfers write data from an internal buffer (e.g., a buffer memory 12) to the NAND package group 20, and when data writing finishes, the buffer is released”) .
Disclosures by Lee, Yeh and Kondo are analogous because they are in the same field of endeavor of memory access and control.
It would have been obvious to an ordinary person skilled in the art before the earliest effective filing date of the claimed invention to incorporate writing data of the next command during the program operation of the previous write command taught by Lee/Yeh to include a buffer to transfer write data to the NAND memory disclosed by Kondo. The motivation for include a buffer to transfer write data to the NAND memory by paragraph [0265] of Kondo is for improving the execution efficiency of a new operation.
Regarding claim 17, these claims limitations are significantly similar to those of claim 7, and, therefore, are rejected on the same grounds.
Regarding claim 8, Lee and Yeh do not disclose a plurality of timers.
However, Kondo further discloses The memory system according to claim 1, wherein the nonvolatile memory includes a plurality of memory chips (Kondo: Fig. 1: ‘memory chips 21-24’), and the memory system further comprises a plurality of timers (Fig. 2: ‘timer group 146), each timer being configured to being measure the elapsed time from the start of the program operation in a corresponding memory chip (Kondo: Fig. [0054]: “each timer starts measuring or resets its measured time in accordance with an instruction from the control circuit”).
Disclosures by Lee, Yeh and Kondo are analogous because they are in the same field of endeavor of memory access and control.
It would have been obvious to an ordinary person skilled in the art before the earliest effective filing date of the claimed invention to incorporate writing data of the next command during the program operation of the previous write command taught by Lee/Yeh to include timers to measure start execution of an operation disclosed by Kondo. The motivation for include timers to measure start execution of an operation by paragraph [0010] of Kondo is for performing a read command during the current program operation.
Regarding claim 18, these claims limitations are significantly similar to those of claim 8, and, therefore, are rejected on the same grounds.
Claims 6, 9, 16 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al (2021/0042233) hereinafter Lee in view of Lee in view of Yeh (2011/0055457) hereinafter Yeh as applied to claims 1 and 11 respectively above, and further in view of Tan et al (2014/0372667) hereinafter Tan.
Regarding claim 6, Lee and Yeh do not disclose exactly the limitations of claim 6.
However, Tan discloses The memory system according to claim 1,
wherein the nonvolatile memory is configured to store a plurality of bits of data per memory cell provided in the memory cell array (Tan: [0054]: “To be specific, an NAND flash memory may be classified into a Single Level Cell (SLC) NAND flash memory, a Multi Level Cell (MLC) NAND flash memory, or a Trinary Level Cell (TLC) NAND flash memory according to the number of bits which each memory cell thereof is capable of storing”), and
wherein the controller is configured to start the operation of transferring a plurality of pages of data for the next program operation, as the second data, to the nonvolatile memory based on the elapse of the first time from the start of the program operation during execution of the program operation ([0080]: “when a write command (hereinafter referred to as "the second write command") and data DATA2 to be stored into the logical addresses LBA(4).about.LBA(11) are received from the host system 1000, the memory controller 104 (or the memory management circuit 202) temporarily stores the data DATA2 into the buffer memory 208 and divides the data DATA1 into sub data streams SDATA5, SDATA6, SDATA7, SDATA 8, SDATA 9, SDATA 10, SDATA 11 and SDATA 12 based on the size of one physical programming unit… Then, the memory controller 104 (or the memory management circuit 202) writes sub data streams SDATA5, SDATA6, SDATA7, SDATA 8, SDATA 9, SDATA 10, SDATA 11 and SDATA 12 and the error checking and correcting codes ECC5, ECC6, ECC7, ECC8, ECC9, ECC10, ECC 11 and ECC12 respectively into the physical programming units 701(4), 701(5), 701(6), 701(7), 701(8), 701(9), 701(10) and 701(11) of the physical programming unit 304”).
Disclosures by Lee, Yeh and Tan are analogous because they are in the same field of endeavor of memory access and control.
It would have been obvious to an ordinary person skilled in the art before the earliest effective filing date of the claimed invention to incorporate writing data of the next command during the program operation of the previous write command taught by Lee/Yeh to include a buffer to transmit a sub data streams to a nonvolatile memory disclosed by Tan. The motivation for include the buffer to transmit a sub data streams to a nonvolatile memory by paragraph [0012] of Tan is for executing write commands with a smaller buffer memory while data reliability can be ensured.
Regarding claim 16, these claims limitations are significantly similar to those of claim 6, and, therefore, are rejected on the same grounds.
Regarding claim 9, Lee and Yeh do not disclose exactly the limitations of claim 9.
However, Tan further discloses The memory system according to claim 1, wherein the nonvolatile memory includes a NAND flash memory (Tan: [0059]: “the rewritable non-volatile memory module 106 is a MLC NAND flash memory module”).
Disclosures by Lee, Yeh and Tan are analogous because they are in the same field of endeavor of memory access and control.
It would have been obvious to an ordinary person skilled in the art before the earliest effective filing date of the claimed invention to incorporate writing data of the next command during the program operation of the previous write command taught by Lee/Yeh to include a nonvolatile memory as NAND disclosed by Tan. The motivation for include the buffer to transmit a sub data streams to a nonvolatile memory by paragraph [0057] of Tan is for faster speed of writing data.
Regarding claim 19, these claims limitations are significantly similar to those of claim 9, and, therefore, are rejected on the same grounds.
Response to arguments
Applicant's arguments filed on 01/21/2026 have been fully considered but are moot because the arguments do not apply to the combination of the references being used in the current rejection.
Contact Information
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/HAN V DOAN/Examiner, Art Unit 2137
/Arpan P. Savla/Supervisory Patent Examiner, Art Unit 2137