Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Objections
Claims 1 and 8 is objected to because of the following informalities:
Claim 1, line 11, “an output” should correctly be “the output”, see line 9.
Claim 8, page 3, line 4, “a voltage representing a detection” should correctly be “the voltage representing the detection”, see line 1.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 8, 11, and 12 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Fujita (5,051,707).
Regarding claim 1, Fujita (Fig. 1) discloses an amplifier circuit comprising: a first circuit (2) having a radio frequency input terminal (Vs/1), a radio frequency output terminal (Vo), and a control terminal (61); a power detector (3) connected to the radio frequency output terminal; a gain control circuit (6) operable as a correction circuit having a clock terminal (output of comparator (41), an enable terminal (output of comparator (42)), an input terminal (Ø1), and an output terminal (61); a first comparator (41) connected between an output (Vp) of the power detector (3) and the clock terminal; and a second comparator (42) connected between the output (Vp) of the power detector and the enable terminal, wherein the output terminal is connected to the control terminal, and wherein a reference voltage (VRP) of the second comparator (42) is greater than a reference voltage (VRN) of the first comparator (41), see column 2, lines 47-50.
Regarding claim 8, Fujita (Fig. 1) discloses an amplifier circuit comprising: a first circuit (2) configured to process a radio frequency signal (Vs); a power detector (3) configured to detect a power of the radio frequency signal; a first comparator (41) configured to compare a first reference voltage (VRN) with a voltage (voltage output from detector (3)) representing a detection result of the power detector; a second comparator (42) configured to compare a second reference voltage (VRP) with the voltage (voltage output from detector (3)) representing the detection result of the power detector, the second reference voltage (VRP) being greater than the first reference voltage (VRN); and a gain control circuit (6) operable as a correction circuit configured to perform a correction on the first circuit based on a comparison result of the first comparator (41) and a comparison result of the second comparator (42).
Regarding claims 11 and 12, wherein the first circuit is a variable gain amplifier (2), operable as a power amplifier.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 13-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fujita.
Regarding claims 13 and 14, Fujita does not disclose details of the amplifier (2) comprises either field effect transistor or bipolar transistor. However, it is well known in the art that field effect transistor or bipolar transistor is commonly use for amplification purposes and it is further well known that amplifier is formed by single or plurality of transistors.
Regarding claims 15 and 16, Fujita discloses claimed invention except a first circuit includes a variable matching circuit. However, it is well known in the art that variable impedance matching is often provided to improve the linearity of the power amplifier, see Pletcher et al. (8,779,857). Therefore, providing variable impedance matching for Fujita is considered a matter of design engineering.
Allowable Subject Matter
Claims 2-7, 9, and 10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance:
Regarding claims 2 and 9, prior art(s) does not disclose a timing circuit having the connection and configuration as claimed.
Regarding claims 3 and 10, prior art(s) does not disclose a radio frequency detection circuit connected between the first circuit and the input terminal.
Regarding claim 4, prior art(s) does not disclose the input terminal is connected to an output of the power detector.
Regarding claim 5, prior art(s) does not disclose a temperature detection circuit connected to the input terminal.
Regarding claim 6, prior art(s) does not disclose a power supply voltage detection circuit connected to the input terminal.
Regarding claim 7, prior art(s) does not disclose a directional coupler, wherein the power detector is connected to the radio frequency output terminal via the directional coupler.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The prior arts made of record and not relied upon is considered pertinent to applicant's disclosure. They all have at least first and second comparators. However, they all lack a reference voltage of the second comparator is greater than a reference voltage of the first comparator
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Khanh V. Nguyen whose telephone number is (571) 272-1767. The examiner can normally be reached from 8:30 AM – 5:00 PM EST.
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/KHANH V NGUYEN/ Primary Examiner, Art Unit 2843
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