Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Species 2 in the reply filed on July 3rd, 2026, is acknowledged. The traversal is on the ground(s) that Fig. 1 should be included in Species 2. This is not found persuasive because Fig. 1 is a top view of an exemplary substrate structure 100 and does not include a chip package 200 that is in Species 2.
The requirement is still deemed proper and is therefore made FINAL.
Applicant's election with traverse of Sub-species 1a in the reply filed on July 3rd, 2026, is acknowledged. The traversal is on the ground(s) that Figs. 1-2B-1, Fig. 3, and Fig. 4 do not possess mutually exclusive characteristics. This is not found persuasive because “at least one opening” can encompass a single opening as well as multiple openings, but a single opening cannot encompass multiple openings nor can multiple openings encompass a single opening. Additionally, a number of openings is not the same as alternative geometric implementations because the alternative geometric implementations regard the placement of openings, not the number of openings.
The requirement is still deemed proper and is therefore made FINAL.
Applicant's election with traverse of Sub-species 2b in the reply filed on July 3rd, 2026, is acknowledged. The traversal is on the ground(s) that Figs. 5A and 5B are directed to the same embodiment and are not independent or distinct. This is not found persuasive because Fig. 5A does not show the leads that should be present in the embodiment from the cross-sectional perspective.
The requirement is still deemed proper and is therefore made FINAL.
Applicant's election with traverse of Sub-species 1(a)(1) in the reply filed on July 3rd, 2026 is acknowledged. The traversal is on the ground(s) that the distinction between a conductive layer 120 being formed directly under a chip pad portion 111 and not being formed directly under chip pad portion 111 is a positional variation and not a different inventive concept. This is not found persuasive because the positional distinction is a defining factor of the different embodiments.
The requirement is still deemed proper and is therefore made FINAL.
Priority
Acknowledgment is made of applicant’s claim for domestic priority based on provisional
application 63/489,508 filed on March 10th, 2023.
Information Disclosure Statement
The information disclosure statement(s) (IDS) was/were submitted on August 30th, 2024. This submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The disclosure is objected to because of the following informalities:
In Para. 26, “The ground traces 121, 122 serves” should read “The ground traces 121, 122 serve”
In Para. 27, “chip pad portion 125a” should read “chip pad portion 111”.
Appropriate correction is required.
Claim Objections
Claims 1, 11, and 15 are objected to because of the following informalities:
In claim 1, “the second THV passes through the least one second pad portion” should read “the second THV passes through the at least one second pad portion”.
In claim 11, “the second THV passes through the least one second pad portion” should read “the second THV passes through the at least one second pad portion”.
In claim 15, “at least one opening further expose at least a portion of the first ground trace” should read “at least one opening further exposes at least a portion of the first ground trace”.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 8, 11-13, and 18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kondo et al, US 20220059427 A1 (Kondo).
Regarding claim 1; Kondo teaches a substrate structure (Fig. 13: module substrate 12), comprising:
an uppermost conductive layer (Fig. 13: metal pads 20 and 28) adjacent to a top surface (Fig. 13: top surface 12U) of the substrate structure, wherein the uppermost conductive layer comprises:
a first pad portion (Fig. 13: metal pad 20);
and at least one second pad portion (Fig. 13: metal pad 28) separated from the first pad portion and arranged near a corner of the first pad portion (Fig. 2: via conductor 23 passes through metal pad 20 and via conductor 24 passes through metal pad 28. Via conductor 24 is located near a corner of via conductor 23.);
a first through-hole via (THV) (Fig. 13: via conductors 23) and a second THV (Fig. 13: via conductors 24) formed in the substrate structure and passing through the substrate structure,
wherein the first THV passes through the first pad portion (Fig. 13: via conductor 23 passing through metal pad 20; Para. 88) and the second THV passes through the least one second pad portion (Fig. 13: via conductor 24 passing through metal pad 28; Para. 88);
and a first bridge trace formed in the substrate structure (Fig. 13: metal film 22) and thermally connected to the second THV and the first THV (Fig. 13: heat conduction paths 95; Para. 88: "The heat conduction paths 95 from the heat generating sources 17 of the semiconductor chips 14 to the casing 90 through the bumps 15, the metal pads 20, the via conductors 23, the first metal films 22, the via conductors 24, the metal pad 28, the thermally conductive bonding material 32, the metal member 30, and the thermal coupling member 91 are formed").
Regarding claim 2; Kondo teaches all the limitations of the substrate structure as claimed in claim 1. Further, Kondo teaches wherein the first bridge trace is formed in the uppermost conductive layer or in another conductive layer of the substrate structure that is below the uppermost conductive layer (Fig. 13: second conductive layer is below the uppermost conductive layer; see annotated figure shared in this OA).
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Regarding claim 3; Kondo teaches all the limitations of the substrate structure as claimed in claim 2. Further, Kondo teaches the substrate structure further comprising:
a second bridge trace thermally connected to the second THV and the first THV (Fig. 13: plurality of first metal films 22),
and formed in a conductive layer of the substrate structure that is different from the conductive layer in which the first bridge trace is formed (Fig. 13: third conductive layer is different from second conductive layer; see annotated figure shared in this OA).
Regarding claim 8; Kondo teaches all the limitations of the substrate structure as claimed in claim 1. Further, Kondo teaches wherein the first bridge trace (Fig. 19: metal film 22) is connected to an electrical ground layer (Fig. 19: metal pad 68; Para. 112) in the substrate structure.
Regarding claim 11; Kondo teaches a package assembly (Fig. 1: semiconductor package 10), comprising:
a substrate structure (Fig. 13: module substrate 12);
and a chip package mounted on the substrate structure (Fig. 13: semiconductor chip 14), wherein the substrate structure comprising:
an uppermost conductive layer (Fig. 13: metal pads 20 and 28) adjacent to a top surface (Fig. 13: top surface 12U) of the substrate structure, wherein the uppermost conductive layer comprises:
a first pad portion (Fig. 13: metal pad 20);
and at least one second pad portion (Fig. 13: metal pad 28) separated from the first pad portion and arranged near a corner of the first pad portion (Fig. 2: via conductor 23 passes through metal pad 20 and via conductor 24 passes through metal pad 28. Via conductor 24 is located near a corner of via conductor 23.);
a first through-hole via (THV) (Fig. 13: via conductors 23) and a second THV (Fig. 13: via conductors 24) formed in the substrate structure and passing through the substrate structure,
wherein the first THV passes through the first pad portion (Fig. 13: via conductor 23 passing through metal pad 20; Para. 88) and the second THV passes through the least one second pad portion (Fig. 13: via conductor 24 passing through metal pad 28; Para. 88);
and a first bridge trace formed in the substrate structure (Fig. 13: metal film 22) and thermally connected to the second THV and the first THV (Fig. 13: heat conduction paths 95; Para 88: "The heat conduction paths 95 from the heat generating sources 17 of the semiconductor chips 14 to the casing 90 through the bumps 15, the metal pads 20, the via conductors 23, the first metal films 22, the via conductors 24, the metal pad 28, the thermally conductive bonding material 32, the metal member 30, and the thermal coupling member 91 are formed").
Regarding claim 12; Kondo teaches all the limitations of the package assembly as claimed in claim 11. Further, Kondo teaches wherein the first bridge trace is formed in the uppermost conductive layer or in another conductive layer of the substrate structure that is below the uppermost conductive layer (Fig. 13: second conductive layer is below the uppermost conductive layer; see annotated figure shared in this OA).
Regarding claim 13; Kondo teaches all the limitations of the package assembly as claimed in claim 12. Further, Kondo teaches the package assembly further comprising:
a second bridge trace thermally connected to the second THV and the first THV (Fig. 13: plurality of first metal films 22),
and formed in a conductive layer of the substrate structure that is different from the conductive layer in which the first bridge trace is formed (Fig. 13: third conductive layer is different from second conductive layer; see annotated figure shared in this OA).
Regarding claim 18; Kondo teaches all the limitations of the package assembly as claimed in claim 11. Further, Kondo teaches wherein the first bridge trace (Fig. 19: metal film 22) is connected to an electrical ground layer in the substrate structure (Fig. 19: metal pad 68; Para. 112).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection note: Italicized claim limitation indicate claim limitations that are not explicitly disclosed by the primary reference but are disclosed by the secondary reference(s).
Claims 4-6 and 14-17 are rejected under 35 U.S.C. 103 as being unpatentable over Kondo et al, US 20220059427 A1 (Kondo) in view of Saita et al, US 20100163168 A1 (Saita).
Regarding claim 4; Kondo teaches all the limitations of the substrate structure as claimed in claim 1. Further Kondo teaches the substrate structure further comprising: a lowermost conductive layer adjacent to a bottom surface of the substrate structure (Fig. 1: metal pads 25 and 26).
Kondo fails to teach a solder mask layer disposed on the lowermost conductive layer, and comprising at least one opening to expose at least a portion of the second THV and at least a portion of the first THV.
However, Saita teaches and a solder mask layer (Fig. 1: solder resist 38) disposed on the lowermost conductive layer (Fig. 1: first buildup layer 31), and comprising at least one opening (Fig. 1: openings 40) to expose at least a portion of the second THV and at least a portion of the first THV (Fig. 1: via conductors 47 connected to through hole conductors 16).
Kondo and Saita are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Kondo by having a solder mask with at least one opening to expose at least a portion of the second THV and at least a portion of the first THV as disclosed in Saita to prevent solder bridges, protect the conductive layer against oxidation, and have connections to the THVs for pathways to the different layers of the substrate.
Regarding claim 5; Kondo in view of Saita teaches all the limitations of the substrate structure as claimed in claim 4. Further, Saita teaches wherein the lowermost conductive layer comprises a first ground trace (Saita: Fig. 1: ground electrodes 112), wherein the at least one opening (Saita: Fig. 1: openings 40) further exposes at least a portion of the first ground trace (Saita: Fig. 1: via conductor 47 connected to ground electrode 112).
It would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Kondo with the lowermost conductive layer comprising a first ground trace and the at least one opening exposing at least a portion of the first ground trace as disclosed in Saita to act as a shield against electromagnetic interference and is exposed to help with thermal management.
Regarding claim 6; Kondo in view of Saita teaches the substrate structure as claimed in claim 5. Further, Saita teaches wherein the lowermost conductive layer further comprises a power/signal trace (Saita: Fig. 1: power electrodes 111) and a second ground trace (Saita: Fig. 1: ground electrodes 112) separated from the first ground trace by the power/signal trace, wherein the power/signal trace (Saita: Fig. 1: power electrodes 111) is covered by the solder mask layer (Saita: Fig. 1: solder resist 28), and at least a portion of the second ground trace is exposed from the at least one opening (Saita: Fig. 1: via conductor 47 connected to ground electrode 112).
It would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Kondo by having a power/signal trace that is covered by the solder mask, a second ground trace separated from the first ground trace by the power/signal trace, and the at least one opening exposing at least a portion of the second ground trace as disclosed in Saita to reduce inductance by interleaving the ground and power traces.
Regarding claim 14; Kondo teaches all the limitations of the package assembly as claimed in claim 11. Kondo teaches further comprising: a lowermost conductive layer adjacent to a bottom surface of the substrate structure (A: Fig. 1: metal pads 25 and 26).
Kondo fails to teach a solder mask layer disposed on the lowermost conductive layer and comprising at least one opening to expose at least a portion of the second THV and at least a portion of the first THV.
However, Saita teaches a solder mask layer (Fig. 1: solder resist 28) disposed on the lowermost conductive layer (Fig. 1: first buildup layer 31) and comprising at least one opening (Fig. 1: openings 40) to expose at least a portion of the second THV and at least a portion of the first THV (Fig. 1: via conductors 47 connected to through hole conductors 16).
It would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Kondo by having a solder mask with at least one opening to expose at least a portion of the second THV and at least a portion of the first THV as disclosed in Saita to prevent solder bridges, protect the conductive layer against oxidation, and have connections to the THVs for pathways to the different layers of the substrate.
Regarding claim 15; Kondo in view of Saita teaches all the limitations of the package assembly as claimed in claim 14. Further, Saita teaches wherein the lowermost conductive layer comprises a first ground trace (Saita: Fig. 1: ground electrodes 112), wherein the at least one opening (Saita: Fig. 1: openings 40) further expose at least a portion of the first ground trace (Saita: Fig. 1: via conductor 47 connected to ground electrode 112)
It would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Kondo with the lowermost conductive layer comprising a first ground trace and the at least one opening exposing at least a portion of the first ground trace as disclosed in Saita act as a shield against electromagnetic interference and is exposed to help with thermal management
Regarding claim 16; Kondo in view of Saita teaches all the limitations of the package assembly as claimed in claim 15. Further, Saita teaches wherein the lowermost conductive layer further comprises a power/signal trace (Saita: Fig. 1: power electrodes 111) and a second ground trace (Saita: Fig. 1: ground electrodes 112) separated from the first ground trace by the power/signal trace, wherein the power/signal trace (Saita: Fig. 1: power electrodes 111) is covered by the solder mask layer (Saita: Fig. 1: solder resist 28), and at least a portion of the second ground trace is exposed from the at least one opening (Saita: Fig. 1: via conductor 47 connected to ground electrode 112).
It would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Kondo by having a power/signal trace that is covered by the solder mask, a second ground trace separated from the first ground trace by the power/signal trace, and the at least one opening exposing at least a portion of the second ground trace as disclosed in Saita to reduce inductance by interleaving the ground and power traces.
Allowable Subject Matter
Claims 7 and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 7; the primary reason for the allowable subject matter of claim 7 is the inclusion of the limitation “a conductive connector electrically coupling the first ground trace and the second ground trace, wherein the conductive connector passes through the at least one opening, and further spans the power/signal trace” in combination with the other limitations of the claim. For example, prior art of record fails to teach or be reasonably combined to render obvious the claim limitations “conductive connector”, “passes through the at least one opening”, and “spans the power/signal trace”. The particular configuration claimed goes beyond the teachings or obvious suggestions of the prior art of record, and the analogous structures found elsewhere in prior art.
Regarding claim 17; the primary reason for the allowable subject matter of claim 17 is the inclusion of the limitation “a conductive connector electrically coupling the first ground trace and the second ground trace, wherein the conductive connector passes through the at least one opening, and further spans the power/signal trace” in combination with the other limitations of the claim. For example, prior art of record fails to teach or be reasonably combined to render obvious the claim limitations “conductive connector”, “passes through the at least one opening”, and “spans the power/signal trace”. The particular configuration claimed goes beyond the teachings or obvious suggestions of the prior art of record, and the analogous structures found elsewhere in prior art.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AUBRIE I HETHERINGTON whose telephone number is (571)270-0666. The examiner can normally be reached M-Th 7:30-5, Fr 7:30-4.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/AUBRIE IRENE HETHERINGTON/Examiner, Art Unit 2817
8/19/2026
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817
Prosecution Insights