DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Allowable Subject Matter
The indicated allowability of claims are withdrawn in view of the newly discovered reference(s) to Kim (US 2008/0001623). Rejections based on the newly cited reference(s) follow.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
4. Claim(s) 1-4, 9, 16, 19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim (US 2008/0001623).
Claim 1, Kim discloses a semiconductor device (Figs. 3, 10, and 15)
comprising:
a first circuit configured to pull up a voltage of a first node (PIN, Fig. 3), the first circuit including a plurality of first transistors (p-type pull-up transistors connected between VDDQ and PIN, Fig. 3) connected in parallel to the first node;
a first pad (PIN, Fig. 3) connected to the first node;
a first comparator (comparator 32A, Fig. 3) configured to compare a voltage of the first node (PIN) with a first reference voltage (VREF_A);
a second comparator (comparator 32B, Fig. 3) configured to compare the voltage of the first node (PIN) with a second reference voltage (VREF_B);
a control circuit (pull-up code 310 which is part of code generating unit 300, Fig. 10) configured to control the plurality of first transistors based on an output of the first comparator and an output of the second comparator; and
a voltage divider circuit (200, Figs. 10, 15) configured to output one of the first and second reference voltages (VREF_A, VREF_B) selected based on control of the control circuit (control signal HLD_ENB which is generated by the control signal pull-up code 310 of code generating unit 300, see Fig. 10).
Claim 3, Kim discloses the semiconductor device according to claim 1, wherein the voltage divider circuit includes: a plurality of resistors connected in series (resistors are connected between VDDQ and VSSQ, Fig. 15); and a selector (TG4-TG9, Fig. 15) to which a plurality of voltages divided by the plurality of resistors are input.
Claim 4, Kim discloses the semiconductor device according to claim 1, wherein the voltage divider circuit is connected to each of a power voltage (VDDQ) and a ground voltage (VSSQ).
Claim 9, Kim discloses the semiconductor device according to claim 1, wherein the first reference voltage is different from the second reference voltage (VREF_A and VREF_B voltages are different, see Figs. 15, 16).
Claim 16, Kim discloses a method of controlling a semiconductor device (Figs. 3, 10, and 15) including: a first circuit (p-type pull-up transistors, Fig. 3) connected to a first node (PIN, Fig. 3) and configured to pull up a voltage of the first node; and a first pad (PIN) connected to the first node and to a resistance element (ZQ resistor, Fig. 3) provided outside the semiconductor device, the method comprising:
performing a first calibration of output impedance of the semiconductor device for a first period of time (see P[0049]…short-calibration…); and performing a second calibration of the output impedance of the semiconductor device for a second period of time longer than the first period of time (see P[0049]…long-calibration…), wherein the first calibration comprises:
comparing (comparators 32A and 32B, Fig. 3) a voltage of the first node with each of a first reference voltage (VREF_B) and a second reference voltage (VREF_A); and controlling (pull-up code 310 which is part of code generating unit 300, Fig. 10) the first circuit to vary the voltage of the first node, based on a relation between the voltage of the first node and the first reference voltage and a relation between the voltage of the first node and the second reference voltage.
Claim 19, Kim discloses the method of controlling the semiconductor device according to claim 16, wherein the first reference voltage (VREF_B) is lower than the second reference voltage (VREF_A, see Fig. 16), and said controlling the first circuit to vary the voltage of the first node (PIN) comprises:
maintaining the voltage of the first node when the voltage of the first node is higher than the first reference voltage and is lower than the second reference voltage, raising the voltage of the first node when the voltage of the first node is lower than the first reference voltage and is lower than the second reference voltage, and lowering the voltage of the first node when the voltage of the first node is higher than the first reference voltage and is higher than the second reference voltage (basic operation of comparing the voltage at the first node between two reference voltages, VREF_A and VREF_B).
Claim Rejections - 35 USC § 103
5. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
6. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
7. Claim(s) 11-14, 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2008/0001623).
Claims 11-12, Kim discloses the claimed invention except for wherein the first
reference voltage is lower than 1/2 or 1/3 of a power voltage of the first circuit, and the second reference voltage is higher than 1/2 or 1/3 of the power voltage of the first circuit. It would have been obvious before the effective filing date of the claimed
invention was made to select the first reference voltage is lower than 1/2 or 1/3 of a
power voltage of the first circuit, and the second reference voltage is higher than 1/2 or
1/3 of the power voltage of the first circuit, since it has been held that discovering an
optimum value of a result effective variable involves only routine skill in the art.
Claims 13-14, Kim discloses, further comprising: a memory array (inherent element of a memory device, see P[0003]-[0005]); and an input/output circuit (circuit 400, Fig. 10 and see P[0004]) configured to receive data to be written into and output data read from the memory array, wherein the control circuit (the code generating unit 300, Fig. 10) is configured to calibrate an output impedance of the input/output circuit by controlling the plurality of first transistors (the pull-up transistors connected to PIN, Fig. 3). Thus, Kim discloses the invention substantially as claimed, but does not disclose the memory device as a NAND flash or a DRAM memory device. It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention was made to implement the memory device as a NAND flash or a DRAM memory device, since it has held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use a matter of obvious design choice.
Claim 18, Kim discloses the claimed invention except for wherein the number of times the voltage of the first node is compared with the first reference voltage during the first calibration is once and the number of times the voltage of the first node is compared with the second reference voltage during the first calibration is once. It would have been obvious before the effective filing date of the claimed invention was made to provide the number of times the voltage of the first node is compared with the first reference voltage during the first calibration is once and the number of times the voltage of the first node is compared with the second reference voltage during the first calibration is once, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art.
Allowable Subject Matter
1. Claims 5-8, 10, 20-22 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
2. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANH Q TRAN whose telephone number is (571)272-1813. The examiner can normally be reached M-F: 9AM - 5PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander H Taningco can be reached at 571-272-8048. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ANH Q TRAN/
Primary Examiner, Art Unit 2845
8/31/26
Prosecution Insights