DETAILED ACTION
Claims 1- 20 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Notification of invoking - 35 USC § 112(f)
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
Regarding claims 1 – 19, these claims are invoking 112(f) interpretation because in claims 1 and 9 recite limitations such as “an arithmetic processing unit” , “a determining section”, “a step of” has/have been interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because it uses/they use a generic placeholder “unit” and “section” and “step of” coupled with functional language “controlled by the arithmetic processing unit” ,“determining section which determines”, “a step of starting”, “step of causing”, “step of stopping”, “step of …” without reciting sufficient structure to achieve the function. Furthermore, the generic placeholder is not preceded by a structural modifier.
Since the claim limitation(s) invokes 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, claim(s) 1-19 has/have been interpreted to cover the corresponding structure described in the specification that achieves the claimed function, and equivalents thereof.
A review of the specification shows that the following appears to be the corresponding structure described in the specification paragraphs 9-11, 155-173, Figs. 3, 10 and 30 for the 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph limitation. Thus, the above invoking 112(f) terms “an arithmetic processing unit” “a determining section” will be interpreted according to the structure definition provided in paragraphs 9-11, 155-173, Figs. 3, 10 and 30.
If applicant wishes to provide further explanation or dispute the examiner’s interpretation of the corresponding structure, applicant must identify the corresponding structure with reference to the specification by page and line number, and to the drawing, if any, by reference characters in response to this Office action.
If applicant does not intend to have the claim limitation(s) treated under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112 , sixth paragraph, applicant may amend the claim(s) so that it/they will clearly not invoke 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, or present a sufficient showing that the claim recites/recite sufficient structure, material, or acts for performing the claimed function to preclude application of 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
For more information, see MPEP § 2173 et seq. and Supplementary Examination Guidelines for Determining Compliance With 35 U.S.C. 112 and for Treatment of Related Issues in Patent Applications, 76 FR 7162, 7167 (Feb. 9, 2011).
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claim 20 is rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter. Claim 20 is directed to “a time measurement program”. Consequently, all of the elements claimed could be reasonably interpreted in light of the disclosure by an ordinary artisan as being software alone, and therefore the claims are directed to software per se, hence non-statutory subject matter. In order for such a software claim to be statutory, it must be claimed in combination with an appropriate medium and/or hardware to be establish a statutory category of invention and enable any functionality to be realized.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 20 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Regarding claim 20, the claim recites “a time measurement program in a semiconductor device including an arithmetic processing unit, peripheral circuits” renders the claim indefinite because under broadest reasonable interpretation “a time measurement program” can include the arithmetic processing unit, peripheral circuits. The arithmetic processing unit and peripheral circuits are hardware components and the time measurement program is the software program. Thus, software program cannot include the hardware components.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 9, 10, 12-15 and 20 are rejected under AIA 35 U.S.C. 102(a)(1) as being anticipated by Beardsley (US Patent 5471631 A).
Regarding claim 1, Beardsley discloses a semiconductor device [Fig. 1] comprising:
an arithmetic processing unit [cluster];
a plurality of peripheral circuits [peripheral devices] which are controlled by the arithmetic processing unit; and
a timing management circuit which outputs a result of time measurement executed according to a request for the time measurement from each of the peripheral circuits to the peripheral circuit, wherein the timing management circuit executes the time measurement according to each request for the time measurement [Col. 5 lines 22-44: peripheral subsystem 12 upon detecting later-described data processing events requests host processors 10 to supply a current time of the TOD clock 15 as a host time stamp. Peripheral subsystem 12 responds to the predetermined data processing events to send a data channel attention message (ATT'N) 40 to host processors 10 over a selected path group for requesting a host processor 10 to send a host time stamp] [Col. 7 lines 53-Col. 8 lines 20].
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Regarding claim 2, Beardsley discloses the semiconductor device according to claim 1, wherein, when the timing management circuit receives a first request for a first time measurement from any one of the plurality of the peripheral circuits, the timing management circuit starts the first time measurement, and wherein, when the timing management circuit receives a second request for a second time measurement during execution of the first time measurement, the timing management circuit starts the second time measurement, while continuing to execute the first time measurement [Col. 2 lines 3-12] [Col. 8 lines 53-63: a host processors 10 also can supply a new host time stamp to peripheral subsystem 12 and to other peripheral subsystems 13].
Regarding claim 3, Beardsley discloses the semiconductor device according to claim 2, further comprising a clock generation circuit which generates a clock signal serving as a reference for the time measurement in the timing management circuit, wherein the timing management circuit executes the first time measurement and the second time measurement on a basis of the same clock signal generated in the clock generation circuit, when executing the first time measurement and the second time measurement [the host clock generates timestamps according the peripheral requests][Col. 2 lines 47-61][Col. 3 lines – Col. 4 lines 14].
Regarding claim 4, Beardsley discloses the semiconductor device according to claim 1, wherein the timing management circuit executes the time measurement by receiving the request for the time measurement from the peripheral circuit, and wherein the timing management circuit stops the time measurement until it receives a next request after outputting all of the results of the time measurement of the received requests [the host clock generates timestamps according the peripheral requests] [Col. 2 lines 3-12] [Col. 8 lines 53-63].
Regarding claim 9, Beardsley discloses the semiconductor device according to claim 1, wherein the timing management circuit has a determination section which determines whether the request for the time measurement from the peripheral circuit is enabled, and wherein, in at least either one of a case in which the time measurement being executed is not continued or a case in which the number of requests for the time measurement to be measurable simultaneously exceeds a maximum, the determination section rejects the request for the time measurement from the peripheral circuit [Col. 10 lines 64 – Col. 11 lines 11: If in machine step 105 the third time out expires, then support facility 32 builds a time-stamp error entry for SFLOG 39 indicating or reflecting that three requests to host processors 10 failed to obtain a host time stamp][Claim 14].
Regarding claim 10, Beardsley discloses the semiconductor device according to claim 9, wherein the peripheral circuit has a counter function of executing the time measurement, and wherein, when rejecting the request, the determination section causes the peripheral circuit to execute the time measurement with use of the counter function of the peripheral circuit [Col. 18 lines 49 to Col. 19 lines 35: entering in said LOG portion a request error entry indicating failure of said time-stamp requests for said host time stamp and time stamping the request error entry the time of said first peripheral time].
Regarding claims 12 -15, these claims are taught by Beardsley for the same reasons as set forth in claims 1-4 above.
Regarding claim 20, this claim is taught by Beardsley for the same reasons as set forth in claim 1 above.
Allowable Subject Matter
Claims 5 – 8, and 11, 16-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The prior arts of record do not disclose nor suggest the limitations recited in claims 5 – 8, and 11, 16-19.
Conclusion
Examiner's note: Examiner has cited particular paragraphs and columns and line numbers in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner (see MPEP § 2123).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PHIL K NGUYEN whose telephone number is (571)270-3356. The examiner can normally be reached 9:30 a.m - 5 p.m.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jaweed Abbaszadeh can be reached at (571)270-1640. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PHIL K NGUYEN/Primary Examiner, Art Unit 2176