Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I and Species 1a in the reply filed on July 13th, 2026, is acknowledged.
Priority
The instant application claim of the priority date of March 17th, 2023, of the foreign application
JAPAN 2023-043226 is noted and entered. Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) was submitted on March 4th, 2024. This submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Claim Objections
Claim 9 is objected to because of the following informalities:
In claim 9, “the first plug is electrically insulated from the second electrode layer” should read “the first plug is electrically insulated from the second electrode”.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5 and 8-10 are rejected under 35 U.S.C. 102as being anticipated by Yoshinaga et al, US 20190287903 A1 (Yoshinaga).
Regarding claim 1; Yoshinaga teaches a semiconductor device (Fig. 2: semiconductor memory device 100) comprising:
a stacked film (See Yoshinaga annotated Fig. 2 shared in this OA; Para. 28: "For example, conductivity layers 34a, 34b, 34c, 34d, 34e, 34f, 34g, 34h, and 34i are stacked with the insulating layer 33 therebetween.") including a plurality of electrodes (Fig. 2: conductivity layers 34a, 34b, 34c, 34d, 34e, 34f, 34g, 34h, and 34i),
which includes a first electrode (Fig. 2: conductivity layer 34f),
and a plurality of first insulating films alternately stacked in a first direction (Fig. 7I: insulating layer 33 formed from insulating film 62, oxide film 94, and surface layer 98);
a plurality of plugs extending through the stacked film in the first direction (Fig. 2: electrode members 58),
the plurality of plugs including a first plug (Fig. 4: electrode member 58b) electrically connected to the first electrode (Fig. 4; Para. 39: "The electrode member 58b is connected to the conductivity layer 34f");
and a columnar portion (Fig. 3: memory hole 70) extending through the stacked film in the first direction,
the columnar portion including a charge storage layer (Fig. 3: charge accumulation film 73) and a semiconductor layer (Fig. 3: channel body 41; Para. 55: "The channel body 41 is a pillar including a semiconductor material such as silicon, for example."),
wherein the first electrode includes a metal layer (Fig. 4: conductivity layer 34f; Para. 43: "As an example of materials of the conductivity layers 34a, 34b, 34c, 34d, 34e, 34f, 34g, 34h, and 34i, tungsten, titanium nitride, or copper is preferably used.") and the first plug includes a metal layer (Fig. 4: electrode member 58b; Para. 44: "As an example of materials of the electrode members 58a, 58b, and 58c (and other electrode members described above (not shown in the drawings)), tungsten, titanium nitride, or copper is preferably used.") that is integrally formed (Fig. 4; Para. 80: "The conductivity layer 34 and the electrode member 58 are integrally formed by the second conductivity material") with the metal layer of the first electrode (Fig. 4: conductivity layer 34f) and formed of a same material as a material of the metal layer of the first electrode (Para. 43: "As an example of materials of the conductivity layers 34a, 34b, 34c, 34d, 34e, 34f, 34g, 34h, and 34i, tungsten, titanium nitride, or copper is preferably used."; Para. 44: "As an example of materials of the electrode members 58a, 58b, and 58c (and other electrode members described above (not shown in the drawings)), tungsten, titanium nitride, or copper is preferably used.")).
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Regarding claim 2; Yoshinaga teaches all the limitations of the semiconductor device according to claim 1,
wherein the metal layer of the first electrode includes a first metal layer (Fig. 4: conductivity layer 34f; Para. 43: "As an example of materials of the conductivity layers 34a, 34b, 34c, 34d, 34e, 34f, 34g, 34h, and 34i, tungsten, titanium nitride, or copper is preferably used.") and a second metal layer (Fig. 4: part of barrier metal film 36f; See Yoshinaga annotated fig. 4 shared in this OA) provided on at least an upper surface and a lower surface of the first metal layer (Fig. 4: barrier metal film 36f on upper and lower surface of conductivity layer 34f),
and the metal layer of the first plug includes a third metal layer (Fig. 4: electrode member 58b) that is formed of a same material (Fig. 4; Para. 44: "As an example of materials of the electrode members 58a, 58b, and 58c (and other electrode members described above (not shown in the drawings)), tungsten, titanium nitride, or copper is preferably used.") as a material of the first metal layer,
and a fourth metal layer provided on at least a side surface of the third metal layer (Fig. 4: part of barrier metal film 36f on side surface of electrode member 58b; See Yoshinaga annotated fid. 4 shared in this OA),
the fourth metal layer being formed of a same material as a material of the second metal layer (Para. 63: “The barrier metal films 36a, 36b, 36c, 36d, 36e, 36f, 36g, and 36h include, for example, titanium nitride (TiN)”).
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Regarding claim 3; Yoshinaga teaches all the limitations of the semiconductor device according to claim 2,
wherein the first metal layer (Fig. 4: conductivity layer 34f) of the first electrode is integrally formed with the third metal layer (Fig. 4: electrode member 58b) of the first plug (Fig. 4; Para. 80: "The conductivity layer 34 and the electrode member 58 are integrally formed by the second conductivity material"),
and the second metal layer of the first electrode is integrally formed with the fourth metal layer of the first plug (Para. 63: “The barrier metal films 36a, 36b, 36c, 36d, 36e, 36f, 36g, and 36h include, for example, titanium nitride (TiN)”).
Regarding claim 4; Yoshinaga teaches all the limitations of the semiconductor device according to claim 2, wherein the first metal layer of the first electrode is not separated from the third metal layer of the first plug by the second and fourth metal layers (Fig. 4: conductivity layer 34f is not separated from electrode member 58b).
Regarding claim 5; Yoshinaga teaches all the limitations of the semiconductor device according to claim 2,
wherein the first metal layer contains a first metal element (Fig. 4: conductivity layer 34f; Para. 43: "As an example of materials of the conductivity layers 34a, 34b, 34c, 34d, 34e, 34f, 34g, 34h, and 34i, tungsten, titanium nitride, or copper is preferably used."),
and the second metal layer contains a second metal element different from the first metal element (Fig. 4; Para. 63: "The barrier metal films 36a, 36b, 36c, 36d, 36e, 36f, 36g, and 36h include, for example, titanium nitride (TiN)").
Regarding claim 8; Yoshinaga teaches all the limitations of the semiconductor device according to claim 1,
wherein the stacked film includes a stepped structure (Fig. 2: first staircase region),
and the first plug (Fig. 2: electrode member 58b) extends through the stepped structure (Fig. 2: first staircase region) of the stacked film.
Regarding claim 9; Yoshinaga teaches all the limitations of the semiconductor device according to claim 1,
wherein the plurality of electrodes includes a second electrode (Fig. 4: conductivity layer 34c) and the first plug (Fig. 4: electrode member 58b) is electrically insulated from the second electrode layer.
Regarding claim 10; Yoshinaga teaches all the limitations of the semiconductor device according to claim 9, further comprising:
a third insulating film (Fig. 4: insulating layer 33b) provided between the first plug (Fig. 4: electrode member 58b) and the second electrode (Fig. 4: conductivity layer 34c).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection note: An italicized claim limitation indicates claim limitations that are not explicitly disclosed by the primary reference but are disclosed by the secondary reference(s).
Claims 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over Yoshinaga et al, US 20190287903 A1 (Yoshinaga) in view of Son et al, US 20190326316 A1 (Son).
Regarding claim 6; Yoshinaga teaches all the limitations of the semiconductor device according to claim 5.
Yoshinaga fails to teach the semiconductor device according to claim 5 further comprising: a second insulating film provided on an upper surface of the first electrode and a side surface of the first plug, wherein the second insulating film contains a third metal element different from the first and second metal elements.
However, Son teaches further comprising:
a second insulating film (Figs. 3A and 3C: second blocking layer 470; Para. 46) provided on an upper surface of the first electrode and a side surface of the first plug (See Son annotated Fig. 3C shared in this OA: second blocking layer 470 on upper surface of gate electrode 485 and side surface of second extension portion 510b of first upper contact plug 510),
wherein the second insulating film contains a third metal element (Fig. 3C; Para. 46: "The second blocking layer 470 may include a metal oxide, e.g., aluminum oxide, hafnium oxide, etc.") different from the first and second metal elements.
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Yoshinaga and Son are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Yoshinaga by having a second insulating film on an upper surface of the first electrode and side surface of the first plug wherein the second insulating film contains a third metal element different from the first and second metal elements as disclosed in Son to control the bandgap and block electron movement.
Regarding claim 7; Yoshinaga teaches all the limitations of the semiconductor device according to claim 1.
Yoshinaga fails to teach the semiconductor device according to claim 1 further comprising: a second insulating film provided on an upper surface of the first electrode and a side surface of the first plug.
However, Son teaches further comprising:
a second insulating film (Figs. 3A and 3C: second blocking layer 470; Para. 46) provided on an upper surface of the first electrode and a side surface of the first plug (See Son annotated Fig. 3C shared in this OA: second blocking layer 470 on upper surface of gate electrode 485 and side surface of second extension portion 510b of first upper contact plug 510).
Yoshinaga and Son are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Yoshinaga by having a second insulating film on an upper surface of the first electrode and side surface of the first plug as disclosed in Son to control the bandgap and block electron movement.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AUBRIE I HETHERINGTON whose telephone number is (571)270-0666. The examiner can normally be reached M-Th 7:30-5, Fr 7:30-4.
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/AUBRIE IRENE HETHERINGTON/Examiner, Art Unit 2817 8/24/2026
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817
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