Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Application
This action is in response to Applicant's application filed 4 March 2024. Claims 1-20 are presently pending and under consideration.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 4 March 2024 and 27 March 2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Specification
The specification is object to for the following reason: The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: Memory System Command Scheduling and Priority Adjustment based on Congestion.
Claim Objections
Claims 14 and 17 are objected to because of the following informalities: it appears the recitation of “first command” should be plural similar to the recitation of “first commands” in claim 1. Appropriate correction or clarification is required.
Claim 17 further recites “determining a throughput based a congestion degree”. It appears the claim should recite “determining a throughput based ON a congestion degree”. Appropriate correction or clarification is required.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 14, 16, 17, 19, and 20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to a judicial exception of an abstract idea without significantly more. Independent claim 14 recites scheduling first and second commands according to a congestion degree at an egress port and fill-level of response buffer, and independent claim 17 recites determining a throughput based on a congestion degree of an egress port, determining a time window based on a fill-level of a response buffer, and scheduling second and first commands while adjusting second priority according to comparing the time window and execution times of the second commands.
The limitations of scheduling first and second commands according to a congestion degree at an egress port and fill-level of response buffer, as in independent claim 14 and determining a throughput based on a congestion degree, determining a time window based on a fill-level of a response buffer, and scheduling second and first commands while adjusting priority according to comparing the time window and execution times of the second commands, as in independent claim 17, under its broadest reasonable interpretation, covers performance of the limitation entirely in the mind but for the recitation of generic computer components (i.e. generic computer components comprising a memory controller, an egress port, a response buffer, a memory device). That is, other than reciting a memory controller, an egress port, a response buffer, and memory device, nothing in the claim precludes the steps from practically being performed entirely in the mind. In this case, first and second commands are scheduled according to a congestion degree at an egress port and fill-level of response buffer, as in independent claim 14 and second and first commands are scheduled while adjusting priority according to comparing a determined time window and execution times of the second commands, as in independent claim 17. If a claim limitation under its broadest reasonable interpretation, covers performance of the limitation in the mind but for the recitation of generic computer components, then it falls within the “Mental Processes” grouping of abstract ideas. Accordingly, the claim recites an abstract idea.
This judicial exception is not integrated into a practical application. In particular, the claims recite the additional elements of “a memory controller”, “an egress port”, “a response buffer”, and “a memory device”. The “a memory controller”, “an egress port”, “a response buffer”, and “a memory device” are recited a high level of generality (i.e. generic computer components performing generic computer functions), such that they amount to no more than mere instructions to apply the exception using generic computer components. Accordingly, the additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on the performing the mental process.
The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of “a memory controller”, “an egress port”, “a response buffer”, “a memory device” amount to no more than mere instructions to apply the exception using generic computer components. Mere instructions to apply an exception using generic computer components cannot provide an inventive concept. Accordingly, the claim is not patent eligible.
Additionally, dependent claims 16, 18, 19, and 20 recite additional elements that, under their broadest reasonable interpretation, are capable of being performed entirely in the mind or merely a mathematical calculation but for the recitation of generic computer components. Dependent claim 16 recites a “determined”, a “determined”, a “determined”, and a “adjusted” steps, dependent claim 19 recites a “determining”, a “increasing”, a “determination”, a “decreasing”, a “determination” steps, and dependent claim 20 recites a “adjusting”, a “aligning”, a “comparing”, a “determination”, a “determination” steps, which under its broadest reasonable interpretation, covers performance of the limitations entirely in the mind or merely mathematical calculations but for the recitation of generic computer components and dependent claim 18 recites a “storing” step, a “generating” step, and a “generating” step which are mere “data gathering and output”, which amounts to insignificant extra-solution activity (see MPEP 2106.05(g)). The claims do not include additional elements that are sufficient to amount to significantly more than the judicial exception and therefore are also patent ineligible.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-3, 12 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Kajihara (US 2023/0090008 A1, hereinafter Kajihara) in view of Kim (US 2016/0117119 A1, hereinafter Kim), further in view of Zhao et al (US 2020/0020384 A1, hereinafter Zhao).
Regarding claim 1, Kajihara discloses a memory controller comprising: (See Kajihara, Fig. 1, disclosing memory controller 10 and [0041] disclosing same);
a congestion monitoring circuit configured to monitor a congestion degree at an egress port of the memory controller (See Kajihara, Fig. 1 disclosing Congestion degree determination circuit 140 and [0053], [0057] disclosing the same);
a priority control circuit configured to adjust a priority of commands to process second commands prior to first commands corresponding to a host-requested operation (See Kajihara, [0041], disclosing memory system writes user data of write requests received from host device, [0043], disclosing the memory controller may be realized by a dedicated circuit and [0063], disclosing command flow control circuit 150 prioritizing requests for execution), based on the congestion degree at the egress port (See Kajihara, [0057] & [0059], disclosing congestion degree determination circuit and number of requests stored in the write request FIFO ); and
a command generation circuit configured to schedule the first commands and the second commands according to the priority and output the scheduled commands to the memory device (See Kajihara, [0054]-[0056], disclosing FIFO buffers with prioritized requests and [0059], disclosing the command flow control circuit determines based on congestion degree whether to execute an operation of prioritized requests within the FIFO buffers).
Kajihara does not disclose a response buffer configured to store responses provided from a memory device and adjusting a priority of commands based on a fill-level of the response buffer and the second commands corresponding to an internal operation.
However, Kim discloses a response buffer configured to store responses provided from a memory device (See Kim, Fig 1, disclosing storage device 1300 and RAM including completion queue 1 and 2, and [0060], disclosing completion queues CQ1 and CQ2) and adjusting a priority of commands based on a fill-level of the response buffer (See Kim, [0144], disclosing adjusting command fetch manner based on a round robin depending on whether the completion queue is full, or in other words, adjusting command execution order/priority based on queue fill).
Kajihara and Kim are analogous art directed to improved memory management techniques. It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to combine the congestion aware memory system of Kajihara with the completion queue awareness of Kim as memory system performance can be improved by adjusting command fetching to prevent degradation of the operation of the storage device.
Neither Kajihara nor Kim disclose the second commands corresponding to an internal operation.
However, Zhao discloses the second commands corresponding to an internal operation (See Zhao, [0011] disclosing prioritizing of commands including first and second access types and refresh).
Kajihara, Kim, and Zhao are analogous art directed to improved memory management techniques. It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to combine the memory system of Kajihara and Kim with the prioritized refresh handling of Zhao as memory system performance can be improved by adaptively handling requests based on priority needs which include necessary refresh operations (See Zhao, [0046], disclosing prioritizing urgent refreshes).
Regarding claim 2, Kajihara in view of Kim, further in view of Zhao disclosed the memory controller of claim 1 as above. Kajihara in view of Kim, further in view of Zhao further discloses wherein the first commands include commands for performing an operation requested from a host device (See Kajihara,0041], disclosing memory system writes user data of write requests received from host device), wherein the second commands include commands for performing the internal operation that is not requested from the host device (See Zhao, [0011], disclosing refresh commands generated by refresh logic of the memory controller).
Regarding claim 3, Kajihara in view of Kim, further in view of Zhao disclosed the memory controller of claim 1 as above. Zhao further discloses wherein the second commands include at least one of a write-queue flush command, a refresh command or a scrubbing command (See Zhao, [0011], disclosing refresh commands generated by refresh logic of the memory controller).
Regarding claim 12, Kajihara in view of Kim further in view of disclosed the memory controller of claim 1 as above. Zhao further discloses wherein the command generation circuit includes: a first command generator configured to generate the first commands in response to a request from a host device (See Zhao, Fig 5 and [0033], disclosing command queue 520);
a second command generator configured to generate the second commands corresponding to the internal operation regardless of the request from the host device, based on the priority (See Zhao, Fig. 5 and [0035], disclosing refresh logic 532);
a request queue configured to store the first commands and the second commands (See Zhao, Fig. 5 and [0031] disclosing Queue 514); and
an output control circuit configured to schedule the first commands and the second commands stored in the request queue, according to the priority (See Zhao, arbiter 538 and [0039], “efficiently schedule memory accesses” and [0043], “arbiter 538 selects memory access requests (commands) from command queue 520 and refresh logic 532 by taking into account….the priority of each refresh command”).
Regarding claim 14, Kajihara discloses a memory system comprising: a memory device (See Kajihara Fig. 1 disclosing memory system 3 and memory 20 and [0041] disclosing same); and a memory controller configured to schedule second commands to be processed prior to first command corresponding to a host-requested operation (See Kajihara Fig. 1, disclosing memory controller 10 and [0041] disclosing memory controller 10 and the memory system writes user data of write requests received from host device), according to a congestion degree at an egress port of the memory system (See Kajihara, [0043], disclosing the memory controller may be realized by a dedicated circuit and [0063], disclosing command flow control circuit 150 prioritizing requests for execution).
Kajihara does not disclose second commands corresponding to an internal operation and scheduling commands according to a fill-level of a response buffer configured to store responses provided from the memory device.
Kim discloses scheduling commands according to a fill level of a response buffer configured to store responses provided from the memory device (See Kim, [0144], disclosing adjusting command fetch manner based on a round robin depending on whether the completion queue is full, or in other words, adjusting command schedule based on queue fill).
Kajihara and Kim are analogous art directed to improved memory management techniques. It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to combine the congestion aware memory system of Kajihara with the completion queue awareness of Kim as memory system performance can be improved by adjusting command fetching to prevent degradation of the operation of the storage device.
Neither Kajihara nor Kim disclose the second commands corresponding to an internal operation.
However, Lasserre discloses the second commands corresponding to an internal operation (See Lasserre, [0016]& [0017] disclosing priority adjustment of commands including read and write and refresh).
Kajihara, Kim, and Lasserre are analogous art directed to improved memory management techniques. It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to combine the memory system of Kajihara and Kim with the prioritized refresh handling of Lasserre as memory system performance can be improved by adaptively handling requests based on priority needs which include necessary refresh operations (See Lasserre, [0016], disclosing priority handler selecting highest priority requests from itself and also refresh scheduler).
Allowable Subject Matter
Claims 4-11 and 13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 15, 16, and 18-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims and if the rejection of claims 14, 16, 17, 19 and 20 under 35 USC 101 were to be overcome.
The following is a statement of reasons for the indication of allowable subject matter: A search of the prior art returned the following closest prior art:
(1) Kajihara (US 2023/0090008 A1) discloses a memory system and memory controller utilizing a congestion degree determination circuit and command flow control circuit to control execution of storage operation.
(2) Kim (US 2016/0117119 A1) discloses a storage device operating method utilizing the fullness of a completion queue to adjust the manner in which commands are fetched.
(3) Zhao et al (US 2020/0020384 A1) discloses a memory controller handling prioritized commands in a command queue together with prioritized refresh commands.
(4) Putti et al (US 2025/0279130 A1) discloses a memory controller including a refresh scheduler configured to monitor a status of a dynamically changing refresh requirement for the DRAM, determine an alert level for the DRAM based at least in part on the status of the refresh requirement, and manage, based on the determined alert level, the DRAM banks to which refresh commands are sent and the memory transactions for which memory request commands are sent by the request scheduler.
However, the prior art alone or in combination fails to teach or fairly suggest the combination of:
wherein the congestion monitoring circuit is configured to determine an average congestion rate by tracking the congestion degree at the egress port for each monitoring section, and wherein the priority control circuit is configured to determine a throughput based on the average congestion rate, determine a time window according to the fill-level of the response buffer and the throughput, and adjust the priority to process the second commands prior to the first commands by increasing the priority of the second commands according to a result of comparing the time window with execution times for the second commands, as in dependent claim 4. Claims 5-7 depend from and thus incorporate the allowable subject matter of dependent claim 4 and therefore would be allowable for at least the same reasons.
Nor does the prior art alone or in combination teach or fairly suggest the combination of: the memory controller response buffer is configured to transmit a response and a valid signal indicating that the response is valid, in response to a ready signal, and wherein the congestion monitoring circuit is configured to determine an average congestion rate corresponding to the congestion degree at the egress port, by sampling cases in which a back-pressured condition has occurred for each monitoring section based on the ready signal and the valid signal, as in dependent claim 8.
Nor does the prior art alone or in combination teach or fairly suggest the combination of the memory controller priority control circuit includes: a window determination circuit configured to determine a throughput based on the congestion degree at the egress port, and determine a time window according to a ratio of the fill-level of the response buffer and the throughput; and a scheduling control circuit configured to increase the priority of the second commands according to a result of comparing the time window with execution times for the second commands, as in dependent claim 11.
Nor does the prior art alone or in combination teach or fairly suggest the combination of: the memory controller including a response counter configured to generate the fill-level by counting a number of valid responses stored in the response buffer; and a transmitter configured to provide a ready signal to the response buffer and provide a response signal to a host device through the egress port, according to a valid signal provided from the response buffer, as in dependent claim 13.
Nor does the prior art alone or in combination teach or fairly suggest the combination of: the memory controller configured to store a plurality of sampling signals obtained by sampling a ready signal and a valid signal, which are input to and output from the response buffer, at preset sampling intervals; generate a back-pressured count value by counting a number of sampling signals that satisfy a back-pressured condition, among the sampling signals, and generate an average congestion rate corresponding to the congestion degree at the egress port, by tracking the back-pressured count value for each monitoring section, as in dependent claim 15.
Nor does the prior art alone or in combination teach or fairly suggest the combination of:
the memory controller configured to determine an average congestion rate by tracking the congestion degree at the egress port, determine a throughput based on the average congestion rate, determine a time window according to a ratio of the fill-level of the response buffer and the throughput, and adjust a priority of the second commands by increasing the priority according to a result of comparing the time window with execution times for the second commands, as in dependent claim 16.
Nor does the prior art alone or in combination teach or fairly suggest the combination of: a method of operating a memory controller comprising: determining a throughput based on a congestion degree at an egress port of the memory controller, determining a time window according to a fill-level of a response buffer that stores responses provided from a memory device and the throughput; and scheduling second commands corresponding to an internal operation and first command corresponding to a host-requested operation, while adjusting a priority of the second commands according to a result of comparing the time window with execution times for the second commands, as in independent claim 17. Claims 18-20 depend from and thus incorporate the allowable subject matter of dependent claim 4 and therefore would be allowable for at least the same reasons.
Conclusion
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/E.H.K/Examiner, Art Unit 2137 /RYAN BERTRAM/Primary Examiner, Art Unit 2137