DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of claims 1-20 in the reply filed on 09/16/2026 is acknowledged.
Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically teaches d as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 11-12 & 17 are rejected under 35 U.S.C. 103 as being unpatentable over Choi et al. (US 9343601 B2)
Regarding claim 11, Choi teaches,
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An image sensor (Fig. 2) comprising:
a semiconductor substrate (100) comprising a top surface and a bottom surface;
a two-dimensional (2D) material layer (including 200 & 350 comprising 2D sheet of 200 , col. 5, ll. 28-30) on the top surface of the semiconductor substrate and comprising molybdenum disulfide (MoS2) (350 may include MoS2, col. 6, l. 32);
and a top absorber (second graphene layer 300, Col. 6 , l. 20) on a top surface of the 2D material layer and comprising graphene (300 is a graphene layer),
wherein the 2D material layer comprises 2D sheets (first graphene 200 may be provided in a shape of, for example, a two-dimensional (2D) sheet (col. 5, ll. 28-30) …....
and wherein the top absorber comprises a monolayer of graphene (300 may be single layer, col. 5 , l. 30).
But Choi does not explicitly teach,
…comprising from two to five layers stacked in a vertical direction on the top surface of the semiconductor substrate,
But Choi additionally teaches,
first graphene 200 and the second graphene 300 may be provided in a shape of, for example, a two-dimensional (2D) sheet including a single layer, however, is not limited thereto(col. 5, ll. 28-30) which renders 200 might be provided with multiple layers as well.
Thus, it would have been obvious to try by one of ordinary skill in the art before the effective filing date of the claimed invention to use multiple 2-D sheets of 200 such that 2D material layer comprises 2D sheets comprising from two to five layers stacked in a vertical direction on the top surface of the semiconductor substrate, according to the teaching of Choi, in order to have a photo detection layer provided through vertical tunneling junction , as taught by Choi ( Col. 1, ll. 14-16), since it has been held that choosing from a finite number of identified, predictable solutions such as multiple sheet of 2-D graphene layer as taught by Choi above, with a reasonable expectation of success is obvious. KSR Int'l v. Teleflex Inc., 127 S.Ct. 1727 (2007).
Regarding claim 12, Choi teaches the image sensor of claim 11 but does not explicitly teach, wherein the 2D material layer has a thickness in a range of from about 1.5 nanometers to about 3.5 nanometers.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to have the thickness in a range of from about 1.5 nanometers to about 3.5 nanometers, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (CCPA 1955).
Regarding claim 17, Choi teaches the image sensor of claim 11 and further teaches , wherein the top absorber(300) covers an entirety of the top surface of the 2D material layer(200).
Claims 1-7, 9-10, 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Choi et al. (US 9343601 B2) in view of DU, Si-Chao (CN 114613795 A)
Regarding claim 1, Choi teaches,
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An image sensor (Fig. 2) comprising:
a semiconductor substrate (100) comprising a top surface and a bottom surface;
a two-dimensional (2D) material layer (including 200 & 350 comprising 2D sheet of 200 , col. 5, ll. 28-30) on the top surface of the semiconductor substrate and comprising molybdenum disulfide (MoS2) (350 may include MoS2, col. 6, l. 32); and
a top absorber (second graphene layer 300, Col. 6 , l. 20) on a top surface of the 2D material layer and comprising graphene (300 is a graphene layer) , wherein the semiconductor substrate comprises silicon ……(100 may be a silicon substrate, col. 4, l. 43),
wherein the 2D material layer has n-type conductivity (first graphene 200 may be n-type conductivity, col. 5, l. 7) ,
and wherein the semiconductor substrate and the 2D material layer are configured to form a p-n diode (“the first graphene 200, the inserting layer 350, and the second graphene 300, which are sequentially stacked on the substrate 100, may form p-n vertical junction diodes”, see col. 6, ll. 50-52).
But Choi does not explicitly teach,
wherein the semiconductor substrate (100) comprises silicon (silicon of 100) doped with a p-type impurity
But, DU, Si-Chao (CN 114613795 A) teaches,
Silicon substrate doped with P type ……., which is good for the light absorption of the substrate to surface graphite the optical current (see yellow highlighted in attached foreign reference)
It would have been obvious to one of ordinary skill in art before the effective filing date of the claimed invention to dope the substrate 100 with P -type conductivity such that p-type semiconductor substrate 100 and 2-D material layer (n-type graphene 200) obviously forms a p-n diode, according to teaching of Du, Si-Chao, in order to have good light absorption of the substrate to surface graphite the optical current, as taught by Du, Si-Chao above.
Regarding claim 2, Choi & Du, Si-Chao teach the image sensor of claim 1 but does not explicitly teach, wherein the 2D material layer comprises 2D sheets comprising from two to five layers stacked in a vertical direction on the top surface of the semiconductor substrate.
But Choi additionally teaches,
first graphene 200 and the second graphene 300 may be provided in a shape of, for example, a two-dimensional (2D) sheet including a single layer, however, is not limited thereto(col. 5, ll. 28-30) which renders 200 might be provided with multiple layers as well.
Thus, it would have been obvious to try by one of ordinary skill in the art before the effective filing date of the claimed invention to use multiple 2-D sheets of 200 such that 2D material layer comprises 2D sheets comprising from two to five layers stacked in a vertical direction on the top surface of the semiconductor substrate, according to the teaching of Choi, since it has been held that choosing from a finite number of identified, predictable solutions such as multiple sheet of 2-D graphene layer as taught by Choi above, with a reasonable expectation of success is obvious. KSR Int'l v. Teleflex Inc., 127 S.Ct. 1727 (2007).
Regarding claim 3, Choi & Du, Si-Chao teaches the image sensor of claim 1 and further teaches , wherein the top absorber comprises a monolayer of graphene (300 may be single layer, col. 5 , l. 30)
Regarding claim 4, Choi & Du, Si-Chao teaches the image sensor of claim 1 but does not explicitly teach, wherein the 2D material layer has a thickness in a range of from about 1.5 nanometers to about 3.5 nanometers.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to have the thickness in a range of from about 1.5 nanometers to about 3.5 nanometers, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (CCPA 1955).
Regarding claim 5, Choi & Du, Si-Chao teaches the image sensor of claim 1 and further teaches , further comprising: a first electrode (310, Fig. 2) on the top absorber and electrically connected to the 2D material layer ; and a second electrode (210) electrically connected to the semiconductor substrate (via 200, See Fig. 2) .
Regarding claim 6, Choi & Du, Si-Chao teaches the image sensor of claim 1 and further teaches , wherein the semiconductor substrate comprises a doped region (p doped as rejected in claim 1) , and wherein the doped region comprises a p-type impurity (see claim 1 rejection above).
Regarding claim 7, Choi & Du, Si-Chao teaches the image sensor of claim 6 and further teaches , wherein the doped region and the 2D material layer are configured to form a narrow-width depletion region in a junction portion between the doped region and the 2D material layer (obvious depletion region formed at the interface of p-n junction formed by p-type substrate 100 and 2D material 200, see claim 1 rejection).
Regarding claim 9, Choi & Du, Si-Chao teaches the image sensor of claim 1 and further teaches, wherein the top absorber has a thickness ranging from 0.1 nanometers to 1 nanometer.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to have the thickness in a range of from 0.1 nanometers to 1 nanometer, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (CCPA 1955).
Regarding claim 10, Choi & Du, Si-Chao teaches the image sensor of claim 1 and further teaches , wherein the top absorber (300) covers an entirety of the top surface of the 2D material layer (200).
Regarding claim 14, Choi teaches the image sensor of claim 11 and further teaches ……..wherein the semiconductor substrate and the 2D material layer are configured to form a p-n diode (“the first graphene 200, the inserting layer 350, and the second graphene 300, which are sequentially stacked on the substrate 100, may form p-n vertical junction diodes”, see col. 6, ll. 50-52) but does not explicitly teach,
, wherein the semiconductor substrate comprises silicon doped with a p-type impurity, wherein the 2D material layer has n-type conductivity,
But, DU, Si-Chao (CN 114613795 A) teaches,
Silicon substrate doped with P type ……., which is good for the light absorption of the substrate to surface graphite the optical current (see yellow highlighted in attached foreign reference)
It would have been obvious to one of ordinary skill in art before the effective filing date of the claimed invention to dope the substrate with P -type conductivity such that p-type semiconductor substrate 100 and 2-D material layer (n-type graphene 200) obviously forms a p-n diode, according to teaching of Du, Si-Chao, in order to have good light absorption of the substrate to surface graphite the optical current, as taught by Du, Si-Chao above.
Regarding claim 15, Choi & Du, Si-Chao teaches the image sensor of claim 14 and further teaches , wherein the semiconductor substrate comprises a doped region ( p doped region as per claim 14 rejection above), and wherein the doped region and the 2D material layer are configured to form a narrow-width depletion region in a junction portion between the doped region and the 2D material layer (obvious depletion region formed at p type substate 100 and n type 200).
Claims 8 is rejected under 35 U.S.C. 103 as being unpatentable over Choi et al. in view of DU, Si-Chao and further in view of CHOI, Seongryul (CN 118610219 A)
Regarding claim 8, Choi & Du, Si-Chao teaches the image sensor of claim 1 and but does not explicitly teach , wherein the image sensor has an external quantum efficiency (EQE) greater than 100 %
But, CHOI, Seongryul (CN 118610219 A) teaches,
The image sensor according to one or more exemplary embodiments may have a quantum efficiency (or external quantum efficiency (EQE)) of greater than 100 % ……..this is because not only the relatively strong electric field is formed due to the depletion region of narrow width so that the electron-hole pair can be rapidly separated and carriers are generated, but also the top absorber of the graphene monolayer covering the entire top surface of the hybrid photodiode is used as a carrier multiplication member (see yellow highlighted in attached foreign reference of CHOI, Seongryul)
Thus, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to vary electric field in the depletion region of P-N junction formed by substrate 100 and 200 so that the electron-hole pair can be rapidly separated and carriers are generated such that EQE greater than 100 %, with routine experiment and optimization , since strong electric filed is important in order have high EQE, as taught by CHOI, Seongryul. In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990). See also In re Boesch, 205 USPQ 215 (CCPA) (discovery of optimum value of result effective variable in known process is ordinarily within skill of art) and In re Aller, 105 USPQ 233 (CCPA 1955) (selection of optimum ranges within prior art general conditions is obvious).
Claims 16 is rejected under 35 U.S.C. 103 as being unpatentable over Choi et al. and further in view of CHOI, Seongryul (CN 118610219 A)
Regarding claim 16, Choi teaches the image sensor of claim 11 but does not explicitly teach, wherein the image sensor has an external quantum efficiency (EQE) greater than 100 %.
But, CHOI, Seongryul (CN 118610219 A) teaches,
The image sensor according to one or more exemplary embodiments may have a quantum efficiency (or external quantum efficiency (EQE)) of greater than 100 % ……..this is because not only the relatively strong electric field is formed due to the depletion region of narrow width so that the electron-hole pair can be rapidly separated and carriers are generated, but also the top absorber of the graphene monolayer covering the entire top surface of the hybrid photodiode is used as a carrier multiplication member (see yellow highlighted in attached foreign reference of CHOI, Seongryul)
Thus, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to vary electric field in the depletion region of P-N junction formed by substrate 100 and 200 so that the electron-hole pair can be rapidly separated and carriers are generated such that EQE greater than 100 %, with routine experiment and optimization , since strong electric filed is important in order have high EQE, as taught by CHOI, Seongryul. In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990). See also In re Boesch, 205 USPQ 215 (CCPA) (discovery of optimum value of result effective variable in known process is ordinarily within skill of art) and In re Aller, 105 USPQ 233 (CCPA 1955) (selection of optimum ranges within prior art general conditions is obvious).
Allowable Subject Matter
Claims 13 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten to include all of the limitations of the base claim and any intervening claims.
With respect to claims 13 the prior art of record does not appear to teach, suggest, or provide motivation for combination to following limitation:
further comprising: a first electrode on the top absorber and electrically connected to the 2D material layer; and a second electrode on the bottom surface of the semiconductor substrate(claim 13).
Claims 18-20 are allowed.
With respect to claim 18, the prior art made of record does not teach or suggest either alone or in combination “a second electrode on a bottom surface of the semiconductor substrate and electrically connected to the doped region” in further combination with the additionally claimed limitations, as they are claimed by the Applicant.
Regarding claim 18, Choi et al. (US 9343601 B2) teaches,
An image sensor comprising a plurality of pixels ,
wherein each of the plurality of pixels comprises:
a doped region in a semiconductor substrate (100) and comprising a p-type impurity;
a two-dimensional (2D) material layer (including 200 & 350 comprising 2D sheet of 200 , col. 5, ll. 28-30) on a top surface of the semiconductor substrate and comprising molybdenum disulfide (MoS2) (350 may include MoS2, col. 6, l. 32);
a top absorber (second graphene layer 300, Col. 6 , l. 20) on a top surface of the 2D material layer and comprising graphene (300 is a graphene layer);
a first electrode (310) on the top absorber;
…… wherein the 2D material layer comprises 2D sheets (col. 5, ll. 28-30)
….and wherein the top absorber comprises a monolayer of graphene(300 may be single layer, col. 5 , l. 30)
But Choi does not explicitly teach,
a second electrode on a bottom surface of the semiconductor substrate and electrically connected to the doped region,
…..comprising from two to five layers stacked in a vertical direction on the top surface of the semiconductor substrate, .
But Choi additionally teaches,
first graphene 200 and the second graphene 300 may be provided in a shape of, for example, a two-dimensional (2D) sheet including a single layer, however, is not limited thereto(col. 5, ll. 28-30) which renders 200 might be provided with multiple layers as well.
Thus, it would have been obvious to try by one of ordinary skill in the art before the effective filing date of the claimed invention to use multiple 2-D sheets of 200 such that 2D material layer comprises 2D sheets comprising from two to five layers stacked in a vertical direction on the top surface of the semiconductor substrate, according to the teaching of Choi, since it has been held that choosing from a finite number of identified, predictable solutions such as multiple sheet of 2-D graphene layer as taught by Choi above, with a reasonable expectation of success is obvious. KSR Int'l v. Teleflex Inc., 127 S.Ct. 1727 (2007).
Choi still does not explicitly teach,
a second electrode on a bottom surface of the semiconductor substrate and electrically connected to the doped region
The other cited arts, either alone or in combination, fails to cure deficiencies of Choi.
Claims 19-20 are allowed being dependent on claim 18
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHATIB A RAHMAN whose telephone number is (571)270-0494. The examiner can normally be reached on MON-FRI 8:00 am- 5:00 pm (Arizona).
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/K.A.R/Examiner, Art Unit 2818
/STEVEN H LOKE/Supervisory Patent Examiner, Art Unit 2818
