DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 1-4, 6, 11-14, 16-22 objected to because of the following informalities:
Claim 1 recites, “wherein creating… wherein the controller…, and wherein after the physical block”, which as best understood by the Examiner in light of the specification should be amended to recite, “wherein creating…, wherein the controller…, and wherein after the physical block” (a comma should be added before “wherein the controller…” and after the “wherein creating…” clause).
Claim 1 recites, “the working memory for the memory device”, which as best understood by the Examiner in light of the specification should be amended to recite, “the working memory
Claim 14 recites, “wherein creating… wherein the first indication…, and wherein after the physical block”, which as best understood by the Examiner in light of the specification should be amended to recite, “wherein creating…, wherein the first indication…, and wherein after the physical block” (a command should be added before “wherein the first indication” and after the “wherein creating…” clause).
Claim 14 recites, “a first indication that indicates whether the physical block is referenced in a first region of a logical-to-physical table that is larger than the working memory”, which as best understood by the Examiner in light of the specification should be amended to recite, “a first indication that indicates whether the physical block is referenced in a first region of a logical-to-physical table, wherein the logical-to-physical table larger than the working memory” should apply to “a first indication”, “a first region of a logical-to-physical table” or “a logical-to-physical table”.
Claim 18 recites, “wherein creating… wherein the controller…, and wherein after the physical block”, which as best understood by the Examiner in light of the specification should be amended to recite, “wherein creating…, wherein the controller…, and wherein after the physical block” (a comma should be added before “wherein the controller…” and after the “wherein creating…” clause).
Claim 18 recites, “a first indication that indicates whether the physical block is referenced in a first region of a logical-to-physical table that is larger than the working memory”, which as best understood by the Examiner in light of the specification should be amended to recite, “a first indication that indicates whether the physical block is referenced in a first region of a logical-to-physical table, wherein the logical-to-physical table
Claims 2-4, 6, 11-13, 16-17, 19-22 are objected to for failing to correct the deficiencies of a base claim from which they depend.
Appropriate correction is required.
Claim Rejections - 35 USC § 112(b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 18-22 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 18:
Claim 18 recites, “the memory device having a working memory”. However, There is insufficient antecedent basis for this limitation in the claim because the claim does not previously recite a memory device having a working memory. Accordingly, the scope of the claim cannot be determined and the claim is indefinite. The Examiner suggests amending the claim to instead recite, “A non-transitory, machine-readable medium storing instructions that, when executed by a controller of a memory device having a working memory, cause the controller to: erase a physical block of memory elements of the memory device
Regarding claims 19-22:
Claims 19-22 are rejected for failing to cure the deficiencies of a rejected base claim from which they depend.
Claim Rejections – 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 6, 11-14 and 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over US Patent Application Publication No. US 2017/0075600 A1 (Jung) in view of US Patent No. US 9,529,705 B2 (Kim) as evidenced by US Patent Application Publication No. US 2015/0143197 A1 (Klein) and as motivated by US Patent Application Publication No. US 2010/0332730 A1 (Royer).
Regarding claim 1 and analogous claims 14 and 17-20:
Jung teaches, a memory device (storage device (300) implemented as a flash based memory device [0034] [Fig. 1]) comprising: memory elements (NVM (400) contains a plurality of blocks (410), which contain a plurality of pages (memory elements) of flash memory [0040] [0050] [Fig. 1]) and a controller (controller (310), including CPU that executes firmware (i.e., instructions stored in a non-transitory memory) for controlling the functions of the controller [0037] [Fig. 1]) configured to: erase a physical block of the memory elements (by teaching that the controller controls the erase operations of the physical blocks [0037], where the erase operation is performed on a block by block basis [0051])) and create a data structure, wherein the data structure comprises a first indication that indicates whether the physical block is referenced in a first region of a logical-to-physical table, wherein creating the data structure comprises changing the first indication to initialize the data structure based on the erasure to unset the first indication wherein the controller is configured such that the first indication is unset with initializing the whole data structure to a known state when the physical block is erased, and wherein after the physical block is written the first indication of the data structure is maintained at a set value until the physical block is erased (by teaching that the BITMAPK includes 8 bits (8 indications including a first indication) which correspond to eight mapping tables (8 regions of a mapping table including a first region). The bits are each used to index to one of the respective mapping tables. A logical ‘1’ indicates that the block contains a page included in the respective mapping table, whereas a logical ‘0’ (unset, with regard to claim 20) indicates that the block does not contain a page corresponding to the respective mapping table [0078-0084]. The BITMAP data structure may be created before writing to the block (S121) (S131) [Fig. 7] [Fig. 11]. From the entire disclosure, one of ordinary skill in the art would understand that when a block is newly written, all bits of the BITMAPK would initially be set to ‘0’ because the block containing the BITMAPK is erased (S121) (S131) [Fig. 7] [Fig. 9] [Fig. 10] [Fig. 11]. Furthermore, because the block is erased, no more pages of the block correspond to any of the respective mapping tables, and so for the BITMAPK to reflect this, it would include all ‘0’s [0078-0084] Each of the bits may be updated whenever data is written to at least one of the pages included in the data block that corresponds to a region of the mapping table indicated by the respective bit that was not previously referenced in the block (S122) (S132) [0081] [0083] [Fig. 7] [Fig. 9] [Fig. 10] [Fig. 11]. Furthermore, the bits of the bitmap would be erased whenever the block is erased as the bitmap is stored in a page of the block. Moreover, once a bit of the bitmap is set, there is not disclosed situation in which is unset except for erasure as the bits are only discussed as being set or maintained (such as when another LBA from the same portion of the mapping table is written to the block as a previous LBA written to the block) [0081-0082: “The controller 310 may update or set a first bit 430-1 corresponding to the mapping table MTA in the bitmap 430 to logic 1 from logic 0”…. “The controller 310 may maintain logic 1 that has been set as the first bit 430-1”] [0084-0085] [0089-0091]. Additionally, the controller is disclosed as controlling (310) the erasure operations, and therefore would be configured such that the first indication is unset with initializing the whole data structure to a known state when the physical block is erased as erasures occur at the block level (i.e., would apply to the whole data structure) whereas reads and programming would occur at the page level, which are also controlled by the controller [0037] [0051] [0056]) and a working memory, wherein the controller is configured to: read the data structure during a garbage collection of the physical block; and load only a portion of the logical-to-physical table into the working memory (by teaching the internal memory (350) (working memory) [Fig. 1]. Furthermore, the mapping table managed by the FTL is divided into eight tables and each table stores data for 100 logical address mappings [0043]. The mapping table is stored in the meta area [0048]. In this way, the controller may read and analyze the bitmap in order to determine the portions of the mapping table needed to perform garbage collection on the block, acquire these needed mapping tables (load only a portion of the logical to physical table into working memory that correspond to the mapping tables have an entry in the data structure that is set (i.e. according to the bitmap) (i.e., retrieving only the regions of the logical-to-physical table loaded into the working memory to perform the garbage collection according to claim 17 or retrieve only the portion of the regions of the logical-to-physical table needed to perform the garbage collection according to claim 19), and determine the validity of the pages in the block based on scanning through the acquired mapping tables for the physical addresses of the block [0093-0106] [Fig. 7]) wherein the portion of the logical-to-physical table comprises only those regions of the logical-to-physical table regions that have an asserted value in their respective indications in the data structure (by teaching that the mapping table managed by the FTL is divided into eight tables and each table stores data for 100 logical address mappings [0043]. The mapping table is stored in the meta area [0048]. In this way, the controller may read and analyze the bitmap in order to determine the portions of the mapping table needed to perform garbage collection on the block, acquire these needed mapping tables (load only a portion of the logical to physical table into working memory that correspond to the mapping tables have an entry in the data structure that is set (i.e. regions that have an asserted value in the respective indications in the data structure)), and determine the validity of the pages in the block based on scanning through the acquired mapping tables for the physical addresses of the block [0093-0106] [Fig. 7]).
Jung does not explicitly teach, but Kim as evidenced by Klein teaches to create the data structure in response to erasure of the physical block of memory; wherein the controller is configured such that the first indication is unset only with initializing the whole data structure to a known state when the physical block is erased, and wherein after the physical block is written the first indication of the data structure does not change from a set value until the physical block is erased (by teaching that a sub-bitmap for a block may be updated when the data block is erased (create a data structure – interpreted in line with Applicant’s specification which appears to indicate that creating a data structure involves initializing it to all 0’s [Applicant’s Specification, 0061]) [Kim, Col 2: line 30-40] [Kim, Col 6: lines 28-37]. The sub-bitmap may be stored in a meta area of a solid-state drive. The sub-bitmap functions in an analogous fashion to the BITMAPK of Jung, as a logic high for a bit indicates a page in the block which corresponds to a particular sub mapping table, and a logic low indicates there are no pages in the block which correspond to the particular sub mapping table, where the bits index to the corresponding sub mapping tables [Col 6: line 38 – Col 7: line 10, Kim]. The non-volatile memory device can program data in the meta area (122) with a single level cell method in order to improve the reliability of the data stored in the meta area, so that it is stored with a higher reliability than data stored in the user area (121) [Col 7: lines 18-26, Kim]. Furthermore, Klein teaches that a basic property of flash memory (as used in both Jung and Kim) is that a 0-bit can be changed to a 1-bit (setting the data structure), but not vice-versa (unset only with initializing) [Abstract, Klein]. In this way, writing a 0-bit or a 1-bit to flash memory are not symmetrical operations [0026, Klein]. If a block contains only 0s (initializing the whole data structure to a known state because it was freshly erased (with initializing the whole data structure)), individual bits can be changed to a 1, however, once a bit is set to 1, it can be changed back to a value of 0 only by erasing the entire block (i.e., bits can be set to 0 (unset) only with the initializing) (create a data structure in response to erasure of the physical block) [0026, Klein]. In this way, in order to update the BITMAP data structure (which has 1’s set due to previous writes to the block) in the metablock in response to the erasure as taught by Jung, the BITMAP would have to be erased with the block (create a data structure in response to the erasure). Then, if bits of the BITMAP are set again, they could not be unset until the metablock was again erased as evidenced through the mechanics of flash memory as taught by Klein, where the reading/writing and erasing of data are performed by the memory controller (as previously taught by Jung) as taught by Kim [Col 3: lines 51-55], [Col 7: line 40 – Col 8: line 21]) wherein the logical-to-physical table is larger than the working memory for the memory device (by teaching that conventionally, a non-volatile memory system has limited resources in the controller such that all the sub-mapping tables cannot be loaded at a time, such as in the SRAM as discussed [Col 10: lines 18-22]. Accordingly, only a portion may be loaded at a time and the others must be flushed back to non-volatile memory [Col 13: lines 55-67]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the use of the bitmap for indicating which mapping table portions are associated with pages programmed into a block as taught by Jung to include creating and updating the bitmaps by the controller in the meta region in a single level cell method, while storing user data by the controller in a two-level cell method in a user data area, and updating the bitmap with the controller in response to the erasure of a block of memory, such as changing all bits of the metablock to ‘0’ in an erasure operation (i.e., of the entire block as evidenced by Klein), as taught by Kim, which results in a metablock of all 0’s that once set to a ‘1’, cannot be overwritten unless the entire metablock block is erased by the controller (wherein the controller is configured such that the first indication is unset only with initializing the whole data structure to a known state when the physical block is erased) as taught by Kim as evidenced by Klein; and furthermore to have modified the controller’s working memory as taught by Jung to be smaller than the entire mapping table so that it can only store portions at a time, which must then be flushed back to non-volatile memory as taught by Kim.
One of ordinary skill in the art would have been motivated to make this modification because one of ordinary skill in the art would appreciate that it would allow the bitmap to accurately reflect the portions of the mapping data related to the data stored in the block, and creating and updating the bitmap in the meta area using a single level cell programming method while storing user data in a user data area in a two level cell method, which allows for increased reliability of the data stored in the meta area and increased density of the data stored in the user area as taught by Kim in [Col 7: lines 18-26] [Col 8: lines 33-40]. Additionally, during garbage collection, since the bitmap is created and updated in the meta area, the controller can read the bitmap from a meta area rather than scanning a spare area of the source block, and performance of the non-volatile memory is improved as taught by Kim in [Col 5: lines 38-50]. Furthermore, because volatile memory is expensive, by only storing portions of the mapping table at a time, less of the expensive volatile memory is needed as taught by Royer in [0002-0003] [0016].
Regarding claim 2 and analogous claim 16:
The memory device of claim 1 is made obvious by Jung in view of Kim as evidenced by Klein as motivated by Royer (Jung-Kim-Klein-Royer).
Jung further discloses, wherein the controller is configured to update the data structure in response to a write to the physical block, wherein the update to the data structure comprises setting a second indication in the data structure corresponding to a second region of the logical-to-physical table (by teaching that in response to a write to a block, the bit that corresponds to the mapping table will be set to a logic ‘1’, this may occur for any of the eight bits, depending on which mapping table is associated with the logical-to-physical address mapping of the written data [0078-0083]).
Regarding claim 3:
The memory device of claim 2 is made obvious by Jung-Kim-Klein-Royer.
Jung further discloses, wherein the first region and the second region are the same region (by teaching that in response to a write to a block, the bit that corresponds to the mapping table will be set to a logic ‘1’, this may occur for any of the eight bits, depending on which mapping table is associated with the logical-to-physical address mapping of the written data [0078-0083] (such that the update may be for a bit corresponding to the same region as another region with a corresponding bit set to a ‘0’ in a previous erase operation as taught by Kim as previously applied).
Regarding claim 4:
The memory device of claim 2 is made obvious by Jung-Kim-Klein-Royer.
Jung further discloses, wherein the first region and the second region are the same region (by teaching that in response to a write to a block, the bit that corresponds to the mapping table will be set to a logic ‘1’, this may occur for any of the eight bits, depending on which mapping table is associated with the logical-to-physical address mapping of the written data [0078-0083] (such that the update may be for a bit corresponding to a different region than another region with a corresponding bit set to a ‘0’ in a previous erase operation as taught by Kim as previously applied).
Regarding claim 6:
The memory device of claim 1 is made obvious by Jung-Kim-Klein-Royer.
Jung does not explicitly disclose, but Kim teaches, wherein creating the data structure comprises setting the first indication to a zero (by teaching that the bitmap may be updated in response to an erase operation [Col 2: lines 32-40]. Furthermore, from the context of the specification and drawings, it is understood that updating the bitmap after an erase operation would involve updating the bitmap to include all 0’s because in this case, no pages of the block would be associated with any mapping tables as none of the pages yet store data after the block is erased [Col 12: lines 34-67]. For example, as seen in [Fig. 13], when the first memory block is a free block (erased block), the sub-bitmap does not contain any 1’s, but instead contains all 0’s [Col 15: lines 4-50]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the use of the bitmap for indicating which mapping table portions are associated with pages programmed into a block as taught by Jung to include creating and updating the bitmaps in the meta region in a single level cell method, while storing user data in a two-level cell method in a user data area, and updating the bitmap in response to the erasure of a block of memory, such as changing all bits of the metablock to ‘0’ in an erasure operation (i.e., of the entire block as evidenced by Klein), as taught by Kim, which results in a metablock of all 0’s that once set to a ‘1’, cannot be overwritten unless the entire metablock block is erased (restricted from changing the first indication from the set value) as evidenced by Klein.
One of ordinary skill in the art would have been motivated to make this modification because one of ordinary skill in the art would appreciate that it would allow the bitmap to accurately reflect the portions of the mapping data related to the data stored in the block, and creating and updating the bitmap in the meta area using a single level cell programming method while storing user data in a user data area in a two level cell method, which allows for increased reliability of the data stored in the meta area and increased density of the data stored in the user area as taught by Kim in [Col 7: lines 18-26] [Col 8: lines 33-40]. Additionally, during garbage collection, since the bitmap is created and updated in the meta area, the controller can read the bitmap from a meta area rather than scanning a spare area of the source block, and performance of the non-volatile memory is improved as taught by Kim in [Col 5: lines 38-50].
Regarding claim 11:
The memory device of claim 1 is made obvious by Jung-Kim-Klein-Royer.
Jung further discloses, wherein the first indication comprises a single bit in the data structure (by teaching the BITMAPK, where each bit (a single bit) corresponds to a portion of the mapping table [0078-0083]).
Regarding claim 12:
The memory device of claim 1 is made obvious by Jung-Kim-Klein-Royer.
Jung further discloses, wherein indications in the data structure are indexed by regions of the logical-to-physical table (by teaching that the index of the bitmap corresponds to the index of the portions of the mapping table [0084]).
Regarding claim 13:
The memory device of claim 1 is made obvious by Jung-Kim-Klein-Royer.
Jung further discloses, wherein the physical block is a NAND flash block (by teaching that NVM includes a memory cell array of pages and blocks of flash memory that may be accessed by a NAND Flash Interface [Fig. 1] [Fig. 2] [0028]).
Claims 21-22 are rejected under 35 U.S.C. 103 as being unpatentable over Jung-Kim-Klein-Royer in further view of US Patent Application Publication No. US 2017/0192903 A1 (Kawamura).
Regarding claims 21 and analogous claim 22:
The memory device of claim 1 is made obvious by Jung-Kim-Klein-Royer.
Jung further discloses, wherein the data structure is no longer updated after the physical block is fully written until initializing the data structure (by teaching that the data structure is only updated when the block is written (S122) (S132) [Fig. 7] [Fig. 11] [0081] [0101], and once the block is fully written the bitmap may be stored in the last page of the block (S123) (S133) [Fig. 7] [Fig. 9] [Fig. 11] [0185] [0101], at which point there are no other disclosures of it being updated until it erased [0056] [0101]).
Jung does not explicitly disclose, but Kawamura teaches, wherein the data structure is restricted from changing after the physical block is fully written until initializing the data structure (by teaching that a the flash memory, data cannot be overwritten on a physical page and data of an entire physical block must be erased first before writing again to each of the previously written pages in the block. In this way, the writing process may occur on pages and may occur once on each page until the block is then erased in a block unit across all pages of the entire block, as erase operations cannot be performed on each page individually [0002-0003] [0075] [0079]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the bitmap written to the last page of the block once the block is fully written to include being unable to be overwritten or reprogrammed (i.e., restricting from changing) unless and until the block is erased as taught by Kawamura.
One of ordinary skill in the art would have been motivated to make this modification because it would have only required the combination of known elements according to known methods to yield predictable results. For example, Jung teaches the memory is flash memory and that it is written in page units and erased in block units but does not explicitly disclose that pages cannot be overwritten unless first erased in an erasure of the entire block. However, Kawamura teaches that this erase before writing procedure and not overwriting previously written pages, but only writing pages that have been erased in an erasure of all pages of the block is a conventional operating method of flash memory. Accordingly, one of ordinary skill in the art could have combined the writing procedures and restrictions on overwriting taught by Kawamura with the flash memory storing the bitmap in the last page taught by Jung according to known methods and the combination would have yielded predictable results (i.e., that the bitmap written to a fully written block could not be erased unless the entire block was erased as taught by Kawamura). Accordingly, the combination would have been obvious to one of ordinary skill in the art.
Response to Arguments/Amendments
In response to the amendments to the claims, the previous claim objections have been withdrawn. However, in response to the amendments to the claims, new claim objections have been made as seen in the corresponding objection section above.
In response to the amendments to the claims, the previous 35 USC §112(b) and 35 USC §112(a) rejections have been withdrawn. However, a new 35 USC §112(b) rejection has been made to claims 18-22, as seen in the corresponding rejection section above.
In response to the amendments to the claims, the 35 USC §103 rejection has been updated to reflect the amended limitations as seen in the corresponding rejection section above. Furthermore, Applicant’s arguments have been fully considered, but are not persuasive. Accordingly, the claims are not indicated as allowable.
Applicant argues that “the amended claims require the controller to be specifically configured such that the first indication is unset only with the initializing, which is a deliberate design choice… not merely a consequence of the underlying storage medium”. However, the Examiner respectfully disagrees.
The claims do not require the controller itself to impose the restriction (and claim 14 does not even link the restriction to the operation of the controller at all). Rather, it is sufficient that the controller is configured to operate within a system in which the restriction exists. A controller may be configured to operate in accordance with constrains imposed by the underlying storage medium, even when the controller does not independently enforce those constrains. Therefore, the fact that the first indication is unset only during initialization as a consequence of the storage medium’s characteristics does not mean that the controller is not configured such that the first indication is unset only during initialization.
The prior art teaches the controller as claimed. Jung teaches a controller that performs and controls read, write and erase operations on the storage device. See [0037] [0056] and [0081-0084] of Jung where the controller sets or maintains bits of the bitmap to a value of ‘1’ as a result of program operations to pages, but otherwise does not erase the bits of the bitmap to ‘0’ outside of an erase operation to the entire block. Klein further teaches that bits cannot be set to ‘0’ without an erase operation to the entire block [0026 of Klein]. Similarly, Kim teaches that read and write operations are performed on a page unit, while erase operations are performed on a block unit, and the bitmap may be updated as a result of an erasure to the block storing the data corresponding to the bitmap [Col 1: lines 42-55 of Kim] [Kim, Col 2: line 30-40] [Kim, Col 6: lines 28-37].
Therefore, the combined teachings establish that the controller is configured to perform read, write and erase operations, and that bits are reset from ‘1’ to ‘0’ only when a block erase operation is performed. Because the controller does not reset bits from ‘1’ to ‘0’ during program or read operations, and because resetting bits from ‘1’ to ‘0’ only occurs through the erase/initialization process, the controller operates such that the first indication is unset only with the initializing.
Applicant’s arguments improperly imports an additional requirement that the controller must have been deliberately designed to achieve the claimed result or must independently enforce the claimed behavior. However, no such requirement appears in the claim language. The claims recite that the controller is configured such that the first indication is unset only with the initializing; they do not require that the controller itself be the source of that restriction. Because the cited references teach a controller that operates within a system in which the first indication is unset only through erase/initialization process, the claimed limitation is met. Accordingly, Applicant’s argument is not persuasive.
The remainder of Applicant’s arguments relies on the premise that the cited references do not teach a controller configured such that the fist indication is unset only with the initializing. However, for the reasons discussed above, the Examiner finds that the references do teach this limitation. Accordingly, Applicant’s arguments regarding the prior art not teaching the additional amended limitations in combination with a controller configured such that the first indication is unset only with the initializing are not persuasive.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US Patent Application Publication No. US 2018/0024920 A1 (Thomas) – discloses a block address entropy counter that is used to improve the efficiency of garbage collection by tracking the number of L2P table segments that are referenced by a block that would need to be used during garbage collection.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/CURTIS JAMES KORTMAN/Examiner, Art Unit 2139
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