DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 30 December 2025 and 29 January 2026 has been entered.
Claim Objections
Claims 21-22 objected to because of the following informalities:
Claims 21-22 recite “changing from a a fully written state”, which as best understood by the Examiner in light of the specification should be amended to recite, “changing from a [[a]] fully written state”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112(b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-4, 6-14, and 16-22 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 1:
Claim 1 recites a data structure comprising a first indication “wherein a set value of the first indication indicates the data structure is restricted to changing the first indication from the set value only with initializing the whole data structure to a known state when the physical block is erased” and further recites that “after the physical block is written the first indication of the data structure does not change from the set value until the physical block is erased”. These limitations purport to impose restrictions on when and how the first indication may be changed. However, the claim does not recite any structural element that enforces or carries out these restrictions. “[T]he use of functional language in a claim may fail "to provide a clear-cut indication of the scope of the subject matter embraced by the claim" and thus be indefinite. In re Swinehart, 439 F.2d 210, 213 (CCPA 1971). For example, when claims merely recite a description of a problem to be solved or a function or result achieved by the invention, the boundaries of the claim scope may be unclear. Halliburton Energy Servs., Inc. v. M-I LLC, 514 F.3d 1244, 1255, 85 USPQ2d 1654, 1663 (Fed. Cir. 2008)” [MPEP 2173.05(g) ¶6]. While functional language is not per se improper, here the claimed function is not tied to any structure capable of performing or enforcing it.
A data structure, by itself, is not understood to be capable of preventing modification of its own values or ensuring that a value remains unchanged over time. Rather, such a behavior would require an enforcing mechanism, such as the memory controller. Although the claim recites a controller configured to erase a block and to create the data structure, the controller is not recited as being configured to enforce the claimed restrictions on modification of the first indication, and there are no phrases linking what the controller is “configured to” preform to these functions. Instead, the claim recites temporal and conditional behavior of the first indication (“after the physical block is written… until the physical block is erased”), but does not recite any structure that would enforce this behavior. Accordingly, the limitations describing that the first indication “is restricted to changing” or “does not change” are not tied to any claimed structure or configuration capable of performing or enforcing those functions. As recited, these limitations merely describe a result of the data structure being used in a particular way, by unclaimed structures/actors, rather than a structural or functional limitation of the claimed device. Accordingly, the use of functional language in the claim has failed to provide a clear-cut indication of the scope of the subject matter embraced by the claim and the claim is indefinite.
Furthermore, the claim does not actually recite that the data structure ever has a ‘set value’. Instead, the claim merely describes what a hypothetical ‘set value’ would indicate if it were present. Because the existence of the set value is not required by the claim, the recited restrictions on what the set value means may never come into effect, rendering their scope indeterminate. It is therefore unclear what limiting effect this limitation has on any claimed structure. Accordingly, the use of functional language in the claim has failed to provide a clear-cut indication of the scope of the subject matter embraced by the claim and the claim is indefinite.
Because the claim fails to specify if or how the recited restrictions are implemented or enforced by the claimed structures, the scope of the claim cannot be determined and the claim is indefinite. For the purposes of applying prior art, the Examiner will interpret the aforementioned limitations as being enforced/enacted by the controller.
Regarding analogous claims 14 and 18:
Claims 14 and 18 are rejected under reasoning analogous to that performed for claim 1 for reciting analogous limitations to those identified for claim 1 in the claim rejection section for claim 1 above.
Regarding claims 2-4, 6-13, 15-17 and 19-22:
Claims 2-4, 6-13, 15-17 and 19-22 are rejected for failing to cure the deficiencies of a rejected base claim from which they depend.
Claim Rejections – 35 USC § 112(a)
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-4, 6-14, and 16-22 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claim 1:
Claim 1 recites, “a set value of the first indication indicates that the data structure is restricted to changing the first indication from the set value only with initializing the whole data structure to a known state when the physical block is erased” (emphasis added). The claim language “indicates” requires that the “restriction to changing” be discernible from, or conveyed by, the set value itself, rather than merely enforced by the controller or some other logic. However, the specification does not disclose such a requirement.
Nowhere in the specification does a set value in the data structure “indicate that the data structure is restricted to changing the first indication from the set value only with initializing”. Instead, the specification is replete with descriptions of a set value indicating that a corresponding L2P region has at one time mapped a logical page to a physical page of the block, but not that it “indicates” a restriction on changing the first indication from the set value [0026-0027] [0037] [0040-0042] [0050-0053] [0059-0062].
The restriction on the bit being unset is disclosed as a system constraint and not something that the “set value” itself conveys. For example, [0042] says that “the indication is unset only with the initializing”, but this describes how the system behaves. The specification does not provide any suggestion that the set value of ‘1’ conveys this restriction to anything else, that the set value encodes a lock condition, or that reading the bit and finding a “set value” tells a structure in the system that it cannot be unset except by initialization. Instead, the description “the indication is unset only with the initialization” describes a constraint on how the system operates (no selective unsetting) and not what the set value means. In this way, the restriction exists independently of the bit’s value, the system simply does not allow selective unsetting or unsetting at all except during initialization, and the bit does not “indicate” that restriction, but is merely subject to it. In effect, Applicant is trying to claim an undisclosed representational meaning of the “set value” where the specification merely described an operational constraint on the system and the limitation is regarded as new matter.
Regarding analogous claims 14 and 18:
Claims 14 and 18 are rejected under reasoning analogous to that performed for claim 1 for reciting analogous limitations to those identified for claim 1 in the claim rejection section for claim 1 above.
Regarding claims 21-22:
Claims 21-22 each recite, “wherein the data structure is restricted from changing from a fully written state until initializing the data structure”. However, the specification never discloses such as restriction on the data structure that is based on the data structure being fully written, nor does the specification ever disclose a “fully written” data structure. Instead, the restriction from changing the data structure is based on the fully written state of the block to which the data structure corresponds (“after the block is fully written—that is, there are no more free pages—the bitmap for the block is not changed until the block is erased” [0027], also see [0042]), and not on a fully written state of the data structure. Accordingly, the limitation is regarded as new matter.
Regarding claims 2-4, 6-13, 15-17 and 19-22:
Claims 2-4, 6-13, 15-17 and 19-22 are rejected for failing to cure the deficiencies of a rejected base claim from which they depend.
Claim Rejections – 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 6-14 and 16-22 are rejected under 35 U.S.C. 103 as being unpatentable over US Patent Application Publication No. US 2017/0075600 A1 (Jung) in view of US Patent No. US 9,529,705 B2 (Kim) as evidenced by US Patent Application Publication No. US 2015/0143197 A1 (Klein).
Regarding claim 1 and analogous claims 14 and 18:
Jung teaches, a memory device (storage device (300) implemented as a flash based memory device [0034] [Fig. 1]) comprising: memory elements (NVM (400) contains a plurality of blocks (410), which contain a plurality of pages (memory elements) of flash memory [0040] [0050] [Fig. 1]) and a controller (controller (310), including CPU that executes firmware (i.e., instructions stored in a non-transitory memory) for controlling the functions of the controller [0037] [Fig. 1]) configured to: erase a physical block of the memory elements (by teaching that the controller controls the erase operations of the physical blocks [0037], where the erase operation is performed on a block by block basis [0051])) and create a data structure, wherein the data structure comprises a first indication that indicates whether the physical block is referenced in a first region of a logical-to-physical table, wherein creating the data structure comprises changing the first indication to initialize the data structure based on the erasure to unset the first indication (by teaching that the BITMAPK includes 8 bits (8 indications including a first indication) which correspond to eight mapping tables (8 regions of a mapping table including a first region). The bits are each used to index to one of the respective mapping tables. A logical ‘1’ indicates that the block contains a page included in the respective mapping table, whereas a logical ‘0’ (unset, with regard to claim 20) indicates that the block does not contain a page corresponding to the respective mapping table [0078-0084]. The BITMAP data structure may be created before writing to the block (S121) (S131) [Fig. 7] [Fig. 11]. From the entire disclosure, one of ordinary skill in the art would understand that when a block is newly written, all bits of the BITMAPK would initially be set to ‘0’ because the block containing the BITMAPK is erased (S121) (S131) [Fig. 7] [Fig. 9] [Fig. 10] [Fig. 11]. Furthermore, because the block is erased, no more pages of the block correspond to any of the respective mapping tables, and so for the BITMAPK to reflect this, it would include all ‘0’s [0078-0084] Each of the bits may be updated whenever data is written to at least one of the pages included in the data block that corresponds to a region of the mapping table indicated by the respective bit that was not previously referenced in the block (S122) (S132) [0081] [0083] [Fig. 7] [Fig. 9] [Fig. 10] [Fig. 11].).
Jung does not explicitly teach, but Kim as evidenced by Klein teaches to create the data structure in response to erasure of the physical block of memory; where a set value of the first indication indicates that the data structure is restricted to changing the first indication from the set value only with initializing the whole data structure to a known state when the physical block is erased, and wherein after the physical block is written the first indication of the data structure does not change from the set value until the physical block is erased (by teaching that a sub-bitmap for a block may be updated when the data block is erased (create a data structure – interpreted in line with Applicant’s specification which appears to indicate that creating a data structure involves initializing it to all 0’s [Applicant’s Specification, 0061]) [Kim, Col 2: line 30-40] [Kim, Col 6: lines 28-37]. The sub-bitmap may be stored in a meta area of a solid-state drive. The sub-bitmap functions in an analogous fashion to the BITMAPK of Jung, as a logic high for a bit indicates a page in the block which corresponds to a particular sub mapping table, and a logic low indicates there are no pages in the block which correspond to the particular sub mapping table, where the bits index to the corresponding sub mapping tables [Col 6: line 38 – Col 7: line 10, Kim]. The non-volatile memory device can program data in the meta area (122) with a single level cell method in order to improve the reliability of the data stored in the meta area, so that it is stored with a higher reliability than data stored in the user area (121) [Col 7: lines 18-26, Kim]. Furthermore, Klein teaches that a basic property of flash memory (as used in both Jung and Kim) is that a 0-bit can be changed to a 1-bit (setting the data structure), but not vice-versa (the data structure is restricted to changing the first indication from the set value) [Abstract, Klein]. In this way, writing a 0-bit or a 1-bit to flash memory are not symmetrical operations [0026, Klein]. If a block contains only 0s (initializing the whole data structure to a known state because it was freshly erased (with initializing the whole data structure)), individual bits can be changed to a 1, however, once a bit is set to 1, it can be changed back to a value of 0 only by erasing the entire block (bits can be set to 0 (i.e., changed from the set value) only with initializing the data structure based on the erasure) (create a data structure in response to erasure of the physical block) [0026]. In this way, in order to update the BITMAP data structure (which has 1’s set due to previous writes to the block) in the metablock in response to the erasure as taught by Jung, the BITMAP would have to be erased with the block (create a data structure in response to the erasure). Then, if bits of the BITMAP are set again, they could not be unset until the metablock was again erased as evidenced through the mechanics of flash memory as taught by Klein.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the use of the bitmap for indicating which mapping table portions are associated with pages programmed into a block as taught by Jung to include creating and updating the bitmaps in the meta region in a single level cell method, while storing user data in a two-level cell method in a user data area, and updating the bitmap in response to the erasure of a block of memory, such as changing all bits of the metablock to ‘0’ in an erasure operation (i.e., of the entire block as evidenced by Klein), as taught by Kim, which results in a metablock of all 0’s that once set to a ‘1’, cannot be overwritten unless the entire metablock block is erased (restricted from changing the first indication from the set value) as evidenced by Klein.
One of ordinary skill in the art would have been motivated to make this modification because one of ordinary skill in the art would appreciate that it would allow the bitmap to accurately reflect the portions of the mapping data related to the data stored in the block, and creating and updating the bitmap in the meta area using a single level cell programming method while storing user data in a user data area in a two level cell method, which allows for increased reliability of the data stored in the meta area and increased density of the data stored in the user area as taught by Kim in [Col 7: lines 18-26] [Col 8: lines 33-40]. Additionally, during garbage collection, since the bitmap is created and updated in the meta area, the controller can read the bitmap from a meta area rather than scanning a spare area of the source block, and performance of the non-volatile memory is improved as taught by Kim in [Col 5: lines 38-50].
Regarding claim 2 and analogous claim 16:
The memory device of claim 1 is made obvious by Jung in view of Kim as evidenced by Klein (Jung-Kim-Klein).
Jung further discloses, wherein the controller is configured to update the data structure in response to a write to the physical block, wherein the update to the data structure comprises setting a second indication in the data structure corresponding to a second region of the logical-to-physical table (by teaching that in response to a write to a block, the bit that corresponds to the mapping table will be set to a logic ‘1’, this may occur for any of the eight bits, depending on which mapping table is associated with the logical-to-physical address mapping of the written data [0078-0083]).
Regarding claim 3:
The memory device of claim 2 is made obvious by Jung-Kim-Klein.
Jung further discloses, wherein the first region and the second region are the same region (by teaching that in response to a write to a block, the bit that corresponds to the mapping table will be set to a logic ‘1’, this may occur for any of the eight bits, depending on which mapping table is associated with the logical-to-physical address mapping of the written data [0078-0083] (such that the update may be for a bit corresponding to the same region as another region with a corresponding bit set to a ‘0’ in a previous erase operation as taught by Kim as previously applied).
Regarding claim 4:
The memory device of claim 2 is made obvious by Jung-Kim-Klein.
Jung further discloses, wherein the first region and the second region are the same region (by teaching that in response to a write to a block, the bit that corresponds to the mapping table will be set to a logic ‘1’, this may occur for any of the eight bits, depending on which mapping table is associated with the logical-to-physical address mapping of the written data [0078-0083] (such that the update may be for a bit corresponding to a different region than another region with a corresponding bit set to a ‘0’ in a previous erase operation as taught by Kim as previously applied).
Regarding claim 6:
The memory device of claim 1 is made obvious by Jung-Kim-Klein.
Jung does not explicitly disclose, but Kim teaches, wherein creating the data structure comprises setting the first indication to a zero (by teaching that the bitmap may be updated in response to an erase operation [Col 2: lines 32-40]. Furthermore, from the context of the specification and drawings, it is understood that updating the bitmap after an erase operation would involve updating the bitmap to include all 0’s because in this case, no pages of the block would be associated with any mapping tables as none of the pages yet store data after the block is erased [Col 12: lines 34-67]. For example, as seen in [Fig. 13], when the first memory block is a free block (erased block), the sub-bitmap does not contain any 1’s, but instead contains all 0’s [Col 15: lines 4-50]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the use of the bitmap for indicating which mapping table portions are associated with pages programmed into a block as taught by Jung to include creating and updating the bitmaps in the meta region in a single level cell method, while storing user data in a two-level cell method in a user data area, and updating the bitmap in response to the erasure of a block of memory, such as changing all bits of the metablock to ‘0’ in an erasure operation (i.e., of the entire block as evidenced by Klein), as taught by Kim, which results in a metablock of all 0’s that once set to a ‘1’, cannot be overwritten unless the entire metablock block is erased (restricted from changing the first indication from the set value) as evidenced by Klein.
One of ordinary skill in the art would have been motivated to make this modification because one of ordinary skill in the art would appreciate that it would allow the bitmap to accurately reflect the portions of the mapping data related to the data stored in the block, and creating and updating the bitmap in the meta area using a single level cell programming method while storing user data in a user data area in a two level cell method, which allows for increased reliability of the data stored in the meta area and increased density of the data stored in the user area as taught by Kim in [Col 7: lines 18-26] [Col 8: lines 33-40]. Additionally, during garbage collection, since the bitmap is created and updated in the meta area, the controller can read the bitmap from a meta area rather than scanning a spare area of the source block, and performance of the non-volatile memory is improved as taught by Kim in [Col 5: lines 38-50].
Regarding claim 7:
The memory device of claim 1 is made obvious by Jung-Kim-Klein.
Jung further discloses, comprising a working memory, wherein the controller is configured to: read the data structure during a garbage collection of the physical block; and load only a portion of the logical-to-physical table into the working memory (by teaching the internal memory (350) (working memory) [Fig. 1]. Furthermore, the mapping table managed by the FTL is divided into eight tables and each table stores data for 100 logical address mappings [0043]. The mapping table is stored in the meta area [0048]. In this way, the controller may read and analyze the bitmap in order to determine the portions of the mapping table needed to perform garbage collection on the block, acquire these needed mapping tables (load only a portion of the logical to physical table into working memory that correspond to the mapping tables have an entry in the data structure that is set (i.e. according to the bitmap)), and determine the validity of the pages in the block based on scanning through the acquired mapping tables for the physical addresses of the block [0093-0106] [Fig. 7]).
Regarding claim 8:
The memory device of claim 7 is made obvious by Jung-Kim-Klein.
Jung does not explicitly disclose, but Kim teaches, wherein the logical-to-physical table is larger than the working memory for the memory device (by teaching that conventionally, a non-volatile memory system has limited resources in the controller such that all the sub-mapping tables cannot be loaded at a time, such as in the SRAM as discussed [Col 10: lines 18-22]. Accordingly, only a portion may be loaded at a time and the others must be flushed back to non-volatile memory [Col 13: lines 55-67].
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the controller’s working memory as taught by Jung to be smaller than the entire mapping table so that it can only store portions at a time, which must then be flushed back to non-volatile memory as taught by Kim.
One of ordinary skill in the art would have been motivated to make this modification because volatile memory is expensive, and by only storing portions of the mapping table at a time, less of the expensive volatile memory is needed as taught by Royer in [0002-0003] [0016].
Regarding claim 9:
The memory device of claim 7 is made obvious by Jung-Kim-Klein.
Jung further discloses, wherein the portion of the logical-to-physical table comprises only those regions of the logical-to-physical table regions that have an asserted value in their respective indications in the data structure (by teaching that the mapping table managed by the FTL is divided into eight tables and each table stores data for 100 logical address mappings [0043]. The mapping table is stored in the meta area [0048]. In this way, the controller may read and analyze the bitmap in order to determine the portions of the mapping table needed to perform garbage collection on the block, acquire these needed mapping tables (load only a portion of the logical to physical table into working memory that correspond to the mapping tables have an entry in the data structure that is set (i.e. regions that have an asserted value in the respective indications in the data structure)), and determine the validity of the pages in the block based on scanning through the acquired mapping tables for the physical addresses of the block [0093-0106] [Fig. 7]).
Regarding claim 10 and analogous claims 17 and 19-20:
The memory device of claim 9 is made obvious by Jung-Kim-Klein.
Jung further discloses, wherein the controller is configured to retrieve only the portion of the logical-to-physical table to perform the garbage collection (by teaching that the mapping table managed by the FTL is divided into eight tables and each table stores data for 100 logical address mappings [0043]. The mapping table is stored in the meta area [0048]. In this way, the controller may read and analyze the bitmap in order to determine the portions of the mapping table needed to perform garbage collection on the block, acquire these needed mapping tables (retrieve only the portion of the logical to physical table to perform garbage collection), and determine the validity of the pages in the block based on scanning through the acquired mapping tables for the physical addresses of the block [0093-0106] [Fig. 7]).
Regarding claim 11:
The memory device of claim 1 is made obvious by Jung-Kim-Klein.
Jung further discloses, wherein the first indication comprises a single bit in the data structure (by teaching the BITMAPK, where each bit (a single bit) corresponds to a portion of the mapping table [0078-0083]).
Regarding claim 12:
The memory device of claim 1 is made obvious by Jung-Kim-Klein.
Jung further discloses, wherein indications in the data structure are indexed by regions of the logical-to-physical table (by teaching that the index of the bitmap corresponds to the index of the portions of the mapping table [0084]).
Regarding claim 13:
The memory device of claim 1 is made obvious by Jung-Kim-Klein.
Jung further discloses, wherein the physical block is a NAND flash block (by teaching that NVM includes a memory cell array of pages and blocks of flash memory that may be accessed by a NAND Flash Interface [Fig. 1] [Fig. 2] [0028]).
Regarding claims 21 and analogous claim 22:
The memory device of claim 1 is made obvious by Jung-Kim-Klein.
Jung does not explicitly disclose, but Kim as evidenced by Klein teaches, wherein the data structure is restricted from changing from a a fully written state until initializing the data structure (by teaching that a sub-bitmap for a block may be updated when the data block is erased [Applicant’s Specification, 0061] [Kim, Col 2: line 30-40] [Kim, Col 6: lines 28-37]. The sub-bitmap may be stored in a meta area of a solid-state drive. The sub-bitmap functions in an analogous fashion to the BITMAPK of Jung, as a logic high for a bit indicates a page in the block which corresponds to a particular sub mapping table, and a logic low indicates there are no pages in the block which correspond to the particular sub mapping table, where the bits index to the corresponding sub mapping tables [Col 6: line 38 – Col 7: line 10, Kim]. The non-volatile memory device can program data in the meta area (122) with a single level cell method in order to improve the reliability of the data stored in the meta area, so that it is stored with a higher reliability than data stored in the user area (121) [Col 7: lines 18-26, Kim]. Furthermore, Klein teaches that a basic property of flash memory (as used in both Jung and Kim) is that a 0-bit can be changed to a 1-bit, but not vice-versa (the data structure is restricted to changing the first indication from the set value) [Abstract, Klein]. If a block contains only 0s, individual bits can be changed to a 1, however, once a bit is set to 1 (or all bits are set to 1), it can be changed back to a value of 0 only by erasing the entire block [0026]. In this way, if the BITMAP were written with all 1’s (fully written), it could not be changed unless it was erased (restricted from changing from a fully written state until initializing the data structure).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the use of the bitmap for indicating which mapping table portions are associated with pages programmed into a block as taught by Jung to include creating and updating the bitmaps in the meta region in a single level cell method, while storing user data in a two-level cell method in a user data area, and updating the bitmap in response to the erasure of a block of memory, such as changing all bits of the metablock to ‘0’ in an erasure operation (i.e., of the entire block as evidenced by Klein), as taught by Kim, which results in a metablock of all 0’s that once set to a ‘1’, cannot be overwritten unless the entire metablock block is erased (restricted from changing from a fully written state until initializing the data structure) as evidenced by Klein.
One of ordinary skill in the art would have been motivated to make this modification because one of ordinary skill in the art would appreciate that it would allow the bitmap to accurately reflect the portions of the mapping data related to the data stored in the block, and creating and updating the bitmap in the meta area using a single level cell programming method while storing user data in a user data area in a two level cell method, which allows for increased reliability of the data stored in the meta area and increased density of the data stored in the user area as taught by Kim in [Col 7: lines 18-26] [Col 8: lines 33-40]. Additionally, during garbage collection, since the bitmap is created and updated in the meta area, the controller can read the bitmap from a meta area rather than scanning a spare area of the source block, and performance of the non-volatile memory is improved as taught by Kim in [Col 5: lines 38-50].
Response to Arguments/Amendments
In response to Applicant clearly linking the new claim terminology to the disclosures in the specification on pg. 2, ¶1-3 in the Remarks filed 30 December 2025, the objection to the specification has been withdrawn.
In response to the amendments to the claims, the previous 35 USC §112(b) rejections have been withdrawn. However, a new 35 USC §112(b) rejection has been made, as seen in the corresponding rejection section above.
In response to the amendments to the claims, a 35 USC §112(a) rejection has been made as seen in the corresponding rejection section above.
In response to the amendments to the claims, a 35 USC §103 rejection has been made as seen in the corresponding rejection section above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US Patent Application Publication No. US 2018/0024920 A1 (Thomas) – discloses a block address entropy counter that is used to improve the efficiency of garbage collection by tracking the number of L2P table segments that are referenced by a block that would need to be used during garbage collection.
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