DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 2 and 6-12 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Claim 2 recites “wherein the first scan transistor and the second scan transistor receive a first scan signal and a second scan signal respectively, wherein the first scan transistor and the second scan transistor are turned-on at different times according to the first scan signal and the second scan signal” which is indefinite, because it is written as a method step of actually receiving signals and turning on transistors instead of as a structural limitation of the transistors, causing it to be unclear whether, and to what extent, said method step serves to further limit the claimed invention. Claim 12 is likewise rejected for the recitation of “wherein the tunable component is controlled by a control signal corresponding to the data voltage”.
Claim 6 recites “wherein the pre-charge voltage is equal to or less than a maximum voltage of the data voltage, and the pre-charge voltage is equal to or larger than a minimum voltage of the data voltage” which is indefinite, because the pre-charge voltage is transient rather than physical or permanent, and is additionally outside the scope of the claim, i.e., something that only exists during operation of the electronic device. It is unclear whether, and to what extent, a limitation of an element outside the scope of the claim serves to further limit the claim from which it depends. Claims 7-8 and 10 are likewise rejected. Dependent claims 9 and 11 fail to cure the deficiency.
Claim Rejections - 35 USC § 102
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Serb et al. (US 2021/0004669 A1), hereinafter Serb.
Regarding claim 1, Serb discloses an electronic device (abstract, regarding a tunable CMOS circuit), comprising:
a plurality of electronic units (texel 35; fig. 3; see para. [0052] regarding a texel array), wherein each of the plurality of electronic units comprises:
a pixel circuit (stage 2 of the texel 35, as shown in fig. 3); and
a tunable component (memristor R1; fig. 3; para. [0041], regarding the memristors are one example of a tunable load), coupled to the pixel circuit (as shown in fig. 3),
wherein the pixel circuit comprises:
a storage capacitor (capacitor C2; fig. 3);
a first scan transistor (transistor M3; fig. 3), coupled to the storage capacitor (as shown in fig. 3); and
a second scan transistor (transistor M4; fig. 3), coupled to the storage capacitor (as shown in fig. 3).
Regarding claim 2, Serb discloses the invention in claim 1, and further discloses wherein the first scan transistor (M3) and the second scan transistor (M4) receive a first scan signal and a second scan signal respectively (para. [0054], regarding connecting the transistors to the drain terminals of M3 and M4 may allow independent tuning of the FWHM of the current output, thus controlling the selectivity of the texel 35), wherein the first scan transistor and the second scan transistor are turned-on at different times according to the first scan signal and the second scan signal (Examiner notes that the mere intent to turn the first and second scan transistors on at different times according to first and second scan signals does not structurally distinguish the invention from the prior art, see MPEP §2114(II); see also related rejection under §112(b) detailed hereinabove).
Regarding claim 3, Serb discloses the invention in claim 1, and further discloses wherein the second scan transistor (M4) is configured to transfer a data voltage to the storage capacitor (as shown in fig. 3, inherent by virtue of their mutual electrical connection and capabilities).
Regarding claim 4, Serb discloses the invention in claim 3, and further discloses wherein the second scan transistor (M4) is coupled to a data line to receive the data voltage (as shown in fig. 3).
Regarding claim 5, Serb discloses the invention in claim 3, and further discloses wherein the first scan transistor (M3) is configured to transfer a pre-charge voltage to the storage capacitor (as shown in fig. 3, inherent by virtue of their mutual electrical connection and capabilities).
Regarding claim 6, Serb discloses the invention in claim 5, and further discloses wherein the pre-charge voltage is equal to or less than a maximum voltage of the data voltage, and the pre-charge voltage is equal to or larger than a minimum voltage of the data voltage (Examiner notes that the mere intent to use a pre-charge voltage of any particular size does not structurally distinguish the invention from the prior art, see MPEP §2114(II); see related rejection under §112(b) detailed hereinabove).
Regarding claim 7, Serb discloses the invention in claim 6, and further discloses wherein the pre-charge voltage is a fixed voltage (Examiner notes that the mere intent to use a pre-charge voltage of any particular size does not structurally distinguish the invention from the prior art, see MPEP §2114(II); see related rejection under §112(b) detailed hereinabove).
Regarding claim 8, Serb discloses the invention in claim 7, and further discloses wherein the pre-charge voltage is within a first preset range corresponding to a center of a voltage range of the data voltage (Examiner notes that the mere intent to use a pre-charge voltage of any particular size does not structurally distinguish the invention from the prior art, see MPEP §2114(II); see related rejection under §112(b) detailed hereinabove).
Regarding claim 9, Serb discloses the invention in claim 6, and further discloses wherein the first scan transistor (M3) receives the pre-charge voltage from a common voltage line shared with the plurality of electronic units on a same row and/or a same column (as shown in figs. 1 and 3; Examiner notes that the mere intent to have the first scan transistor (M3) receive the pre-charge voltage from a common voltage line shared with the plurality of electronic units on a same row and/or a same column does not structurally distinguish the invention from the prior art, see MPEP §2114(II); see related rejection under §112(b) detailed hereinabove).
Regarding claim 10, Serb discloses the invention in claim 6, and further discloses wherein the pre-charge voltage is within a second preset range corresponding to a center of a voltage range of a first voltage, wherein the first voltage is a current data voltage plus a previous data voltage divided by 2 (Examiner notes that the mere intent to use a pre-charge voltage of any particular size does not structurally distinguish the invention from the prior art, see MPEP §2114(II); see related rejection under §112(b) detailed hereinabove).
Regarding claim 11, Serb discloses the invention in claim 6, and further discloses wherein the first scan transistor and the second scan transistor are coupled to a data line (as shown in figs. 1 and 3).
Regarding claim 12, Serb discloses the invention in claim 3, and further discloses wherein the tunable component (R1) is controlled by a control signal corresponding to the data voltage (Examiner notes that the mere intent to control the tunable component by a control signal corresponding to the data voltage does not structurally distinguish the invention from the prior art, see MPEP §2114(II); see related rejection under §112(b) detailed hereinabove).
Regarding claim 13, Serb discloses the invention in claim 12, and further discloses wherein the tunable component is a voltage-controlled component (Examiner notes that the mere intent to control the tunable component by voltage does not structurally distinguish the invention from the prior art, see MPEP §2114(II)).
Regarding claim 14, Serb discloses the invention in claim 12, and further discloses wherein the tunable component is a capacitance tunable component (Examiner notes that the mere intent to control the tunable component by capacitance does not structurally distinguish the invention from the prior art, see MPEP §2114(II)).
Regarding claim 15, Serb discloses the invention in claim 3, and further discloses wherein the pixel circuit further comprises: a driving circuit (formed by transistors M5 and M6), coupled to the tunable component (as shown in fig. 3).
Regarding claim 16, Serb discloses the invention in claim 15, and further discloses wherein the driving circuit is a voltage driver (para. [0042], regarding the current draw of the second CMOS stage M3/M4 is maximised when the voltage at node ‘MID’ Vmid is such that both M3 and M4 are simultaneously maximally open; this will occur at a predetermined fixed voltage value Vpk; the voltage value Vpk is determined by the sizing of M3 and M4; to a weaker degree, the voltage value Vpk may also be dependent on the sizing of M5; fig. 3).
Regarding claim 17, Serb discloses the invention in claim 1, and further discloses wherein the electronic device is an active matrix device (as shown in fig. 6).
Regarding claim 18, Serb discloses the invention in claim 17, and further discloses wherein the electronic device is an antenna device (as attached to the antenna module 40 as shown in fig. 1).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
a) Determining the scope and contents of the prior art.
b) Ascertaining the differences between the prior art and the claims at issue.
c) Resolving the level of ordinary skill in the pertinent art.
d) Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Serb et al. (US 2021/0004669 A1), hereinafter Serb.
Regarding claims 19 and 20, Serb discloses the invention in claim 18, but does not appear to specifically disclose wherein the antenna device is a liquid crystal antenna (claim 19); or wherein the antenna device is a varactor antenna (claim 20).
However, it would have been obvious to one having ordinary skill in the art at the time the invention was made to configure the invention such that the antenna device is a liquid crystal antenna or a varactor antenna, since the equivalence of generic antennas and liquid crystal/varactor for their use in the antenna art and the selection of any known equivalents to liquid crystal/varactor antennas would be within the level of ordinary skill in the art. Examiner notes that liquid crystal/varactor antennas are well-known and conventionally used antenna alternatives, and Applicant offers no criticality for one type of antenna over another (see para. [0020]).
Conclusion
The cited references made of record in the contemporaneously filed PTO-892 form and not relied upon in the instant office action are considered pertinent to applicant's disclosure, and may have one or more of the elements in Applicant’s disclosure and at least claim 1.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRADY W FRAZIER whose telephone number is (469)295-9263. The examiner can normally be reached Monday-Friday 9:00am-5:00pm CT.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Kelleher can be reached at 571-272-7753. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BRADY W FRAZIER/ Primary Examiner, Art Unit 3648
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