Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicants’ election without traverse of Species 1 in the reply filed on July 13th, 2025, is acknowledged.
Priority
The instant application claim of the priority date of 09/13/2023 of the foreign application JAPAN 2023-148695 is noted and entered. Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statements (IDS) were submitted on 3/5/2024 and 3/21/2025. This submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Claim Objections
Claim 4 is objected to because of the following informalities:
In claim 4, “The first insulating film” should have a lowercase t and read “the first insulating film”.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 9 and 13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ishimaru et al, US 20210305431 A1 (Ishimaru).
Regarding claim 9; Ishimaru teaches a semiconductor device (Fig. 1: transistor 100) comprising:
an oxide semiconductor (Fig. 1: Channel region 18; Para. 92: "The channel region 18 is an oxide semiconductor.") including a first end and a second end (See Ishimaru annotated Fig. 1 shared in this OA),
the oxide semiconductor extending in a first direction (A: Fig. 1: Third Direction) oriented from the second end to the first end (See Ishimaru annotated Fig. 1 shared in this OA);
a first electrode (Fig. 1: drain electrode 12) arranged to contact (indirectly physically "contacting") the first end of the oxide semiconductor;
a second electrode (source electrode 10) configured to contact (indirectly physically "contacting") the second end of the oxide semiconductor;
a first insulating film (Fig. 1: gate insulating layer 22) arranged to enclose at least a part of the oxide semiconductor in the first direction side (Fig. 2: gate insulating layer 22 enclosing channel region 18);
a gate electrode (Fig. 1: gate electrode 20) arranged to enclose the oxide semiconductor with the first insulating film interposed therebetween between the first and second ends of the oxide semiconductor (Fig. 2: gate electrode 20 enclosing gate insulating layer 22 that is around channel region 18);
a third insulating film (Fig. 1: second interlayer insulating layer 28) arranged to contact (indirectly physically "contacting") a part of a side surface of the first insulating film including an end portion in the first direction side (Fig. 1: second interlayer insulating layer 28 indirectly contacting gate insulating layer 22);
and a fourth insulating film (Fig. 1: second protective insulating layer 32) arranged to contact the third insulating film in a direction side opposite to the first direction,
wherein a material of the third insulating film (Para. 108: "The second interlayer insulating layer 28 is an oxide, a nitride, or an oxynitride") is different from a material of the fourth insulating film (A: Para. 112: "The second protective insulating layer 32 is an oxide, a nitride, or an oxynitride, for example. The second protective insulating layer 32 is formed of a material different from that forming the second interlayer insulating layer 28, for example").
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Regarding claim 13; Ishimaru teaches a semiconductor device (Fig. 1: transistor 100) comprising:
an oxide semiconductor (Fig. 1: Channel region 18; Para. 92: "The channel region 18 is an oxide semiconductor.") including a first end and a second end (See Ishimaru annotated Fig. 1 shared in this OA),
the oxide semiconductor extending in a first direction (Fig. 1: Third Direction) oriented from the second end to the first end (See Ishimaru annotated Fig. 1 shared in this OA);
a first electrode (Fig. 1: drain electrode 12) arranged to contact (indirectly physically "contacting") the first end of the oxide semiconductor;
a second electrode (source electrode 10) arranged to contact (indirectly physically "contacting") the second end of the oxide semiconductor;
a first insulating film (Fig. 1: gate insulating layer 22) arranged to enclose at least a part of the oxide semiconductor in the first direction side (Fig. 2: gate insulating layer 22 enclosing channel region 18);
and a gate electrode (Fig. 1: gate electrode 20) arranged to enclose the oxide semiconductor with the first insulating film interposed therebetween between the first and second ends of the oxide semiconductor (Fig. 2: gate electrode 20 enclosing gate insulating layer 22 that is around channel region 18),
wherein the second electrode is distant from an end portion of the first insulating film in a direction side opposite to the first direction (Fig. 1: first protective insulating layer 30 and first interlayer insulating layer 26 are between source electrode 10 and gate insulating layer 22).
Allowable Subject Matter
Claims 1-8 and 14-16 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
The primary reason for the allowable subject matter of claims 1-8 and 14-16 is the inclusion of the limitation “a second metal film including a first cylindrical portion in contact with the first metal film in the first direction side” and “the second metal film encloses the second oxide semiconductor with the second insulating film interposed therebetween” in combination with the other limitations in the claim. For example, prior art of record teaches a second metal film but fails to teach, or be reasonably combined, to render obvious the claimed combination of limitations “second metal film” with “in the first direction side” in combination with all other limitations of claim 1. Additionally, prior art of record fails to teach, or be reasonably combined, to render obvious the claimed combination of limitations “the second metal film” with “encloses the second oxide semiconductor” in combination with all other limitations of claim 1.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Sawabe (US 20190296155 A1) discloses a semiconductor device with a second metal film but fails to teach a second metal film in contact with a first metal film in the first direction or the second metal film enclosing a second oxide semiconductor.
Makala (US 20140225181 A1) discloses a semiconductor device with a second metal film but fails to disclose the second metal film enclosing the second oxide semiconductor.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AUBRIE I HETHERINGTON whose telephone number is (571)270-0666. The examiner can normally be reached M-Th 7:30-5, Fr 7:30-4.
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/AUBRIE IRENE HETHERINGTON/Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817
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