DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set
forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this
application is eligible for continued examination under 37 CFR 1.114, and the fee set
forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action
has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on
10/20/2025 has been entered.
Response to Amendment
The office action is responding to the arguments filed on 03/09/2026. Claims 1-18 and 20-21 are pending.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-2,6-7,13-14, 18 and 20-21 are rejected under 35 U.S.C. 103 as being unpatentable over Duan et al. (US 20210279010 A1) in view of Yang et al. (US 10971215 B1) hereinafter Duan and Yang.
Regarding claim 1, Duan teaches An apparatus, comprising: one or more memory devices comprising one or more memory cells, the one or more memory cells comprising a first type of memory cells having a first storage density different than a second type of memory cells having a second storage density; (“Each of memory cells 210 can be programmed individually or collectively to one or a number of programmed states. For example, a single-level cell (SLC) can represent one of two programmed states (e.g., 1 or 0), representing one bit of data. However, flash memory cells can also represent one of more than two programmed states, allowing the manufacture of higher density memories without increasing the number of memory cells, as each cell can represent more than one binary digit (e.g., more than one bit)”) (paragraph [0030] line 1-5) (i.e. Fig 2 illustrates memory cells 210 can be programmed to one or a number of programmed states and can be combination of single bit density SLC or multiple bit density MLC, TLC)
and a controller coupled with the one or more memory devices using a channel and configured to cause the apparatus to: (“The memory control unit 318 includes a communication interface 315, processor 330 (CPU), static random access memory (SRAM) 332, and a flash controller 334”) (paragraph [0034] line 1-2)
(“The flash controller 334 communicates with the memory array 301 via bus 336 (e.g., a NAND flash bus using a double data rate, or DDR, interface). The flash controller 334 sends flash commands, sends write data, and receives read data using the bus”) (paragraph [0035] line 1-2) (i.e. Fig 3 illustrates flash controller 334 communicates with the memory array 301 via bus 336 and sends flash commands and write data using bus 336)
transfer information between at least one of the one or more memory devices and the controller over the channel using the adjusted clock rate associated with the clock signal; and (“once the memory (e.g., type of flash) and the communication interface 315 (e.g., type of protocol) are decided for a storage device, the time for the memory read access (4) and the time for a transfer via the communication interface (t.sub.D) are set”) (paragraph [0046] line 5-7)
(“The memory control unit may include a controller, such as flash controller 334 in FIG. 3, that communicates with the memory array via the bus”) (paragraph [0047] line 4-5) (i.e. Once the flash type is decided, for a particular flash type t.sub.A can be adjusted by changing the speed of the processor and time t.sub.C can be adjusted by changing the speed of one or both of the ECC decoder and the memory bus for writing data where communication between controller and memory happens using memory bus)
perform, concurrently with transferring the information, a write operation to write the data to the one or more memory cells based at last in part on adjusting the clock rate associated with the channel. (“Once the memory and the communication interface are decided upon for a storage device the time for the communication interface transfer (t.sub.B) and the time for the memory programming (t.sub.D) are set and the processor or the firmware can't dynamically change time t.sub.B car t.sub.D. However, time t.sub.A can be adjusted by changing the speed of the processor, and time t.sub.C can be adjusted by changing the speed of one or both of the ECC decoder and the memory bus”) (paragraph [0055] line 1-5) (i.e. Fig 5 illustrates commands (1-4) and command steps (A-D) are executed concurrently where communication interface transfer (B) and adjusted speed (C) memory program or write can happen concurrently for two commands. In other words, adjusted program data transfer time and communication or transferring information can happen concurrently)
Duan teaches data transfer methods in memory system. However, Duan does not explicitly teach wherein the first storage density is greater than the second storage density
determine to write data to the one or more memory cells comprising the first type of memory cells; adjust a clock rate of a clock signal associated with the channel based at least in part on determining to write the data to the one or more memory cells comprising the first type of memory cells
such that the clock rate is associated with the first storage density of the first type of memory cells
and a second type of memory cells, the first type of memory cells
On the other hand, Yang which also relates to data transfer methods in memory system teaches wherein the first storage density is greater than the second storage density (see Fig 6, col 8, illustrates memory die 202 having SLC and 404 and MLC 406 memory blocks where MLC block having higher density than SLC block)
determine to write data to the one or more memory cells comprising the first type of memory cells; adjust a clock rate of a clock signal associated with the channel based at least in part on determining to write the data to the one or more memory cells comprising the first type of memory cells (see Fig 6 and 7, col 21, illustrates storage controller 120 is configured to service storage operations for SLC storage block 404 and MLC storage block 406 using different data transfer speed for SLC block and MLC block. In other words, storage controller determines what data transfer speed need to be used for different density blocks and make adjustment accordingly)
such that the clock rate is associated with the first storage density of the first type of memory cells (see Fig 3 and 4, col 15 line 1-3, 24-26, illustrates MLC data transfer speed or clock rate is configured specifically for MLC cells storage and SLC data transfer speed or clock rate is configured specifically for SLC cells storage)
and a second type of memory cells, the first type of memory cells (see Fig 4, col 13 line 52-55, illustrates non-volatile memory 118 may include SLC type storage blocks 404 and MLC type storage blocks 406)
Both Duan and Yang relate to different data transfer methods in memory system.
Duan teaches different data transfer methods in memory system. On the other hand, Yang also teaches different data transfer methods in memory system and different memory type where data transfer methods are adjusted based on memory type and also MLC data transfer speed or clock rate is configured specifically for MLC cells storage and SLC data transfer speed or clock rate is configured specifically for SLC cells storage where non-volatile memory may include SLC type storage blocks and MLC type storage blocks. Therefore, it would have been obvious to one of ordinary skill at the time the invention was effectively filed to combine Duan with Yang to specify different data transfer methods in memory system and different memory type where data transfer methods are adjusted based on memory type also MLC data transfer speed or clock rate is configured specifically for MLC cells storage and SLC data transfer speed or clock rate is configured specifically for SLC cells storage where non-volatile memory may include SLC type storage blocks and MLC type storage blocks providing a system configured to dynamically adjust data transfer speed for a non-volatile memory die for better performance as mentioned in col 2.
Regarding claim 2, Duan in view of Yang teaches data transfer methods in memory system in claim 1. However, Duan - Yang combination does not explicitly teach The apparatus of claim 1, wherein the controller is further configured to cause the apparatus to: receive a command to write the data to the one or more memory cells, wherein to output the clock signal is based at least in part on receiving the command
On the other hand, Duan which also relates to data transfer methods in memory
System teaches The apparatus of claim 1, wherein the controller is further configured to cause the apparatus to: receive a command to write the data to the one or more memory cells, wherein to output the clock signal is based at least in part on receiving the command. (“when the memory access requests are to sequential addresses, the memory control unit may reduce the frequency of the clock signal of the processor while maintaining the frequency of the clock signal of the flash controller. Similarly, when the memory access requests are to random addresses, the memory control unit may reduce the frequency of the clock signal of the flash controller and maintain the frequency of the clock signal of the processor”) (paragraph [0064] line 2-6) (i.e. when the memory access requests are to sequential addresses the memory control unit may reduce the frequency of the clock signal of the processor while maintaining the frequency of the clock signal of the flash controller and when the memory access requests are to random addresses the memory control unit may reduce the frequency of the clock signal of the flash controller and maintain the frequency of the clock signal of the processor. In other words, controller can configure output clock signal based on type of memory request commands)
The same motivation that was utilized for combining Duan with Yang as set forth in claim 1 is equally applicable to claim 2.
Regarding claim 6, Duan in view of Yang teaches data transfer methods in memory system in claim 1. However, Duan - Yang combination does not explicitly teach The apparatus of claim 1, wherein the controller is further configured to cause the apparatus to: receive the clock signal, wherein to transfer the information is based at least in part on receiving the clock signal
On the other hand, Duan which also relates to data transfer methods in memory
System teaches The apparatus of claim 1, wherein the controller is further configured to cause the apparatus to: receive the clock signal, wherein to transfer the information is based at least in part on receiving the clock signal. (“The memory control unit may reduce the transfer rate of the bus by reducing a frequency of the clock signal of the flash controller when the queued memory access requests are to random addresses of the memory array”) (paragraph [0063] line 5-7) (i.e. the flash controller receives clock signal and memory access requests and based on that memory control unit may reduce transfer rate of the bus by reducing clock signal frequency)
The same motivation that was utilized for combining Duan with Yang as set forth in claim 1 is equally applicable to claim 6.
Regarding claim 7, Duan in view of Yang teaches data transfer methods in memory system in claim 1. However, Duan - Yang combination does not explicitly teach The apparatus of claim 1, wherein the controller is further configured to cause the apparatus to: generate the clock signal in accordance with the adjusted clock rate associated with the clock signal; and
output the clock signal using the adjusted clock rate, wherein to transfer the information is based at least in part on outputting the clock signal
On the other hand, Duan which also relates to data transfer methods in memory
System teaches The apparatus of claim 1, wherein the controller is further configured to cause the apparatus to: generate the clock signal in accordance with the adjusted clock rate associated with the clock signal; and
output the clock signal using the adjusted clock rate, wherein to transfer the information is based at least in part on outputting the clock signal. (“The flash controller configured to transfer data between the memory control unit and memory array. The memory control unit is configured to reduce a frequency of a clock signal of the processor when the queued memory access requests are to sequential addresses of the memory array, and reduce a frequency of a clock signal of the flash controller when the queued memory access requests are to random addresses of the memory array”) (paragraph [0105] line 2-5) (i.e. flash controller is configured to transfer data between the memory control unit and memory array when the queued memory access requests along with control signals are received where memory control unit adjust frequency of clock signal)
The same motivation that was utilized for combining Duan with Yang as set forth in claim 1 is equally applicable to claim 7.
Regarding claim 13, Duan teaches A non-transitory computer-readable medium storing code comprising instructions which, when executed by a processor of an electronic device, cause the electronic device to: (“The processor 330 may execute instructions contained in firmware to perform functions such as, among other things, handle read/write commands, manage the flash memory and initiate data transfers”) (paragraph [0035] line 1-2) (i.e. Fig 3 illustrates The processor 330 may execute instructions contained in firmware to perform functions such as handle read/write commands, manage the flash memory and initiate data transfers)
determine to write data to one or more memory cells of a memory device, (“The memory control unit 318 includes a communication interface 315, processor 330 (CPU), static random access memory (SRAM) 332, and a flash controller 334”) (paragraph [0034] line 1-2)
(“The flash controller 334 communicates with the memory array 301 via bus 336 (e.g., a NAND flash bus using a double data rate, or DDR, interface). The flash controller 334 sends flash commands, sends write data, and receives read data using the bus”) (paragraph [0035] line 1-2) (i.e. Fig 3 illustrates flash controller 334 communicates with the memory array 301 via bus 336 and sends flash commands and write data using bus 336)
the one or more memory cells comprising a first type of memory cells having a first storage density different than a second type of memory cells having a second storage density; (“Each of memory cells 210 can be programmed individually or collectively to one or a number of programmed states. For example, a single-level cell (SLC) can represent one of two programmed states (e.g., 1 or 0), representing one bit of data. However, flash memory cells can also represent one of more than two programmed states, allowing the manufacture of higher density memories without increasing the number of memory cells, as each cell can represent more than one binary digit (e.g., more than one bit)”) (paragraph [0030] line 1-5) (i.e. Fig 2 illustrates memory cells 210 can be programmed to one or a number of programmed states and can be combination of single bit density SLC or multiple bit density MLC, TLC)
transfer information between the memory device and a controller over the channel using the adjusted clock rate associated with the clock signal; and (“once the memory (e.g., type of flash) and the communication interface 315 (e.g., type of protocol) are decided for a storage device, the time for the memory read access (4) and the time for a transfer via the communication interface (t.sub.D) are set”) (paragraph [0046] line 5-7)
(“The memory control unit may include a controller, such as flash controller 334 in FIG. 3, that communicates with the memory array via the bus”) (paragraph [0047] line 4-5) (i.e. Once the flash type is decided, for a particular flash type t.sub.A can be adjusted by changing the speed of the processor and time t.sub.C can be adjusted by changing the speed of one or both of the ECC decoder and the memory bus for writing data where communication between controller and memory happens using memory bus)
perform, concurrently with transferring the information, a write operation to write the data to the one or more memory cells based at last in part on adjusting the clock rate associated with the channel. (“Once the memory and the communication interface are decided upon for a storage device the time for the communication interface transfer (t.sub.B) and the time for the memory programming (t.sub.D) are set and the processor or the firmware can't dynamically change time t.sub.B car t.sub.D. However, time t.sub.A can be adjusted by changing the speed of the processor, and time t.sub.C can be adjusted by changing the speed of one or both of the ECC decoder and the memory bus”) (paragraph [0055] line 1-5) (i.e. Fig 5 illustrates commands (1-4) and command steps (A-D) are executed concurrently where communication interface transfer (B) and adjusted speed (C) memory program or write can happen concurrently for two commands. In other words, adjusted program data transfer time and communication or transferring information can happen concurrently)
Duan teaches data transfer methods in memory system. However, Duan does not explicitly teach wherein the first storage density is greater than the second storage density
determine to write data to the one or more memory cells comprising the first type of memory cells; adjust a clock rate of a clock signal associated with the channel based at least in part on determining to write the data to the one or more memory cells comprising the first type of memory cells
such that the clock rate is associated with the first storage density of the first type of memory cells
and a second type of memory cells, the first type of memory cells
On the other hand, Yang which also relates to data transfer methods in memory system teaches wherein the first storage density is greater than the second storage density (see Fig 6, col 8, illustrates memory die 202 having SLC and 404 and MLC 406 memory blocks where MLC block having higher density than SLC block)
determine to write data to the one or more memory cells comprising the first type of memory cells; adjust a clock rate of a clock signal associated with the channel based at least in part on determining to write the data to the one or more memory cells comprising the first type of memory cells (see Fig 6 and 7, col 21, illustrates storage controller 120 is configured to service storage operations for SLC storage block 404 and MLC storage block 406 using different data transfer speed for SLC block and MLC block. In other words, storage controller determines what data transfer speed need to be used for different density blocks and make adjustment accordingly)
such that the clock rate is associated with the first storage density of the first type of memory cells (see Fig 3 and 4, col 15 line 1-3, 24-26, illustrates MLC data transfer speed or clock rate is configured specifically for MLC cells storage and SLC data transfer speed or clock rate is configured specifically for SLC cells storage)
and a second type of memory cells, the first type of memory cells (see Fig 4, col 13 line 52-55, illustrates non-volatile memory 118 may include SLC type storage blocks 404 and MLC type storage blocks 406)
Both Duan and Yang relate to different data transfer methods in memory system.
Duan teaches different data transfer methods in memory system. On the other hand, Yang also teaches different data transfer methods in memory system and different memory type where data transfer methods are adjusted based on memory type and also MLC data transfer speed or clock rate is configured specifically for MLC cells storage and SLC data transfer speed or clock rate is configured specifically for SLC cells storage where non-volatile memory may include SLC type storage blocks and MLC type storage blocks. Therefore, it would have been obvious to one of ordinary skill at the time the invention was effectively filed to combine Duan with Yang to specify different data transfer methods in memory system and different memory type where data transfer methods are adjusted based on memory type also MLC data transfer speed or clock rate is configured specifically for MLC cells storage and SLC data transfer speed or clock rate is configured specifically for SLC cells storage where non-volatile memory may include SLC type storage blocks and MLC type storage blocks providing a system configured to dynamically adjust data transfer speed for a non-volatile memory die for better performance as mentioned in col 2.
Regarding claim 14, Duan in view of Yang teaches data transfer methods in memory system in claim 13. However, Duan - Yang combination does not explicitly teach The non-transitory computer-readable medium of claim 13, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: receive a command to write the data to the one or more memory cells, wherein to output the clock signal is based at least in part on receiving the command
On the other hand, Duan which also relates to data transfer methods in memory
System teaches The non-transitory computer-readable medium of claim 13, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: receive a command to write the data to the one or more memory cells, wherein to output the clock signal is based at least in part on receiving the command. (“when the memory access requests are to sequential addresses, the memory control unit may reduce the frequency of the clock signal of the processor while maintaining the frequency of the clock signal of the flash controller. Similarly, when the memory access requests are to random addresses, the memory control unit may reduce the frequency of the clock signal of the flash controller and maintain the frequency of the clock signal of the processor”) (paragraph [0064] line 2-6) (i.e. when the memory access requests are to sequential addresses the memory control unit may reduce the frequency of the clock signal of the processor while maintaining the frequency of the clock signal of the flash controller and when the memory access requests are to random addresses the memory control unit may reduce the frequency of the clock signal of the flash controller and maintain the frequency of the clock signal of the processor. In other words, controller can configure output clock signal based on type of memory request commands)
The same motivation that was utilized for combining Duan with Yang as set forth in claim 13 is equally applicable to claim 14.
Regarding claim 18, Duan in view of Yang teaches data transfer methods in memory system in claim 13. However, Duan - Yang combination does not explicitly teach The non-transitory computer-readable medium of claim 13, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: receive the clock signal, wherein to transfer the information is based at last in part on receiving the clock signal
On the other hand, Duan which also relates to data transfer methods in memory
System teaches The non-transitory computer-readable medium of claim 13, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: receive the clock signal, wherein to transfer the information is based at last in part on receiving the clock signal. (“The memory control unit may reduce the transfer rate of the bus by reducing a frequency of the clock signal of the flash controller when the queued memory access requests are to random addresses of the memory array”) (paragraph [0063] line 5-7) (i.e. the flash controller receives clock signal and memory access requests and based on that memory control unit may reduce transfer rate of the bus by reducing clock signal frequency)
The same motivation that was utilized for combining Duan with Yang as set forth in claim 13 is equally applicable to claim 18.
Regarding claim 20, Duan teaches A method for operating a memory system, comprising: determining to write data to one or more memory cells of a memory device, the one or more memory cells comprising a first type of memory cells having a first storage density different than a second type of memory cells having a second storage density; (“FIG. 7 is a flow diagram of a method 700 of operating a memory device, such as the memory device 200 of FIG. 2”) (paragraph [0059] line 1) (i.e. Fig 7 is a flow diagram of a method 700 of operating a memory device of the memory device 200)
(“Each of memory cells 210 can be programmed individually or collectively to one or a number of programmed states. For example, a single-level cell (SLC) can represent one of two programmed states (e.g., 1 or 0), representing one bit of data. However, flash memory cells can also represent one of more than two programmed states, allowing the manufacture of higher density memories without increasing the number of memory cells, as each cell can represent more than one binary digit (e.g., more than one bit)”) (paragraph [0030] line 1-5) (i.e. Fig 2 illustrates memory cells 210 can be programmed to one or a number of programmed states and can be combination of single bit density SLC or multiple bit density MLC, TLC)
transferring information between the memory device and a controller over the channel using the adjusted clock rate associated with the clock signal; and (“once the memory (e.g., type of flash) and the communication interface 315 (e.g., type of protocol) are decided for a storage device, the time for the memory read access (4) and the time for a transfer via the communication interface (t.sub.D) are set”) (paragraph [0046] line 5-7)
(“The memory control unit may include a controller, such as flash controller 334 in FIG. 3, that communicates with the memory array via the bus”) (paragraph [0047] line 4-5) (i.e. Once the flash type is decided, for a particular flash type t.sub.A can be adjusted by changing the speed of the processor and time t.sub.C can be adjusted by changing the speed of one or both of the ECC decoder and the memory bus for writing data where communication between controller and memory happens using memory bus) performing, concurrently with transferring the information, a write operation to write the data to the one or more memory cells based at last in part on adjusting the clock rate associated with the channel. (“Once the memory and the communication interface are decided upon for a storage device the time for the communication interface transfer (t.sub.B) and the time for the memory programming (t.sub.D) are set and the processor or the firmware can't dynamically change time t.sub.B car t.sub.D. However, time t.sub.A can be adjusted by changing the speed of the processor, and time t.sub.C can be adjusted by changing the speed of one or both of the ECC decoder and the memory bus”) (paragraph [0055] line 1-5) (i.e. Fig 5 illustrates commands (1-4) and command steps (A-D) are executed concurrently where communication interface transfer (B) and adjusted speed (C) memory program or write can happen concurrently for two commands. In other words, adjusted program data transfer time and communication or transferring information can happen concurrently)
Duan teaches data transfer methods in memory system. However, Duan does not explicitly teach wherein the first storage density is greater than the second storage density
determine to write data to the one or more memory cells comprising the first type of memory cells; adjust a clock rate of a clock signal associated with the channel based at least in part on determining to write the data to the one or more memory cells comprising the first type of memory cells
such that the clock rate is associated with the first storage density of the first type of memory cells
and a second type of memory cells, the first type of memory cells
On the other hand, Yang which also relates to data transfer methods in memory system teaches wherein the first storage density is greater than the second storage density (see Fig 6, col 8, illustrates memory die 202 having SLC and 404 and MLC 406 memory blocks where MLC block having higher density than SLC block)
determine to write data to the one or more memory cells comprising the first type of memory cells; adjust a clock rate of a clock signal associated with the channel based at least in part on determining to write the data to the one or more memory cells comprising the first type of memory cells (see Fig 6 and 7, col 21, illustrates storage controller 120 is configured to service storage operations for SLC storage block 404 and MLC storage block 406 using different data transfer speed for SLC block and MLC block. In other words, storage controller determines what data transfer speed need to be used for different density blocks and make adjustment accordingly)
such that the clock rate is associated with the first storage density of the first type of memory cells (see Fig 3 and 4, col 15 line 1-3, 24-26, illustrates MLC data transfer speed or clock rate is configured specifically for MLC cells storage and SLC data transfer speed or clock rate is configured specifically for SLC cells storage)
and a second type of memory cells, the first type of memory cells (see Fig 4, col 13 line 52-55, illustrates non-volatile memory 118 may include SLC type storage blocks 404 and MLC type storage blocks 406)
Both Duan and Yang relate to different data transfer methods in memory system.
Duan teaches different data transfer methods in memory system. On the other hand, Yang also teaches different data transfer methods in memory system and different memory type where data transfer methods are adjusted based on memory type and also MLC data transfer speed or clock rate is configured specifically for MLC cells storage and SLC data transfer speed or clock rate is configured specifically for SLC cells storage where non-volatile memory may include SLC type storage blocks and MLC type storage blocks. Therefore, it would have been obvious to one of ordinary skill at the time the invention was effectively filed to combine Duan with Yang to specify different data transfer methods in memory system and different memory type where data transfer methods are adjusted based on memory type also MLC data transfer speed or clock rate is configured specifically for MLC cells storage and SLC data transfer speed or clock rate is configured specifically for SLC cells storage where non-volatile memory may include SLC type storage blocks and MLC type storage blocks providing a system configured to dynamically adjust data transfer speed for a non-volatile memory die for better performance as mentioned in col 2.
Claim(s) 3 and 15 are rejected under 35 U.S.C. 103 as being unpatentable
over Duan et al. (US 20210279010 A1) in view of Yang et al. (US 10971215 B1) and further in view of Banerjee et al. (US 20170364140 A1) hereinafter Duan and Yang and Banerjee.
Regarding claim 3, Duan in view of Yang teaches data transfer methods in memory system in claim 1. However, Duan - Yang combination does not explicitly teach The apparatus of claim 1, wherein the controller is further configured to cause the apparatus to: terminate a write boost mode based at least in part on determining to write the data to the one or more memory cells comprising the first type of memory cells, wherein to transfer the information is based at least in part on terminating the write boost mode.
On the other hand, Banerjee which also relates to managing power consumption
with transferring data in memory system teaches The apparatus of claim 1, wherein the controller is further configured to cause the apparatus to: terminate a write boost mode based at least in part on determining to write the data to the one or more memory cells comprising the first type of memory cells, wherein to transfer the information is based at least in part on terminating the write boost mode. (“Moving upward from the block 710, if the workload performance is met, then at block 712 the power mode manager 114 can wait for the software 404 to disable the boosted power state. If the scheduler 704 writes a boost-power-state disable indication into the power mode memory 608, the power mode manager 114 drops back to the highest independent power mode at block 714”) (paragraph [0073] line 5-8) (i.e. Fig 7 illustrates at block 710 if the workload performance is met then at block 712 the power mode manager 114 (Fig1 ) can wait for the software 404 (Fig 4) to disable the boosted power state and also if the scheduler 704 writes a boost-power-state disable indication into the power mode memory 608 the power mode manager 114 drops back to the highest independent power mode at block 714. In other words, when workload performance is met power mode manager disables the boosted power state of memory)
It would have been obvious to one of ordinary skill in the art at the time of
Applicant’s filing to combine Duan with Yang for the reasons set forth in claim 1 above. In addition, Duan, Yang and Banerjee are considered analogous arts, because they all relate to data transfer methods in memory system. Duan – Yang combination teaches data transfer methods in memory system with adjusting data transfer based on memory type. On the other hand, Banerjee also teaches data transfer methods in memory system and when workload performance is met power mode manager disables the boosted power state of memory. Therefore, it would have been obvious to one of ordinary skill at the time the invention was effectively filed to combine Duan – Yang combination with Banerjee to specify data transfer methods in memory system and when workload performance is met power mode manager disables the boosted power state of memory providing workload management for performance and power consumption by the electronic device as mentioned in paragraph [0005].
Regarding claim 15, Duan in view of Yang teaches data transfer methods in memory system in claim 13. However, Duan - Yang combination does not explicitly teach The non-transitory computer-readable medium of claim 13, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to:
terminate a write boost mode based at least in part on determining to write the data to the one or more memory cells comprising the first type of memory cells, wherein to transfer the information is based at least in part on terminating the write boost mode.
On the other hand, Banerjee which also relates to managing power consumption
with transferring data in memory system teaches The non-transitory computer-readable medium of claim 13, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to:
terminate a write boost mode based at least in part on determining to write the data to the one or more memory cells comprising the first type of memory cells, wherein to transfer the information is based at least in part on terminating the write boost mode. (“Moving upward from the block 710, if the workload performance is met, then at block 712 the power mode manager 114 can wait for the software 404 to disable the boosted power state. If the scheduler 704 writes a boost-power-state disable indication into the power mode memory 608, the power mode manager 114 drops back to the highest independent power mode at block 714”) (paragraph [0073] line 5-8) (i.e. Fig 7 illustrates at block 710 if the workload performance is met then at block 712 the power mode manager 114 (Fig1 ) can wait for the software 404 (Fig 4) to disable the boosted power state and also if the scheduler 704 writes a boost-power-state disable indication into the power mode memory 608 the power mode manager 114 drops back to the highest independent power mode at block 714. In other words, when workload performance is met power mode manager disables the boosted power state of memory)
It would have been obvious to one of ordinary skill in the art at the time of
Applicant’s filing to combine Duan with Yang for the reasons set forth in claim 13 above. In addition, Duan, Yang and Banerjee are considered analogous arts, because they all relate to data transfer methods in memory system. Duan – Yang combination teaches data transfer methods in memory system with adjusting data transfer based on memory type. On the other hand, Banerjee also teaches data transfer methods in memory system and when workload performance is met power mode manager disables the boosted power state of memory. Therefore, it would have been obvious to one of ordinary skill at the time the invention was effectively filed to combine Duan – Yang combination with Banerjee to specify data transfer methods in memory system and when workload performance is met power mode manager disables the boosted power state of memory providing workload management for performance and power consumption by the electronic device as mentioned in paragraph [0005].
Claim(s) 4,11 and 16 are rejected under 35 U.S.C. 103 as being unpatentable
over Duan et al. (US 20210279010 A1) in view of Yang et al. (US 10971215 B1) and further in view of Lim et al. (US 20220137848 A1) hereinafter Duan and Yang and Lim.
Regarding claim 4, Duan in view of Yang teaches data transfer methods in memory system in claim 1. However, Duan - Yang combination does not explicitly teach The apparatus of claim 1, wherein the controller is further configured to cause the apparatus to: perform a garbage collection operation comprising writing the data to the one or more memory cells, wherein to transfer the information is based at least in part on the garbage collection operation.
On the other hand, Lim which also relates to managing power consumption
with transferring data in memory system teaches The apparatus of claim 1, wherein the controller is further configured to cause the apparatus to: perform a garbage collection operation comprising writing the data to the one or more memory cells, wherein to transfer the information is based at least in part on the garbage collection operation. (“In response to an operating speed decrease, the storage device 200 according to an example embodiment may request the host device 100 to decrease the multiplication ratios of the clock multiplier 121 of the host device 100 and the clock multiplier 228 or 315 of the storage device 200”) (paragraph [0068] line 1-3)
(“An example of the storage device 200 processing data being low is performing a background operation (e.g., an urgent background operation) such as a migration operation of data from the first area 211 to the second area 212, from the second area 212 to the first area 211, inside the first area 211 or inside the second area, a garbage collection operation”) (paragraph [0068] line 5-8) (i.e. Fig 1 illustrates in response to an operating speed decrease the storage device 200 may request the host device 100 to decrease the multiplication ratios of the clock multiplier 121 of the host device 100 and the clock multiplier 228 of the storage device 200 and storage device 200 processing data being low is performing a background operation such as garbage collection operation in memory device 210. In other words, in response to operating speed decrease storage device may request to decrease clock multiplication to perform garbage collection)
It would have been obvious to one of ordinary skill in the art at the time of
Applicant’s filing to combine Duan with Yang for the reasons set forth in claim 1 above. In addition, Duan, Yang and Lim are considered analogous arts, because they all relate to data transfer methods in memory system. Duan – Yang combination teaches data transfer methods in memory system with adjusting data transfer based on memory type. On the other hand, Lim also data transfer methods in memory system and in response to operating speed decrease storage device may request to decrease clock multiplication to perform garbage collection. Therefore, it would have been obvious to one of ordinary skill at the time the invention was effectively filed to combine Duan – Yang combination with Lim to specify data transfer methods in memory system and in response to operating speed decrease storage device may request to decrease clock multiplication to perform garbage collection providing storage device reduction method of power consumption by adjusting a transmission rate and an operating method of the storage device as mentioned in paragraph [0002].
Regarding claim 11, Duan in view of Yang teaches data transfer methods in memory system in claim 1. However, Duan - Yang combination does not explicitly teach The apparatus of claim 1, wherein: the first type of memory cells comprises one or more triple-level cell (TLC) memory cells, one or more multi-level cell (MLC) memory cells, one or more quad-level cell (QLC) memory cells, or any combination thereof, and the second type of memory cells comprises one or more single-level cell (SLC) memory cells
On the other hand, Lim which also relates to managing power consumption
with transferring data in memory system teaches The apparatus of claim 1, wherein: the first type of memory cells comprises one or more triple-level cell (TLC) memory cells, one or more multi-level cell (MLC) memory cells, one or more quad-level cell (QLC) memory cells, or any combination thereof, and the second type of memory cells comprises one or more single-level cell (SLC) memory cells. (“the controller 220 may use memory cells of the first area 211 as single level cells (SLCs), and may use memory cells of the second area 212 as multi-level cells (MLCs), triple level cells (TLCs), quadruple level cells (QLCs)”) (paragraph [0037] line 3-5) (i.e. Fig 1 illustrates controller 220 may use memory cells of the first area 211 as single level cells (SLCs), and may use memory cells of the second area 212 as multi-level cells (MLCs), triple level cells (TLCs), quadruple level cells (QLCs). In other words, controller may use memory cells of the one area as SLC and another area as MLC, TLC, QLC)
It would have been obvious to one of ordinary skill in the art at the time of
Applicant’s filing to combine Duan with Yang for the reasons set forth in claim 1 above. In addition, Duan, Yang and Lim are considered analogous arts, because they all relate to data transfer methods in memory system. Duan – Yang combination teaches data transfer methods in memory system with adjusting data transfer based on memory type. On the other hand, Lim also teaches data transfer methods in memory system and controller may use memory cells of the one area as SLC and another area as MLC, TLC, QLC. Therefore, it would have been obvious to one of ordinary skill at the time the invention was effectively filed to combine Duan – Yang combination with Lim to specify data transfer methods in memory system and controller may use memory cells of the one area as SLC and another area as MLC, TLC, QLC providing storage device reduction method of power consumption by adjusting a transmission rate and an operating method of the storage device as mentioned in paragraph [0002].
Regarding claim 16, Duan in view of Yang teaches data transfer methods in memory system in claim 13. However, Duan - Yang combination does not explicitly teach The non-transitory computer-readable medium of claim 13, wherein the instructions to perform the write operation are executable by the processor to: perform a garbage collection operation comprising writing the data to the one or more memory cells, wherein to transfer the information is based at least in part on the garbage collection operation.
On the other hand, Lim which also relates to managing power consumption
with transferring data in memory system teaches The non-transitory computer-readable medium of claim 13, wherein the instructions to perform the write operation are executable by the processor to: perform a garbage collection operation comprising writing the data to the one or more memory cells, wherein to transfer the information is based at least in part on the garbage collection operation. (“In response to an operating speed decrease, the storage device 200 according to an example embodiment may request the host device 100 to decrease the multiplication ratios of the clock multiplier 121 of the host device 100 and the clock multiplier 228 or 315 of the storage device 200”) (paragraph [0068] line 1-3)
(“An example of the storage device 200 processing data being low is performing a background operation (e.g., an urgent background operation) such as a migration operation of data from the first area 211 to the second area 212, from the second area 212 to the first area 211, inside the first area 211 or inside the second area, a garbage collection operation”) (paragraph [0068] line 5-8) (i.e. Fig 1 illustrates in response to an operating speed decrease the storage device 200 may request the host device 100 to decrease the multiplication ratios of the clock multiplier 121 of the host device 100 and the clock multiplier 228 of the storage device 200 and storage device 200 processing data being low is performing a background operation such as garbage collection operation in memory device 210. In other words, in response to operating speed decrease storage device may request to decrease clock multiplication to perform garbage collection)
It would have been obvious to one of ordinary skill in the art at the time of
Applicant’s filing to combine Duan with Yang for the reasons set forth in claim 13 above. In addition, Duan, Yang and Lim are considered analogous arts, because they all relate to data transfer methods in memory system. Duan – Yang combination teaches data transfer methods in memory system with adjusting data transfer based on memory type. On the other hand, Lim also teaches data transfer methods in memory system and in response to operating speed decrease storage device may request to decrease clock multiplication to perform garbage collection. Therefore, it would have been obvious to one of ordinary skill at the time the invention was effectively filed to combine Duan – Yang combination with Lim to specify data transfer methods in memory system and in response to operating speed decrease storage device may request to decrease clock multiplication to perform garbage collection providing storage device reduction method of power consumption by adjusting a transmission rate and an operating method of the storage device as mentioned in paragraph [0002].
Claim(s) 5 and 17 are rejected under 35 U.S.C. 103 as being unpatentable
over Duan et al. (US 20210279010 A1) in view of Yang et al. (US 10971215 B1) and further in view of Bahirat et al. (US 20210310874 A1) hereinafter Duan and Yang and Bahirat.
Regarding claim 5, Duan in view of Yang teaches data transfer methods in memory system in claim 1. However, Duan - Yang combination does not explicitly teach The apparatus of claim 1, wherein the clock rate associated with writing the data to the one or more memory cells comprising the first type of memory cells is different than a second clock rate associated with writing the data to the one or more memory cells comprising the second type of memory cells.
On the other hand, Bahirat which also relates to managing power consumption
with transferring data in memory system teaches The apparatus of claim 1, wherein the clock rate associated with writing the data to the one or more memory cells comprising the first type of memory cells is different than a second clock rate associated with writing the data to the one or more memory cells comprising the second type of memory cells. (“The SLC programing mode can have a shorter programing time than the QLC programing mode or the TLC programing mode, which can reduce the power consumption of the memory system.”) (paragraph [0058] line 28-30) (i.e. SLC programing mode can have a shorter programing time than the QLC programing mode or the TLC programing mode which can reduce the power consumption of the memory system. In other words, clock rate for programming to SLC cells can be different than clock rate for programming to TLC memory cells)
It would have been obvious to one of ordinary skill in the art at the time of
Applicant’s filing to combine Duan with Yang for the reasons set forth in claim 1 above. In addition, Duan, Yang and Bahirat are considered analogous arts, because they all relate to data transfer methods in memory system. Duan – Yang combination teaches data transfer methods in memory system with adjusting data transfer based on memory type. On the other hand, Bahirat also teaches data transfer methods in memory system and clock rate for programming to SLC cells can be different than clock rate for programming to TLC memory cells. Therefore, it would have been obvious to one of ordinary skill at the time the invention was effectively filed to combine Duan – Yang combination with Bahirat to specify data transfer methods in memory system and clock rate for programming to SLC cells can be different than clock rate for programming to TLC memory cells providing SSD throttling control algorithms capable of satisfying the requirements associated with multiple workload demands and/or performance modes as mentioned in paragraph [0019].
Regarding claim 17, Duan in view of Yang teaches data transfer methods in memory system in claim 13. However, Duan - Yang combination does not explicitly teach The non-transitory computer-readable medium of claim 13, wherein the clock rate associated with writing the data to the one or more memory cells comprising the first type of memory cells is different than a second clock rate associated with writing the data to the one or more memory cells comprising the second type of memory cells
On the other hand, Bahirat which also relates to managing power consumption
with transferring data in memory system teaches The non-transitory computer-readable medium of claim 13, wherein the clock rate associated with writing the data to the one or more memory cells comprising the first type of memory cells is different than a second clock rate associated with writing the data to the one or more memory cells comprising the second type of memory cells. (“The SLC programing mode can have a shorter programing time than the QLC programing mode or the TLC programing mode, which can reduce the power consumption of the memory system.”) (paragraph [0058] line 28-30) (i.e. SLC programing mode can have a shorter programing time than the QLC programing mode or the TLC programing mode which can reduce the power consumption of the memory system. In other words, clock rate for programming to SLC cells can be different than clock rate for programming to TLC memory cells)
It would have been obvious to one of ordinary skill in the art at the time of
Applicant’s filing to combine Duan with Yang for the reasons set forth in claim 13 above. In addition, Duan, Yang and Bahirat are considered analogous arts, because they all relate to data transfer methods in memory system. Duan – Yang combination teaches data transfer methods in memory system with adjusting data transfer based on memory type. On the other hand, Bahirat also teaches data transfer methods in memory system and clock rate for programming to SLC cells can be different than clock rate for programming to TLC memory cells. Therefore, it would have been obvious to one of ordinary skill at the time the invention was effectively filed to combine Duan – Yang combination with Bahirat to specify data transfer methods in memory system and clock rate for programming to SLC cells can be different than clock rate for programming to TLC memory cells providing SSD throttling control algorithms capable of satisfying the requirements associated with multiple workload demands and/or performance modes as mentioned in paragraph [0019].
Claim(s) 8 and 9 are rejected under 35 U.S.C. 103 as being unpatentable
over Duan et al. (US 20210279010 A1) in view of Yang et al. (US 10971215 B1) and further in view of Shakeri et al. (US 20210110856 A1) hereinafter Duan and Yang and Shakeri.
Regarding claim 8, Duan in view of Yang teaches data transfer methods in memory system in claim 1. However, Duan - Yang combination does not explicitly teach The apparatus of claim 1, wherein the controller is further configured to cause the apparatus to: output, the clock signal in accordance with a first clock rate;
determine to write second data to one or more second memory cells comprising the second type of memory cells; and
output the clock signal using a second clock rate based at least in part on writing the second data to the one or more second memory cells comprising the second type of memory cells.
On the other hand, Shakeri which also relates to managing power consumption
with transferring data in memory system teaches The apparatus of claim 1, wherein the controller is further configured to cause the apparatus to: output, the clock signal in accordance with a first clock rate;
determine to write second data to one or more second memory cells comprising the second type of memory cells; and
output the clock signal using a second clock rate based at least in part on writing the second data to the one or more second memory cells comprising the second type of memory cells. (“The data are received over input/output (I/O) pins [7:0] for an 8-bit device or input/output (I/O) pins [15:0] for a 16-bit device at I/O control circuitry 112 and are written into cache register 118 through sensing devices 106”) (paragraph [0029] line 3-5)
(“First stage 306 may process data in response to the clock signal at a first data rate equal to the clock rate of the clock signal”) (paragraph [0043] line 3-4)
(“second stage 312.sub.1 to 312.sub.N may process data received from first stage 306 at a second data rate equal to or less than the clock rate times the number of second stages 312.sub.1 to 312.sub.N”) (paragraph [0044] line 2-4)
(i.e. Fig 1 illustrates data are received over input/output (I/O) pins [7:0] for an 8-bit device or input/output (I/O) pins [15:0] for a 16-bit device at I/O control circuitry 112 and are written into cache register 118 through sensing devices 106 and Fig 3 illustrates First stage 306 may process data in response to the clock signal at a first data rate equal to the clock rate of the clock signal and second stage 312.sub.1 to 312.sub.N may process data received from first stage 306 at a second data rate equal to or less than the clock rate times the number of second stages 312.sub.1 to 312.sub.N. in other words, data can be received over 2 different I/O pins for 2 memory devices where first and second data may be processed in two different clock rates in response to clocks signals stages)
It would have been obvious to one of ordinary skill in the art at the time of
Applicant’s filing to combine Duan with Yang for the reasons set forth in claim 1 above. In addition, Duan, Yang and Shakeri are considered analogous arts, because they all relate to data transfer methods in memory system. Duan – Yang combination teaches data transfer methods in memory system with adjusting data transfer based on memory type. On the other hand, Shakeri also teaches data transfer methods in memory system and data can be received over 2 different I/O pins for 2 memory devices where first and second data may be processed in two different clock rates in response to clocks signals stages. Therefore, it would have been obvious to one of ordinary skill at the time the invention was effectively filed to combine Duan – Yang combination with Shakeri to specify data transfer methods in memory system and data can be received over 2 different I/O pins for 2 memory devices where first and second data may be processed in two different clock rates in response to clocks signals stages providing mitigation of the effects of variations between clock signal paths and data paths as mentioned in paragraph [0023].
Regarding claim 9, Duan in view of Yang teaches data transfer methods in memory system in claim 8. However, Duan - Yang combination does not explicitly teach The apparatus of claim 8, wherein the first clock rate is half of the second clock rate.
On the other hand, Shakeri which also relates to managing power consumption
with transferring data in memory system teaches The apparatus of claim 8, wherein the first clock rate is half of the second clock rate. (“By using the N-way architecture for a sensing stage, the data rate of each sensing device 430.sub.1 to 430.sub.N of the sensing stage can be reduced by N times the clock rate without affecting the transmission speed to and from the stage. For example, for a clock rate of 10 ns and where N equals five, each sensing device 430.sub.1 to 430.sub.N has 50 ns to sense the data from the memory array”) (paragraph [0075] line 2-6) (i.e. Fig 10 illustrates N-way architecture for a sensing stage the data rate of each sensing device 430.sub.1 to 430.sub.N of the sensing stage can be reduced by N times the clock rate. In other words, clocks rate can be reduced by any number for different transfer modes.
The same motivation that was utilized for combining Duan - Yang combination with Shakeri as set forth in claim 8 is equally applicable to claim 9.
Claim(s) 10 is rejected under 35 U.S.C. 103 as being unpatentable over Duan et al. (US 20210279010 A1) in view of Yang et al. (US 10971215 B1) and further in view of JEE et al. (US 20220262414 A1) hereinafter Duan and Yang and JEE.
Regarding claim 10, Duan in view of Yang teaches data transfer methods in memory system in claim 1. However, Duan - Yang combination does not explicitly teach The apparatus of claim 1, wherein the clock rate corresponds to a periodicity associated with the clock signal
On the other hand, JEE which also relates to managing power consumption
with transferring data in memory system teaches The apparatus of claim 1, wherein the clock rate corresponds to a periodicity associated with the clock signal. (“when the delay of each delay cell is 10 picoseconds and the period of the input clock signal PHY Clock is 2,000 picoseconds (500 MHz)”) (paragraph [0075] line 2-6) (i.e. Fig 6 illustrates period of the input clock signal PHY Clock is 2,000 picoseconds (500 MHz). in other words, clock rate of PHY Clock corresponds to periodicity associated with the clock)
It would have been obvious to one of ordinary skill in the art at the time of
Applicant’s filing to combine Duan with Yang for the reasons set forth in claim 1 above. In addition, Duan, Yang and JEE are considered analogous arts, because they all relate to data transfer methods in memory system. Duan – Yang combination teaches data transfer methods in memory system with adjusting data transfer based on memory type. On the other hand, JEE also teaches data transfer methods in memory system and clock rate of PHY Clock corresponds to periodicity associated with the clock. Therefore, it would have been obvious to one of ordinary skill at the time the invention was effectively filed to combine Duan – Yang combination with JEE to specify data transfer methods in memory system and clock rate of PHY Clock corresponds to periodicity associated with the clock providing frequency of a memory interface optimization for performance according to a memory access type as mentioned in paragraph [0010].
Claim(s) 12 is rejected under 35 U.S.C. 103 as being unpatentable Duan et al. (US 20210279010 A1) in view of Yang et al. (US 10971215 B1) and further in view of Hollis et al. (US 20190215199 A1) hereinafter Duan and Yang and Hollis.
Regarding claim 12, Duan in view of Yang teaches data transfer methods in memory system in claim 1. However, Duan - Yang combination does not explicitly teach The apparatus of claim 1, wherein the controller is further configured to cause the apparatus to: transmit, to the controller, the clock signal with a first amplitude;
determine to write second data to one or more second memory cells comprising the second type of memory cells; and transmit, to the controller, the clock signal with a second amplitude less than the first amplitude
On the other hand, Hollis which also relates to managing power consumption
with transferring data in memory system teaches The apparatus of claim 1, wherein the controller is further configured to cause the apparatus to: transmit, to the controller, the clock signal with a first amplitude;
determine to write second data to one or more second memory cells comprising the second type of memory cells; and transmit, to the controller, the clock signal with a second amplitude less than the first amplitude. (“The eye diagram 200 may be used to identify a rise time 230 and/or a fall time 235 for transitions from a first amplitude 205 to a second amplitude 205”) (paragraph [0044] line 1-2)
(“Each of the plurality of channels 115 may be configured to couple the array of memory cells 105 with the controller 110”) (paragraph [0031] line 1-2)
(“each memory cell may be programmed to store two or more logic states (e.g., a logic ‘0’, a logic ‘1’, a logic ‘00’, a logic ‘01’, a logic ‘10’, a logic ‘11’, etc.)”) (paragraph [0021] line 1-3) (i.e. Fig 1 illustrates plurality of channels 115 may be configured to couple the array of memory cells 105 with the controller 110 where each memory cell may be programmed single bit or multiple bits and Fig 2 illustrates first and second signal voltage amplitude 205. In other words, controller is coupled with different types of arrays and signal voltage amplitudes are identified by eye diagram)
It would have been obvious to one of ordinary skill in the art at the time of
Applicant’s filing to combine Duan with Yang for the reasons set forth in claim 1 above. In addition, Duan, Yang and Hollis are considered analogous arts, because they all relate to data transfer methods in memory system. Duan – Yang combination teaches data transfer methods in memory system with adjusting data transfer based on memory type. On the other hand, Hollis also teaches data transfer methods in memory system and controller is coupled with different types of arrays and signal voltage amplitudes are identified by eye diagram. Therefore, it would have been obvious to one of ordinary skill at the time the invention was effectively filed to combine Duan – Yang combination with Hollis to specify data transfer methods in memory system and signal voltage amplitudes are identified by eye diagram providing improvement of memory devices, generally, may include increasing memory cell density, increasing read/write speeds, increasing reliability, increasing data retention, reducing power consumption, or reducing manufacturing costs, among other metrics as mentioned in paragraph [0005].
Claim(s) 21 is rejected under 35 U.S.C. 103 as being unpatentable Duan et al. (US 20210279010 A1) in view of Yang et al. (US 10971215 B1) and further in view of Shaeffer et al. (US 20120311371 A1) hereinafter Duan and Yang and Shaeffer.
Regarding claim 21, Duan in view of Yang teaches data transfer methods in memory system in claim 1. However, Duan - Yang combination does not explicitly teach The apparatus of claim 1, wherein to adjust the clock rate, the controller is configured to cause the apparatus to: reduce the clock rate.
On the other hand, Shaeffer which also relates to data transfer methods in
memory System teaches The apparatus of claim 1, wherein to adjust the clock rate, the controller is configured to cause the apparatus to: reduce the clock rate. (see Fig 7, paragraph [0086], illustrates adjustment for a clock to be employed when accessing a particular type of memory device)
It would have been obvious to one of ordinary skill in the art at the time of
Applicant’s filing to combine Duan with Yang for the reasons set forth in claim 1 above. In addition, Duan, Yang and Shaeffer are considered analogous arts, because they all relate to data transfer methods in memory system. Duan – Yang combination teaches data transfer methods in memory system with adjusting data transfer based on memory type. On the other hand, Shaeffer also teaches data transfer methods in memory system and adjustment for a clock to be employed when accessing a particular type of memory device. Therefore, it would have been obvious to one of ordinary skill at the time the invention was effectively filed to combine Duan – Yang combination with Shaeffer to specify data transfer methods in memory system and adjustment for a clock to be employed when accessing a particular type of memory device providing high storage capacity-to-cost ratio as mentioned in paragraph [0003].
Response to Arguments
Applicant’s arguments filed on 03/09/2026 have been fully considered but they
are not persuasive.
Applicant’s first argument is claims 1,13 and 20 amendments mapping by
secondary reference Shaeffer and combination of references in page 10 of the response: Shaeffer is generally directed to "[a] memory controller [that] accesses different types of memory devices running at different native rates through the use of a time division multiplexed bus." Shaeffer [Abstract]. At portions cited by the Office Action, Shaeffer describes "different clock rates of clocks fast clock 112 and slow clock 116 corresponding to different types of memory device 106 and 108 from memory controller 102." See Office Action, p. 43.
The Office Action alleges that the clock rate selection is relevant to the linkage between the clock rate and memory cell density. However, selecting a clock rate based on two separate, physically distinct memory devices (i.e., not memory cell type) does not teach or suggest "one or more memory devices comprising one or more memory cells, the one or more memory cells comprising a first type of memory cells and a second type of memory cells." Shaeffer discloses a memory controller that accesses "different types of memory devices running at different native rates" via a time division multiplexed (TDM) shared bus. The specific example given throughout Shaeffer is a DRAM device (memory device 106, the "faster type of memory") and a flash memory device (memory device 108, the "slower type of memory"). Shaeffer [0036]. These are two entirely separate, physically distinct memory devices of different memory technologies (volatile DRAM vs. non-volatile flash), and distinguished based on native I/O transfer rates not on the storage density of the type of memory cell within a single device. Thus, Shaeffer does not teach or suggest "one or more memory devices comprising one or more memory cells, the one or more memory cells comprising a first type of memory cells and a second type of memory cells," as recited in amended independent claim 1.
Duan and Yang do not overcome the deficiencies of Shaeffer, nor does the Office Action suggest otherwise
In summary, applicant argued that secondary reference Shaeffer and combination of references do not teach amended limitation different controller access rates for different memory cell types. The argument is considered and examiner mapped the limitations with secondary reference Yang in this regard in the relevant claims above. For further clarification examiner cites portion from Yang. Also, for applicant’s understanding examiner would like to explain the teachings of Yang and examiner’s interpretation in more detail here. See Fig 3 and 4, col 15 line 1-3, 24-26, Yang teaches MLC data transfer speed or clock rate is configured specifically for MLC cells storage and SLC data transfer speed or clock rate is configured specifically for SLC cells storage. Also see Fig 4, col 13 line 52-55, Yang teaches non-volatile memory 118 may include SLC type storage blocks 404 which first type and MLC type storage blocks 406 which is second type of memory. The cited portions clearly teach data transfer rate or clock rate are configured differently for different memory cell type memory storages. Thus, the rejection of amended claims 1,13 and 20 are maintained.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/S.K.C./Examiner, Art Unit 2132
/HOSAIN T ALAM/Supervisory Patent Examiner, Art Unit 2132
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