DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I in the reply filed on 6/10/2026 is acknowledged.
Claims 18-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Group, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 6/10/2026.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 7 and 9-17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 7 recites the limitations “a constant determined according to a material of the substrate is B, following equation (1) is satisfied L2 ≥ (A−L1)×B … (1) where B = 0.003 holds in a case where the material of the substrate is silicon nitride, B = 0.015 holds in a case where the material of the substrate is silicon oxynitride, and B = 0.044 holds in a case where the material of the substrate is silicon oxide”. Claim 1, earlier in the chain of dependency, also recited the limitation “a substrate on which the semiconductor layer is laminated”. However, it was not required that the material of the substrate be selected from a group consisting of silicon nitride, silicon oxide, and silicon oxynitride. If the substrate includes a different material, there is no basis for assigning a value for the constant ‘B’ in equation (1) of claim 7, rendering an analysis of the claimed equation (technically a non-strict inequality) indefinite because the claim has not provided a basis for determining a value for B when it is a different material (e.g. borosilicate glass).
For purposes of examination on the merits, it will be understood that if the claimed substrate is formed of a different material than SiO, SiN, and SiON, the value of ‘B’ may be set at an arbitrary level. Since equation (1) is a non-strict inequality L2 ≥ (A−L1)×B, satisfied by the thickness value of L2 being greater than or equal to a difference of thicknesses A-L1 multiplied by a constant B, a sufficiently low value for B being set for a material of the substrate not being SiO, SiN, or SiON will satisfy the inequality regardless of the values of L1, L2, and A.
Claim 9 recites the limitations “a substrate on which a semiconductor layer and a wiring layer are laminated” and “a constant determined according to a material of the substrate is B, following equation (1) is satisfied L2 ≥ (A−L1)×B … (1) where B = 0.003 holds in a case where the material of the substrate is silicon nitride, B = 0.015 holds in a case where the material of the substrate is silicon oxynitride, and B = 0.044 holds in a case where the material of the substrate is silicon oxide”. However, it was not required that the material of the substrate be selected from a group consisting of silicon nitride, silicon oxide, and silicon oxynitride. If the substrate includes a different material, there is no basis for assigning a value for the constant ‘B’ in equation (1) of claim 7, rendering an analysis of the claimed equation (technically a non-strict inequality) indefinite because the claim has not provided a basis for determining a value for B when it is a different material (e.g. borosilicate glass).
For purposes of examination on the merits, it will be understood that if the claimed substrate is formed of a different material than SiO, SiN, and SiON, the value of ‘B’ may be set at an arbitrary level. Since equation (1) is a non-strict inequality L2 ≥ (A−L1)×B, satisfied by the thickness value of L2 being greater than or equal to a difference of thicknesses A-L1 multiplied by a constant B, a sufficiently low value for B being set for a material of the substrate not being SiO, SiN, or SiON will satisfy the inequality regardless of the values of L1, L2, and A.
Due to their dependence on claim 9, claims 10-17 are also rejected on this basis.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-4, 8, and 21 are rejected under 35 U.S.C. 103 as being unpatentable over US patent publication US 20220415936 A1 (Jeon et al hereinafter Jeon).
Regarding claim 1, Jeon discloses a photoelectric conversion apparatus (FIG. 8 image sensor 100C, which illustrates an embodiment of cross section A2-A2’ of FIG. 1) that comprises a semiconductor layer (semiconductor substrate 110 ¶ [0028]), the photoelectric conversion apparatus comprising: a plurality of photoelectric conversion elements (FIGS. 1 and 8, active pixels AP ¶ [0032]) that each include a photoelectric conversion unit (FIG. 8, photoelectric conversion region PD ¶ [0037]) disposed on a side of a first surface (FIG. 8, an upper side of a lower surface of substrate 110) of the semiconductor layer, and in which light of a light source enters from a side of a second surface (FIG. 8, light may enter through microlens ML and color filter CF at lower side of upper surface of substrate 110 ¶ [0052]) opposite to the first surface of the semiconductor layer;
a first element isolation portion (FIG. 8, first pixel isolation structure 130 ¶ [0070]) that extends in the semiconductor layer from the first surface toward the second surface between a neighboring first photoelectric conversion element and second photoelectric conversion element of the plurality of photoelectric conversion elements (FIGS. 1 and 8, an instance of first pixel isolation structure 130 extends from a lower surface of substrate 110 toward the upper surface, and it separates two instances of active pixels AP from each other); and a second element isolation portion (FIG. 8, second pixel isolation structure 140 ¶ [0078]) that extends in the semiconductor layer from the second surface toward the first surface between the first photoelectric conversion element and the second photoelectric conversion element, and comes into contact with the first element isolation portion (FIG. 8, an instance of second pixel isolation structure 140 extends from an upper surface of substrate 110 toward a lower surface, is between two instances of active pixel AP, and contacts first pixel isolation structure 130), wherein
the first element isolation portion includes a coated portion (FIG. 8, conductive layer 132 has a coating around it ¶ [0073]) whose conductive material is coated with an insulation material (FIG. 8, first insulating liner 131 coats conductive material 132 and may be formed of SiO, SiN, or SiON ¶ [0074]) containing silicon oxide, silicon nitride, silicon oxynitride, or a combination of the silicon oxide, the silicon nitride, and the silicon oxynitride, the coated portion is in contact with the second element isolation portion (FIG. 8, insulating liner 131 of the coated portion contacts second pixel isolation structure 140).
Jeon does not disclose that a film thickness of the insulation material in a cross section vertical to a substrate on which the semiconductor layer is laminated is 10 nm or more in a case where the insulation material is silicon nitride, 150 nm or more in a case where the insulation material is silicon oxide, and 50 nm or more in a case where the insulation material is silicon oxynitride, a film thickness of the insulation material not being a parameter of particular emphasis in the disclosure of their invention.
However, Jeon does teach that the insulation material is used to reduce or prevent an optical crosstalk phenomenon (¶ [0074]), and a person of ordinary skill in the art would recognize that the film thickness of the insulation material influences the amount of protection from optical crosswalk that the material provides, making it a result-effective variable.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to vary, through routine optimization, the thickness of the insulation material as the thickness would be identified as a result-effective variable. Further, one of ordinary skill in the art would have had a reasonable expectation of success to arrive at a configuration wherein a film thickness of the insulation material in a cross section vertical to a substrate on which the semiconductor layer is laminated is 10 nm or more in a case where the insulation material is silicon nitride, 150 nm or more in a case where the insulation material is silicon oxide, and 50 nm or more in a case where the insulation material is silicon oxynitride, as different materials have different optical and insulating properties motivating different threshold thicknesses to maintain a desirable level of preventing crosstalk. MPEP 2144.05.
Furthermore, the applicant has not presented persuasive evidence that the claimed thickness is for a particular purpose that is critical to the overall claimed invention (i.e., that the invention would not work without the specific claimed dimensions).
Regarding claim 2, Jeon discloses the limitations of claim 1 as detailed above and further discloses that the second element isolation portion includes an insulation material or a conductive material (FIG. 8, second pixel isolation structure 140 includes sub-regions second insulating layer 141 and dielectric layer 142, both of which are insulation materials ¶ [0080-0081]).
Regarding claim 3, Jeon discloses the limitations of claim 1 as detailed above and further discloses that the second element isolation portion is not in contact with the conductive material of the coated portion (FIG. 8, second pixel isolation structure 140 does not directly contact conductive layer 132).
Regarding claim 4, Jeon discloses the limitations of claim 1 as detailed above and further discloses that a layer of the conductive material and a layer of the insulation material of the coated portion of the first element isolation portion, and a layer of the second element isolation portion are laminated in a direction from the first surface to the second surface (FIG. 8, conductive layer 132, first insulating layer 131, and dielectric layer 142 are laminated in a direction from the first/lower surface of substrate 110 to the second/upper surface of substrate 110).
Regarding claim 8, Jeon discloses the limitations of claim 1 as detailed above and further discloses that the first photoelectric conversion element and the second photoelectric conversion element are photodiodes (FIG. 8, photoelectric conversion region PD may be a pinned photo diode PPD ¶ [0139]).
Regarding claim 21, Jeon discloses the limitations of claim 1 as detailed above and further teaches that common applications of image sensors are in smartphones, robots, and Internet of Things, among others (¶ [0003]), and that their disclosed image sensor may be configured to transmit or receive electrical signals to and from an external device (¶ [0030]). Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to apply the disclosed photoelectric conversion apparatus in a machine device that operates on a basis of information obtained by the photoelectric conversion apparatus (e.g. a robot ¶ [0003]) in order to assemble a robot which can interact with its environment based on the optical data received by the photoelectric conversion apparatus.
Claims 1 and 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over US patent publication US 20200219912 A1 (Ro et al hereinafter Ro).
Regarding claim 1, Ro discloses a photoelectric conversion apparatus (the image sensor of FIGS. 3-4B ¶ [0013-0014]) that comprises a semiconductor layer (FIG. 4A, semiconductor substrate 100 ¶ [0047]), the photoelectric conversion apparatus comprising: a plurality of photoelectric conversion elements (FIG. 4A, pixel regions PR ¶ [0050]) that each include a photoelectric conversion unit (FIG. 4A, photoelectric conversion regions 110 function as conversion units ¶ [0047]) disposed on a side of a first surface of the semiconductor layer (FIG. 4A, based on the orientation of the figure regions 110 are on the bottom of an upper side along the D3 direction), and in which light of a light source enters from a side of a second surface opposite to the first surface of the semiconductor layer (FIG. 4A, based on the orientation of the figure light may enter through micro-lenses 307 at a lower side along the D3 direction ¶ [0065]);
a first element isolation portion (FIG. 4A, second device isolation structure 103 and a portion of first dielectric pattern IP1 at the same level along the D3 direction as conductive pattern SP2 and dielectric patterns IP3 and IP4 ¶ [0056, 0070]) that extends in the semiconductor layer from the first surface toward the second surface (FIG. 4A, structure 103 and pattern IP1 begin at the upper surface of semiconductor substrate 100 and extend toward its lower surface) between a neighboring first photoelectric conversion element and second photoelectric conversion element (FIG. 4A, structure 103 and pattern IP1 are between two instances of pixel region PR) of the plurality of photoelectric conversion elements; and a second element isolation portion (FIG. 4A, first conductive pattern SP1 extends from the lower surface toward the upper surface ¶ [0070]) that extends in the semiconductor layer from the second surface toward the first surface between the first photoelectric conversion element and the second photoelectric conversion element (FIG. 4A, pattern SP1 is between two instances of pixel region PR), and comes into contact with the first element isolation portion (FIG. 4A, conductive pattern SP1 contacts the dielectric pattern IP1 portion at the same levels along the D3 direction as an upper portion of conductive pattern SP2 and dielectric pattern IP3), wherein
the first element isolation portion includes a coated portion (FIG. 4A, second device isolation structure 103 and a portion of first dielectric pattern IP1 at the same level along the D3 direction as conductive pattern SP2 and dielectric patterns IP3 and IP4 form a coated portion) whose conductive material (FIG. 4A, conductive pattern SP2 is a conductive material ¶ [0070-0072]) is coated with an insulation material (FIG. 4A, dielectric patterns IP1 and IP3 coat conductive pattern SP2 and may independently be formed of silicon oxide, silicon nitride, or silicon oxynitride ¶ [0072, 0081]) containing silicon oxide, silicon nitride, silicon oxynitride, or a combination of the silicon oxide, the silicon nitride, and the silicon oxynitride, the coated portion is in contact with the second element isolation portion (FIG. 4A, portion of first dielectric pattern IP1 at the same level along the D3 direction as conductive pattern SP2 and dielectric patterns IP3 includes an upper portion which contacts conductive pattern SP1), and a film thickness of the insulation material in a cross section vertical to a substrate (FIG. 4A, interlayer dielectric layer 223 is a substrate layer which semiconductor substrate 100 is laminated on the bottom of ¶ [0063]) on which the semiconductor layer is laminated is present.
Ro does not quantify the film thickness to be 10 nm or more in a case where the insulation material is silicon nitride, 150 nm or more in a case where the insulation material is silicon oxide, and 50 nm or more in a case where the insulation material is silicon oxynitride.
However, Ro does teach that the insulation material insulates conductive patterns SP1 and SP2 from each other (¶ [0080]), and pattern SP2 from substrate 100 (¶ [0079]), preventing the same voltages from being simultaneously applied to conductive patterns SP1 and SP2, thereby reducing the possibility of signal crosstalk, and a person of ordinary skill in the art would recognize that the film thickness of the insulation material influences the amount of protection from optical crosstalk that the material provides, making it a result-effective variable.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to vary, through routine optimization, the thickness of the insulation material as the thickness would be identified as a result-effective variable. Further, one of ordinary skill in the art would have had a reasonable expectation of success to arrive at a configuration wherein a film thickness of the insulation material is 10 nm or more in a case where the insulation material is silicon nitride, 150 nm or more in a case where the insulation material is silicon oxide, and 50 nm or more in a case where the insulation material is silicon oxynitride, as different materials have different optical and insulating properties motivating different threshold thicknesses to maintain a desirable level of preventing crosstalk. MPEP 2144.05.
Furthermore, the applicant has not presented persuasive evidence that the claimed thickness is for a particular purpose that is critical to the overall claimed invention (i.e., that the invention would not work without the specific claimed dimensions).
Regarding claim 5, Ro discloses the limitations of claim 1 as detailed above, and further discloses that a layer of the insulation material of the first element isolation portion (FIG. 4A, in this case, third dielectric pattern IP3 of the insulation material) includes a portion that is made discontinuous by the second element isolation portion in a cross section vertical to the substrate on which the semiconductor layer is laminated (FIG. 4A, third dielectric pattern IP3 of the insulation material is made discontinuous by first conductive pattern SP1 being disposed between portions of it).
Regarding claim 6, Ro discloses the limitations of claim 5 as detailed above, and further discloses that an interface between the layer of the insulation material and a layer of the conductive material of the first element isolation portion is not in contact with the second element isolation portion in the cross section vertical to the substrate on which the semiconductor layer is laminated (FIG. 4A, the interface of third dielectric pattern IP3 and second conductive pattern SP2 does not contact first conductive pattern SP1).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Ro as applied to claim 1 above, and further in view of US patent publication US 20220223634 A1 (Yang et al hereinafter Yang).
Ro discloses the limitations of claim 5 as detailed above, and further discloses that the photoelectric conversion apparatus comprises the substrate on which the semiconductor layer and a wiring layer are laminated (FIG. 4A, a wiring layer including connection lines 212 and 213 is laminated on semiconductor substrate 100 and under interlayer dielectric substrate layer 223 ¶ [0063]). Ro does not further teach that in a case where a distance from the first surface to a distal end of the coated portion in the cross section vertical to the substrate is L1, a thickness of the insulation material of the coated portion in a vertical direction or a horizontal direction of the cross section is L2, a thickness of the substrate is A, and a constant determined according to a material of the substrate is B, following equation (1) is satisfied L2 ≥ (A−L1)×B … (1) where B = 0.003 holds in a case where the material of the substrate is silicon nitride, B = 0.015 holds in a case where the material of the substrate is silicon oxynitride, and B = 0.044 holds in a case where the material of the substrate is silicon oxide, as a material for the interlayer dielectric substrate layer 223 was not taught by Ro.
However, Yang discloses a photoelectric conversion apparatus (the image sensor of FIG. 3A ¶ [0005]) wherein an interconnect structure (FIG. 3A, interconnect dielectric structure 308 ¶ [0027]) of analogous position and function to the claimed substrate layer in Ro may be formed of a variety of materials (including silicon carbide, borosilicate glass (BSG), phosphoric silicate glass (PSG), and borophosphosilicate glass (BPSG) ¶ [0042]), which would serve the purpose of providing structural support and insulation for the wirings.
Ro and Yang both pertain to the field of photoelectric conversion devices, placing them in the same field of endeavor as the claimed invention. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to modify the device of Ro in view of Yang to provide the substrate being formed of one of the materials taught by Yang, e.g. borosilicate glass BSG, as that material has been taught as suitable for the intended purpose and may be found beneficial after consideration of materials costs and changing market conditions. Having done so, the remaining limitations of the claim pertaining to equation (1) may be satisfied, as the value of the constant B in the inequality may be set at a very low value (refer back to rejection of this claim under 35 U.S.C. 112b for further detail), making the right side of the inequality L2 ≥ (A−L1)×B very low, such that the inequality is satisfied.
Claims 9-17 are rejected under 35 U.S.C. 103 as being unpatentable over Ro in view of Yang.
Regarding claim 9, Ro discloses a photoelectric conversion apparatus (the image sensor of FIGS. 3-4B ¶ [0013-0014]) that comprises a substrate (FIG. 4A, interlayer dielectric layer 223 is a substrate layer ¶ [0063]) on which a semiconductor layer (FIG. 4A, semiconductor substrate 100 laminated on layer 223 ¶ [0047]) and a wiring layer (FIG. 4A, a wiring layer including connection lines 212 and 213 is laminated on semiconductor substrate 100 and under interlayer dielectric substrate layer 223 ¶ [0063]) are laminated, the photoelectric conversion apparatus comprising: a plurality of photoelectric conversion elements (FIG. 4A, pixel regions PR ¶ [0050]) that each include a photoelectric conversion unit (FIG. 4A, photoelectric conversion regions 110 function as conversion units ¶ [0047]) disposed on a side of a first surface of the semiconductor layer (FIG. 4A, based on the orientation of the figure regions 110 are on the bottom of an upper side along the D3 direction), and in which light of a light source enters from a side of a second surface (FIG. 4A, based on the orientation of the figure light may enter through micro-lenses 307 at a lower side along the D3 direction ¶ [0065]) opposite to the first surface of the semiconductor layer;
a first element isolation portion (FIG. 4A, second device isolation structure 103 and a portion of first dielectric pattern IP1 at the same level along the D3 direction as conductive pattern SP2 and dielectric patterns IP3 and IP4 ¶ [0056, 0070]) that extends in the semiconductor layer from the first surface toward the second surface (FIG. 4A, structure 103 and pattern IP1 begin at the upper surface of semiconductor substrate 100 and extend toward its lower surface) between a neighboring first photoelectric conversion element and second photoelectric conversion element (FIG. 4A, structure 103 and pattern IP1 are between two instances of pixel region PR) of the plurality of photoelectric conversion elements; and a second element isolation portion (FIG. 4A, first conductive pattern SP1 extends from the lower surface toward the upper surface ¶ [0070]) that extends in the semiconductor layer from the second surface toward the first surface between the first photoelectric conversion element and the second photoelectric conversion element (FIG. 4A, pattern SP1 is between two instances of pixel region PR), and comes into contact with the first element isolation portion (FIG. 4A, conductive pattern SP1 contacts the dielectric pattern IP1 portion at the same levels along the D3 direction as an upper portion of conductive pattern SP2 and dielectric pattern IP3), wherein
the first element isolation portion includes a coated portion (FIG. 4A, second device isolation structure 103 and a portion of first dielectric pattern IP1 at the same level along the D3 direction as conductive pattern SP2 and dielectric patterns IP3 and IP4 form a coated portion) whose conductive material (FIG. 4A, conductive pattern SP2 is a conductive material ¶ [0070-0072]) is coated with an insulation material (FIG. 4A, dielectric patterns IP1 and IP3 coat conductive pattern SP2 and may independently be formed of silicon oxide, silicon nitride, or silicon oxynitride ¶ [0072, 0081]), the coated portion is in contact with the second element isolation portion (FIG. 4A, portion of first dielectric pattern IP1 at the same level along the D3 direction as conductive pattern SP2 and dielectric patterns IP3 includes an upper portion which contacts conductive pattern SP1).
Ro does not further teach that in a case where a distance from the first surface to a distal end of the coated portion in a cross section vertical to the substrate is L1, a thickness of the insulation material of the coated portion in a vertical direction or a horizontal direction of the cross section is L2, a thickness of the substrate is A, and a constant determined according to a material of the substrate is B, following equation (1) is satisfied L2 ≥ (A−L1)×B … (1) where B = 0.003 holds in a case where the material of the substrate is silicon nitride, B = 0.015 holds in a case where the material of the substrate is silicon oxynitride, and B = 0.044 holds in a case where the material of the substrate is silicon oxide, as a material for the interlayer dielectric substrate layer 223 was not taught by Ro.
However, Yang discloses a photoelectric conversion apparatus (the image sensor of FIG. 3A ¶ [0005]) wherein an interconnect structure (FIG. 3A, interconnect dielectric structure 308 ¶ [0027]) of analogous position and function to the claimed substrate layer in Ro may be formed of a variety of materials (including silicon carbide, borosilicate glass (BSG), phosphoric silicate glass (PSG), and borophosphosilicate glass (BPSG) ¶ [0042]), which would serve the purpose of providing structural support and insulation for the wirings.
Ro and Yang both pertain to the field of photoelectric conversion devices, placing them in the same field of endeavor as the claimed invention. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to modify the device of Ro in view of Yang to provide the substrate being formed of one of the materials taught by Yang, e.g. borosilicate glass BSG, as that material has been taught as suitable for the intended purpose and may be found beneficial after consideration of materials costs and changing market conditions. Having done so, the remaining limitations of the claim pertaining to equation (1) may be satisfied, as the value of the constant B in the inequality may be set at a very low value (refer back to rejection of this claim under 35 U.S.C. 112b for further detail), making the right side of the inequality L2 ≥ (A−L1)×B very low, such that the inequality is satisfied.
Regarding claim 10, Ro in view of Yang discloses the limitations of claim 9 as detailed above, and Ro further discloses that the insulation material contains silicon oxide, silicon nitride, silicon oxynitride, or a combination of the silicon oxide, the silicon nitride, and the silicon oxynitride (Ro FIG. 4A, dielectric patterns IP1 and IP3 coat conductive pattern SP2 and may independently be formed of silicon oxide, silicon nitride, or silicon oxynitride ¶ [0072, 0081]).
Regarding claim 11, Ro in view of Yang discloses the limitations of claim 10 as detailed above, but they do not further quantify a film thickness of the insulation material in a cross section vertical to the substrate on which the semiconductor layer is laminated is 10 nm or more in a case where the insulation material is silicon nitride, 150 nm or more in a case where the insulation material is silicon oxide, and 50 nm or more in a case where the insulation material is silicon oxynitride.
However, Ro does teach that the insulation material insulates conductive patterns SP1 and SP2 from each other (¶ [0080]), and pattern SP2 from substrate 100 (¶ [0079]), preventing the same voltages from being simultaneously applied to conductive patterns SP1 and SP2, thereby reducing the possibility of signal crosstalk, and a person of ordinary skill in the art would recognize that the film thickness of the insulation material influences the amount of protection from optical crosstalk that the material provides, making it a result-effective variable.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to vary, through routine optimization, the thickness of the insulation material as the thickness would be identified as a result-effective variable. Further, one of ordinary skill in the art would have had a reasonable expectation of success to arrive at a configuration wherein a film thickness of the insulation material is 10 nm or more in a case where the insulation material is silicon nitride, 150 nm or more in a case where the insulation material is silicon oxide, and 50 nm or more in a case where the insulation material is silicon oxynitride, as different materials have different optical and insulating properties motivating different threshold thicknesses to maintain a desirable level of preventing crosstalk. MPEP 2144.05.
Furthermore, the applicant has not presented persuasive evidence that the claimed thickness is for a particular purpose that is critical to the overall claimed invention (i.e., that the invention would not work without the specific claimed dimensions).
Regarding claim 12, Ro in view of Yang discloses the limitations of claim 9 as detailed above, and Ro further discloses that the second element isolation portion includes an insulation material or a conductive material (Ro FIG. 4A, first conductive pattern SP1 is a conductive material ¶ [0070-0072]).
Regarding claim 13, Ro in view of Yang discloses the limitations of claim 9 as detailed above, and Ro further discloses that the second element isolation portion is not in contact with the conductive material of the coated portion (Ro FIG. 4A, conductive patterns SP1 and SP2 are not in direct contact with each other).
Regarding claim 14, Ro in view of Yang discloses the limitations of claim 9 as detailed above, and Ro further discloses that a layer of the conductive material (Ro FIG. 4A, second conductive pattern SP2) and a layer of the insulation material of the coated portion (FIG. 4A, the portion of insulation pattern IP1 between conductive patterns SP1 and SP2) of the first element isolation portion, and a layer of the second element isolation portion (FIG. 4A, first conductive pattern SP1) are laminated in a direction (annotated FIG. 4A below, a diagonal direction goes from the first surface toward the second surface of substrate 100, and the lamination can be on a vector drawn along that direction) from the first surface toward the second surface.
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Regarding claim 15, Ro in view of Yang discloses the limitations of claim 9 as detailed above, and Ro further discloses that a layer of the insulation material of the first element isolation portion includes a portion that is made discontinuous by the second element isolation portion in a cross section vertical to the substrate on which the semiconductor layer is laminated (Ro FIG. 4A, in the cross section of the figure, insulating pattern IP3 is made discontinuous by the portion of conductive pattern SD1 that contacts insulation pattern IP2).
Regarding claim 16, Ro in view of Yang discloses the limitations of claim 15 as detailed above, and Ro further discloses that an interface between the layer of the insulation material and a layer of the conductive material of the first element isolation portion is not in contact with the second element isolation portion in the cross section vertical to the substrate on which the semiconductor layer is laminated (Ro FIG. 4A, the interface of insulating pattern IP3 with conductive pattern SP2 does not directly contact conductive pattern SP1).
Regarding claim 17, Ro in view of Yang discloses the limitations of claim 9 as detailed above, and Ro further discloses that the first photoelectric conversion element and the second photoelectric conversion element are photodiodes (Ro FIG. 4A, substrate 100 and conversion region 110 together form photodiodes ¶ [0055]).
Cited Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: US patent publications US 20230197754 A1, US 20220052092 A1, US 20210043593 A1, US 20200227455 A1, and US 20190378865 A1.
Conclusion
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/E.R.C./Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
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