Prosecution Insights
Last updated: August 16, 2026
Application No. 18/595,878

SEMICONDUCTOR LIGHT-RECEIVING DEVICE

Non-Final OA §103
Filed
Mar 05, 2024
Priority
Mar 07, 2023 — JP 2023-034592
Examiner
MORA, ONASIS
Art Unit
4100
Tech Center
4100
Assignee
Sumitomo Electric Industries Ltd.
OA Round
1 (Non-Final)
Grant Probability
Favorable
1-2
OA Rounds

Examiner Intelligence

Grants only 0% of cases
0%
Career Allowance Rate
0 granted / 0 resolved
-60.0% vs TC avg
Minimal +0% lift
Without
With
+0.0%
Interview Lift
resolved cases with interview
Typical timeline
Avg Prosecution
6 currently pending
Career history
3
Total Applications
across all art units

Statute-Specific Performance

§103
83.3%
+43.3% vs TC avg
§102
16.7%
-23.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 0 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Priority Acknowledgment is made of applicant's claim for foreign priority based on an application filed in Japan on March 07, 2023. It is noted, however, that applicant has not filed a certified copy of the JP2023-034592 application as required by 37 CFR 1.55. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim(s) 1- 5; 10-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shi (US 10401543) and Park (US 20210242362). Regarding Claim 1, Park teaches a semiconductor light-receiving device (100, Fig. 1, para [0052]) comprising:; a first III-V compound semiconductor layer of n-type (131, Fig. 1, para [0069]); a second III-V compound semiconductor layer of p-type (132, Fig. 1, para [0084]); an optical absorption layer disposed (150, Fig. 1, para [0075]-[0077], called the “light absorbing layer” but accomplishes the same task) between the first III-V compound semiconductor layer (131, Fig. 1, para [0069]) and the second III-V compound semiconductor layer (132, Fig. 1, para [0084]); a cladding layer layer (141, Fig. 1, para [0072]) disposed between the first III-V compound semiconductor layer (131, Fig. 1, para [0069]) and the optical absorption layer (150, Fig. 1, para [0075]-[0077]). wherein the first III-V compound semiconductor layer (131, Fig. 1, para [0069]) is disposed between the indium phosphide substrate and the optical absorption layer. Park fails to explicitly disclose a hole barrier layer. However, Park discloses wherein the cladding layer (element 131) is made of InGaAlAs (Park, para [0068]); which is the same material used in the application. Therefore, the examiner respectfully submits that layer 131 of Park is capable of performing the claimed function and hereinafter have that component referenced as a hole barrier layer. Park also fails to explicitly disclose an indium phosphide substrate as well as an electron blocking layer disposed between the second III-V compound semiconductor layer and the optical absorption layer. However, Shi teaches a related PIN diode comprising, an indium phosphide substrate (11, Fig. 1, para (11)) as well as an electron blocking layer (16, Fig. 1, para (16)) disposed between the second III-V compound semiconductor layer (17, Fig. 1, para (17)) and the optical absorption layer (14 & 15, Fig. 1, para (14) & (15)). In the formation of a III-V compound for the intended use of being a substrate in a semiconductor device, there are only a certain number of total materials that can be combined in a suitable manner. Therefore, it would have been obvious to a person of ordinary skill in the art at the time of the effective filing date to combine the teachings of Park and Shi, to enable the substrate in Park according to the teachings of Shi, because the selection of a known material based on its suitability for its intended use is supported by a prima facie case of obviousness (see MPEP 2144.07). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Park and Shi, to enable the electron blocking layer of Park according to the teachings of Shi, for the further advantage of dark current suppression and improved levels of detectivity. Regarding Claim 2, Park teaches the semiconductor light-receiving device (100, Fig. 1, para [0051]) according to claim 1, wherein the quantum-well light-receiving layer has a type-II superlattice structure. Park does not explicitly disclose a type-II superlattice structure. However, Park discloses wherein the light absorbing layer is made of alternating layers of undoped GaAsSb and InGaAs (see Park, para [0075] – [0077]), which is the same material and orientation used in the application. Therefore, the examiner respectfully submits that layer 150 of Park is capable of performing the claimed function. Accordingly, the light absorbing layer of Park which inherently possesses a type-II superlattice structure is labeled hereinafter the optical absorption layer. Regarding Claim 3, Park teaches the semiconductor light-receiving device according to claim 2 (100, Fig. 1, para [0051]), wherein the superlattice structure includes a gallium indium arsenide layer and a gallium arsenide antimonide layer (150, Fig. 1, para [0075]- [0077]). Regarding Claim 4, Park teaches the semiconductor light-receiving device according to claim 1 (100, Fig. 1, para [0051]), wherein the hole barrier layer is an n-type aluminum gallium indium arsenide layer (131, Fig. 1, para [0068] – [0070]). Regarding Claim 5, Park teaches the semiconductor light-receiving device according to claim 1 (1, Fig. 1, para [0019]), wherein the hole barrier layer is a bulk layer (131 Fig. 1, para [0068] – [0070]). Regarding claim 6, Park teaches the semiconductor light-receiving device according to claim 1 (1, Fig. 1, para [0019]). Park does not explicitly disclose wherein the electron barrier layer is a p-type aluminum gallium arsenide antimonide layer. In a field of similar endeavor Shi teaches a related PIN diode comprising, wherein the electron barrier layer is a p-type aluminum gallium arsenide antimonide layer (16, Fig. 1, para (16)). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Park and Shi, to enable the electron blocking layer of Park according to the teachings of Shi, for the further advantage of dark current suppression and improved levels of detectivity. Regarding Claim 7, Park teaches the semiconductor light-receiving device according to claims 1 (1, Fig. 1, para [0019]), wherein the electron barrier layer is a bulk layer. In a field of similar endeavor Shi teaches a related PIN diode comprising , wherein the electron barrier layer is a bulk layer (16, Fig. 1, para (16)). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Park and Shi, to enable the electron blocking layer of Park according to the teachings of Shi, for the further advantage of dark current suppression and improved levels of detectivity. Regarding Claim 10, Park teaches the semiconductor light-receiving device according to claim 1 (1, Fig. 1, para [0019]). Park does not explicitly teach a non-doped fourth III-V compound semiconductor layer disposed between the hole barrier layer and the optical absorption layer. In a field of similar endeavor, Shi teaches a related PIN diode comprising, a non-doped fourth III-V compound semiconductor layer (14, Fig. 1, para (14)) disposed between the graded layer (13, Fig. 1, para (13)) and the second absorption layer (15, Fig. 1, para (15)). The motivation for modifying Park in view of Shi is found in para (21); wherein “this type of undoped In.sub.0.53Ga.sub.0.47As absorption layer 14 is used in the P-type absorber of a traditional UTC-PD to minimize electron recombination process.” Which is not only the same material as in the applicant’s case but also explicitly references the advantage of that additional layer. Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Park and Shi, to add the InGaAs layer to Park according to the teachings of Shi, for the further advantage of improved device performance. Regarding Claim 11, Park teaches the semiconductor light-receiving device according to claim 10 (1, Fig. 1, para [0019]). Park does not explicitly teach wherein the fourth III-V compound semiconductor layer contains gallium indium arsenide. In a field of similar endeavor, Shi teaches a related PIN diode comprising the fourth III-V compound semiconductor layer contains gallium indium arsenide (14, Fig. 1, para (13) & (21)). The motivation for modifying Park in view of Shi is found in para (21); wherein “this type of undoped In.sub.0.53Ga.sub.0.47As absorption layer 14 is used in the P-type absorber of a traditional UTC-PD to minimize electron recombination process.” Which is not only the same material as in the applicant’s case but also explicitly references the advantage of that additional layer. Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Park and Shi, to add the InGaAs layer to Park according to the teachings of Shi, for the further advantage of improved device performance. Claim(s) 8-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park (US 20210242362) in view of Shi (US 10401543) as applied to claim 1- 5; 10-11 above, and further in view of Fuyuki (US 2019035857). Regarding Claim 8, Park teaches the semiconductor light-receiving device according to claim 1 (1, Fig. 1, para [0019]) Park does not explicitly disclose a non-doped third III-V compound semiconductor layer disposed between the electron barrier layer and the optical absorption layer. In a field of similar endeavor, Fuyuki teaches a semiconductor light-receiving device comprising (1, Fig. 1, para [0019]): an indium phosphide substrate (11, Fig. 1, para [0035]); a first III-V compound semiconductor layer of n-type (12, Fig. 1, para [0037]); a second III-V compound semiconductor layer of p-type (15, Fig. 1, para [0048]); non-doped third III-V compound semiconductor layer (16, Fig. 1, para [0043]) an optical absorption layer (13, Fig. 1, para [0040]) disposed between the first III-V compound semiconductor layer and the second III-V compound semiconductor layer (13, Fig. 1, para [0040]); and a control layer (16. Fig. 1, para) disposed between the second III-V compound semiconductor layer (15, Fig. 1, para [0046]) and the optical absorption layer (13, Fig. 1, para [0040]), wherein the first III-V compound semiconductor layer (12, Fig. 1, para [0037]) is disposed between the indium phosphide substrate (11, Fig. 1, para [0035]) and the optical absorption layer (13, Fig. 1, para [0040]). The motivation for adding a third non-doped compound semiconductor layer is found in Fuyuki para [0021]’ wherein “the presence of the control layer [third non-doped compound semiconductor layer] reduces a sharp change in conduction band level between the diffusion blocking layer [element 15] and the light-receiving layer to reduce the accumulation of the carriers. This reduces a phenomenon in which the extension of a depletion layer is inhibited by the accumulation of the carriers, thus improving the sensitivity of a light-receiving device.” The examiner also notes that the orientation and material of the layer 16 in Fuyuki are the exact same as in the case of the applicant and as such submits that the layers can accomplish the same claimed function and thus derive the same benefit. Therefore, it would have been obvious to one of ordinary skill to modify Park with a non-doped third III-V compound semiconductor layer disposed between the electron barrier layer and the optical absorption layer in order to increase device sensitivity and reduce dark current. Regarding Claim 9, Park teaches the semiconductor light-receiving device according to claim 8 (1, Fig. 1, para [0019]). Park does not explicitly disclose wherein the third III-V compound semiconductor layer contains gallium indium arsenide antimonide. In a field of similar endeavor, Fuyuki teaches a semiconductor light-receiving device comprising (1, Fig. 1, para [0019]): an indium phosphide substrate (11, Fig. 1, para [0035]); a first III-V compound semiconductor layer of n-type (12, Fig. 1, para [0037]); a second III-V compound semiconductor layer of p-type (15, Fig. 1, para [0048]); non-doped third III-V compound semiconductor layer containing gallium indium arsenide antimonide (16, Fig. 1, para [0043]) an optical absorption layer (13, Fig. 1, para [0040]) disposed between the first III-V compound semiconductor layer and the second III-V compound semiconductor layer (13, Fig. 1, para [0040]); and a control layer (16. Fig. 1, para) disposed between the second III-V compound semiconductor layer (15, Fig. 1, para [0046]) and the optical absorption layer (13, Fig. 1, para [0040]), wherein the first III-V compound semiconductor layer (12, Fig. 1, para [0037]) is disposed between the indium phosphide substrate (11, Fig. 1, para [0035]) and the optical absorption layer (13, Fig. 1, para [0040]). The motivation for adding a third non-doped compound semiconductor layer is found in Fuyuki para [0021]’ wherein “the presence of the control layer [third non-doped compound semiconductor layer] reduces a sharp change in conduction band level between the diffusion blocking layer [element 15] and the light-receiving layer to reduce the accumulation of the carriers. This reduces a phenomenon in which the extension of a depletion layer is inhibited by the accumulation of the carriers, thus improving the sensitivity of a light-receiving device.” The examiner also notes that the orientation and material of the layer 16 in Fuyuki are the exact same as in the case of the applicant and as such submits that the layers can accomplish the same claimed function and thus derive the same benefit. Therefore, it would have been obvious to one of ordinary skill to modify Park with a non-doped third III-V compound semiconductor of gallium indium arsenide antimonide in order to increase device sensitivity and reduce dark current. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. NPL Document #2: Low Dark Current Structures for Long-wavelength Type-II Strained Layer Superlattice Photodiodes Document used to show that the knowledge and knowledge of advantages of a pBiBn structure is well-known in the art. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ONASIS MORA whose telephone number is (571)270-0786. The examiner can normally be reached Monday-Friday 9am-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at (571) 272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ONASIS MORA/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
Read full office action

Prosecution Timeline

Mar 05, 2024
Application Filed
Jul 27, 2026
Non-Final Rejection mailed — §103 (current)

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

1-2
Expected OA Rounds
Grant Probability
Low
PTA Risk
Based on 0 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month