DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Examiner Notes
Examiner cites particular columns and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
The examiner encourages Applicant to submit an authorization to communicate with the examiner via the Internet by making the following statement (from MPEP 502.03):
“Recognizing that Internet communications are not secure, I hereby authorize the USPTO to communicate with the undersigned and practitioners in accordance with 37 CFR 1.33 and 37 CFR 1.34 concerning any subject matter of this application by video conferencing, instant messaging, or electronic mail. I understand that a copy of these communications will be made of record in the application file.”
Please note that the above statement can only be submitted via Central Fax, Regular postal mail, or EFS Web (PTO/SB/439).
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-17 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the enablement requirement.
The claims contain subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention. The claims contain subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention. The claimed subject matter for which the specification is not enabling are: “generating a first register index corresponding to the second priority of the second interrupt by using a look-up table based on the second priority of the second interrupt being greater than the first priority.”
There are many factors (“Wands” factors) to be considered when determining whether there is sufficient evidence to support a determination that a disclosure does not satisfy the enablement requirement. These factors include, but are not limited to:(A) The breadth of the claims; (B) The nature of the invention; (C) The state of the prior art; (D) The level of one of ordinary skill; (E) The level of predictability in the art; (F) The amount of direction provided by the inventor; (G) The existence of working examples; and (H) The quantity of experimentation needed to make or use the invention based on the content of the disclosure. Upon consideration of the aforementioned factors, Applicant’s disclosure does not satisfy the enablement requirement because Applicant’s specification does not disclose enough information for one of ordinary skill in the art to generate a first register index corresponding to the second priority of the second interrupt by using a look-up table based on the second priority of the second interrupt being greater than the first priority.
The state of the art at the time of filing shows that controlling interrupt processing by generating a first register index corresponding to the second priority of the second interrupt by using a look-up table based on the second priority of the second interrupt being greater than the first priority is not predictable. The specification does not provide direction as to how to perform this feature. Taking these factors into account, undue experimentation would be required by one of ordinary skill in the art to practice the full scope of claim 1. Thus, claim 1 is not enabled by the disclosure. Applicant cannot rely on the knowledge of one skilled in the art to supply information that is required to enable the novel aspect of the claimed invention when the enabling knowledge is in fact not known in the art. ALZA Corp. v. Andrx Pharms., LLC, 603 F.3d 935, 941, 94 USPQ2d 1823, 1827 (Fed. Cir. 2010) ("ALZA was required to provide an adequate enabling disclosure in the specification; it cannot simply rely on the knowledge of a person of ordinary skill to serve as a substitute for the missing information in the specification").
Claims 2-11 are rejected for their dependence on independent claim 1.
Claim 12 contains the following similar language: “wherein the look-up table is configured to generate a register index corresponding to the priority of the interrupt to be executed based on a comparison result indicating that the priority of the interrupt to be executed is greater than the priority of the interrupt being executed” and fails to comply with the enablement requirement for the same reasons as claim 1. Claims 13-17 are rejected for their dependence on independent claim 12.
Claim 3 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the enablement requirement.
The claims contain subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention. The claims contain subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention. The claimed subject matter for which the specification is not enabling are: “wherein the look-up table comprises a common index and at least two dedicated indexes.”
There are many factors (“Wands” factors) to be considered when determining whether there is sufficient evidence to support a determination that a disclosure does not satisfy the enablement requirement. These factors include, but are not limited to:(A) The breadth of the claims; (B) The nature of the invention; (C) The state of the prior art; (D) The level of one of ordinary skill; (E) The level of predictability in the art; (F) The amount of direction provided by the inventor; (G) The existence of working examples; and (H) The quantity of experimentation needed to make or use the invention based on the content of the disclosure. Upon consideration of the aforementioned factors, Applicant’s disclosure does not satisfy the enablement requirement because Applicant’s specification does not disclose enough information for one of ordinary skill in the art to control interrupt processing using a look-up table that comprises common registers and dedicated registers.
The state of the art at the time of filing shows that controlling interrupt processing using a look-up table that comprises common registers and dedicated registers is not predictable. The specification does not provide direction as to how to perform this feature. In fact, the specification states that the look-up table, common registers, and dedicated registers are separate. (Applicant’s Specification, [0009], The microprocessor includes a control device, a look-up table, a common register, and a dedicated register). Taking these factors into account, undue experimentation would be required by one of ordinary skill in the art to practice the full scope of claim 3. Thus, claim 3 is not enabled by the disclosure. Applicant cannot rely on the knowledge of one skilled in the art to supply information that is required to enable the novel aspect of the claimed invention when the enabling knowledge is in fact not known in the art. ALZA Corp. v. Andrx Pharms., LLC, 603 F.3d 935, 941, 94 USPQ2d 1823, 1827 (Fed. Cir. 2010) ("ALZA was required to provide an adequate enabling disclosure in the specification; it cannot simply rely on the knowledge of a person of ordinary skill to serve as a substitute for the missing information in the specification").
Claim 21 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the enablement requirement.
The claims contain subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention. The claims contain subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention. The claimed subject matter for which the specification is not enabling are: “wherein the look-up table is configured to assign an interrupt to a dedicated index, based on the interrupt having a number of execution occurrences during an operation period of the radio frequency integrated circuit that exceed a threshold value.”
There are many factors (“Wands” factors) to be considered when determining whether there is sufficient evidence to support a determination that a disclosure does not satisfy the enablement requirement. These factors include, but are not limited to:(A) The breadth of the claims; (B) The nature of the invention; (C) The state of the prior art; (D) The level of one of ordinary skill; (E) The level of predictability in the art; (F) The amount of direction provided by the inventor; (G) The existence of working examples; and (H) The quantity of experimentation needed to make or use the invention based on the content of the disclosure. Upon consideration of the aforementioned factors, Applicant’s disclosure does not satisfy the enablement requirement because Applicant’s specification does not disclose enough information for one of ordinary skill in the art to provide a look-up table is configured to assign an interrupt to a dedicated index, based on the interrupt having a number of execution occurrences during an operation period of the radio frequency integrated circuit that exceed a threshold value.
The state of the art at the time of filing shows that controlling interrupt processing using a look-up table that is configured to assign an interrupt to a dedicated index, based on the interrupt having a number of execution occurrences during an operation period of the radio frequency integrated circuit that exceed a threshold value is not predictable. The specification does not provide direction as to how to perform this feature. Taking these factors into account, undue experimentation would be required by one of ordinary skill in the art to practice the full scope of claim 3. Thus, claim 3 is not enabled by the disclosure. Applicant cannot rely on the knowledge of one skilled in the art to supply information that is required to enable the novel aspect of the claimed invention when the enabling knowledge is in fact not known in the art. ALZA Corp. v. Andrx Pharms., LLC, 603 F.3d 935, 941, 94 USPQ2d 1823, 1827 (Fed. Cir. 2010) ("ALZA was required to provide an adequate enabling disclosure in the specification; it cannot simply rely on the knowledge of a person of ordinary skill to serve as a substitute for the missing information in the specification").
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 6-14, 16-17, 24, and 26 are rejected under 35 U.S.C. 103 as being unpatentable over Matsuyama (US 20110252221) in view of Hellwig et al. (US 20190050356).
As per claim 1, Matsuyama teaches the invention substantially as claimed including an interrupt processing method, comprising:
executing a first interrupt ([0080], When a new interrupt request is permitted during execution of the interrupt routine 1; Examiner Note: Matsuyama’s interrupt routine 1 is mapped to the first interrupt) by using a common register ([0048], The interrupt controller 1 is provided …. a plurality of interrupt factor register groups 12-0 to 12-(n-1); and [0050], Data determined based on the interrupt signal which is transmitted on each of the interrupt signal lines are set in a corresponding one of the interrupt factor register groups 12-0 to 12-(n-1). That is, the data corresponding to different interrupt factors are set to the plurality of interrupt factor register groups 12-0 to 12-(n-1), respectively);
receiving a second interrupt and a second priority of the second interrupt during execution of the first interrupt ([0080], When a new interrupt request is permitted during execution of the interrupt routine 1, and the highest priority level of the new interrupt request is higher than the service level (priority level) of the interrupt routine 1);
comparing a first priority of the first interrupt with the second priority of the second interrupt ([0054], The priority level determining circuit 11 compares the priority level set in one flag register 121 with the priority level of the current interrupt processing, and controls the processor 2 to execute the processing with the higher priority level; [0080], When a new interrupt request is permitted during execution of the interrupt routine 1, and the highest priority level of the new interrupt request is higher than the service level (priority level) of the interrupt routine 1, the new interrupt request is accepted (Steps S201, S202; and [0086], the interrupt controller 1 selects the highest priority level among the priority levels of the interrupt factors with "1" set in the flag registers 121 and determines whether or not the selected priority level is higher than the service level (priority level) of the current processing being executed);
generating a first register index corresponding to the second priority of the second interrupt by using a look-up table based on the second priority of the second interrupt being greater than the first priority ([0055], the priority level determining circuit 11 in the present embodiment outputs a register pattern number from the pattern number register 123 of the selected interrupt factor to the processor 2); and
based on the first register index being a dedicated index ([0022], instruction executing section is configured to execute the microinstruction prior to the fetched instruction code, to save the data of registers designated based on the acquired register pattern in the data memory; and [0052], the register pattern is data designating the registers, data of which are to be saved, i.e., data-saved registers, when the interrupt factor has occurred. The register pattern is set in a register list), maintaining a context of the first interrupt stored in the common register ([0052], the register pattern is data designating the registers, data of which are to be saved, i.e., data-saved registers, when the interrupt factor has occurred. The register pattern is set in a register list; and [0083], a context of the data-saved registers (i.e. register data) corresponding to the interrupt factor are saved in response to each of interrupt requests), assigning a dedicated register for execution of the second interrupt ([0022], instruction executing section is configured to execute the microinstruction prior to the fetched instruction code, to save the data of registers designated based on the acquired register pattern in the data memory; [0052], the register pattern is data designating the registers, data of which are to be saved, i.e., data-saved registers, when the interrupt factor has occurred. The register pattern is set in a register list; [0064], The register data saving control circuit 25 is provided with a RAM (not shown) for storing a micro program of microinstructions for controlling register data saving processing and outputs the microinstructions containing the register pattern to the instruction executing section 23, thereby controlling the instruction executing section 23 to execute the register data saving processing based on the microinstructions; [0066], the processor 2 accepts an interrupt request in an interrupt permission state and saves the data of registers into the data memory 4 based on the extracted register pattern; and [0080], processor 2 saves the register data uniquely into the data memory 4 in response to the accepted interrupt request), and executing an interrupt program corresponding to the second interrupt by using the assigned dedicated register ([0004], when an interrupt with a higher priority level than an instruction being executed is generated, the instruction being executed is interrupted and an interrupt sequence is executed; and [0054], priority level determining circuit 11 compares the priority level set in one flag register 121 with the priority level of the current interrupt processing, and controls the processor 2 to execute the processing with the higher priority level. Here, the priority level determining circuit 11 refers to the plurality of interrupt factor register groups 12-0 to 12-(n-1) to select the interrupt factor with the highest priority level among the priority levels set in the priority level registers 122, and compares the highest priority level with the priority level set to the ISPR register 13).
Matsuyama fails to specifically teach, the interrupt program being saved in a memory. However, it would have been obvious to one of ordinary skill in the art to include this step because Matsuyama teaches performing interrupt processing with register stored data. ([0009], When starting the interrupt processing, the instruction executing section 203 saves data of the register file 204 in the data memory 400 (for example, a stack memory). Specifically, the instruction executing section 203 first saves data of the PC and the PSW into the data memory 400 and then, saves data of general purpose registers R0 to R31 into the data memory 400. When saving of the data of register file 204 is completed, the instruction executing section 203 executes processing corresponding to the interrupt request; and [0060], The instruction executing section 23 executes the instruction code fetched by the instruction fetch control circuit 22 and microinstructions obtained from the register data saving control circuit 25).
Furthermore, Hellwig teaches, the interrupt program being saved in a memory ([0100], interrupt control register (ICR) configuration control (ICR CTRL) that comprises a plurality of responses to various interrupt conditions related to the VMM/hypervisor and the plurality of VMs; and [0113], determining a current status of interrupt priority schemes corresponding to the VMM/hypervisor and the plurality of VMs based on information from a central processing unit (CPU) interrupt control registers (ICUs) ).
Matsuyama and Hellwig are analogous because they are both related to interrupt processing. Matsuyama teaches an interrupt processing method including a register allocation scheme to process interrupts based on priority. ([0023], an interrupt control method is achieved by setting a plurality of register patterns in a plurality of register lists, respectively, wherein each of plurality of register patterns designates registers, data of which are to be saved in a data memory; by fetching instruction code from an instruction memory by an instruction fetch control circuit in response to an interrupt request issued based on occurrence of an interrupt factor; by acquiring one register pattern from one of the plurality of register lists by a register data saving control circuit in response to the interrupt request; by issuing a microinstruction based on the acquired register pattern by the register data saving control circuit in response to the interrupt request; and by executing the microinstruction prior to the fetched instruction code by an instruction executing section, to save the data of registers designated based on the acquired register pattern in the data memory; and [0024], according to the present invention, the amount of data saved in the interrupt processing can be reduced. Further, the interrupt processing time can be shortened. Furthermore, the time taken from reception of interrupt to start of saving of the context can be shortened). Hellwig teaches a method of prioritized interrupt processing where interrupt programs are stored in memory. ([0045], the ICU 202 can add priority information to an interrupt to provide an interrupt with an interrupt priority and arbitrate among all other pending interrupts for the CPU, and further send other information such as the interrupt size to the CPU 204; [0100], interrupt control register (ICR) configuration control (ICR CTRL) that comprises a plurality of responses to various interrupt conditions related to the VMM/hypervisor and the plurality of VMs; and [0113], determining a current status of interrupt priority schemes corresponding to the VMM/hypervisor and the plurality of VMs based on information from a central processing unit (CPU) interrupt control registers (ICUs) ). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention that based on the combination, the teachings of Matsuyama would be modified with the interrupt program storing mechanism taught by Hellwig resulting in a system performs prioritized interrupt processing using register allocation. Therefore, it would have been obvious to combine the teachings of Matsuyama and Hellwig.
As per claim 2, Matsuyama teaches, further comprising:
receiving a third interrupt and a third priority of the third interrupt during the execution of the first interrupt ([0051], a 1-bit interrupt factor flag indicating occurrence of the interrupt factor is set to the flag register 121. When the interrupt factor has occurred, the interrupt factor flag of "1" is set to the flag register 121… A priority level assigned to the interrupt factor is set to the priority level register 122; and [0054], a bit position from the bottom correspond to one of priority levels "0", "2", and "3", and data "1" is set in the bit position corresponding to the priority level of the interrupt processing);
comparing the first priority of the first interrupt with the third priority of the third interrupt ([0054], The priority level determining circuit 11 compares the priority level set in one flag register 121 with the priority level of the current interrupt processing, and controls the processor 2 to execute the processing with the higher priority level; [0080], When a new interrupt request is permitted during execution of the interrupt routine 1, and the highest priority level of the new interrupt request is higher than the service level (priority level) of the interrupt routine 1, the new interrupt request is accepted (Steps S201, S202; and [0086], the interrupt controller 1 selects the highest priority level among the priority levels of the interrupt factors with "1" set in the flag registers 121 and determines whether or not the selected priority level is higher than the service level (priority level) of the current processing being executed);
generating a second register index corresponding to the third priority of the third interrupt by using the look-up table based on the third priority of the third interrupt being greater than the first priority([0051], when any of four priority levels is set, the 2-bit priority level register 122 is provided in each of the plurality of interrupt factor register groups 12-0 to 12-(n-1)); and
based on the second register index being a common index, saving the context of the first interrupt in the memory([0004], when an interrupt with a higher priority level than an instruction being executed is generated, the instruction being executed is interrupted and an interrupt sequence is executed. When interrupt processing is started, the processor temporarily saves in a stack memory, the data of a program status word (PSW) and a program counter (PC) and data of general purpose registers (context); Examiner Note: Data from the common index is stored in the general purpose registers: [0011], the interrupt processing can be executed by use of any general purpose registers; and [0051], when any of four priority levels is set, the 2-bit priority level register 122 is provided in each of the plurality of interrupt factor register groups 12-0 to 12-(n-1)), and executing the interrupt program corresponding to the third interrupt by using the common register ([0004], when an interrupt with a higher priority level than an instruction being executed is generated, the instruction being executed is interrupted and an interrupt sequence is executed. When interrupt processing is started, the processor temporarily saves in a stack memory, the data of a program status word (PSW) and a program counter (PC) and data of general purpose registers (context)).
As per claim 3, Matsuyama teaches, wherein the look-up table comprises a common index (Fig. 4, Register N0; [0073], In the example shown in FIG. 4, the register patterns (1) to (4) are associated with the register pattern numbers PTN "0" to "3", respectively, and set in the register list unit 27) and at least two dedicated indexes (Fig. 4, PTN; and [0073], The register pattern can be uniquely identified by the register pattern number PTN), and wherein the interrupt processing method further comprises:
assigning the common index to at least two interrupt priorities ([0051], when any of four priority levels is set, the 2-bit priority level register 122 is provided in each of the plurality of interrupt factor register groups 12-0 to 12-(n-1)), and
assigning each dedicated index of the at least two dedicated indexes to a distinct interrupt priority ([0051], A priority level assigned to the interrupt factor is set to the priority level register 122).
As per claim 6, Matsuyama teaches, further comprising:
receiving an identifier of the second interrupt ([0104], the register data saving control circuit 25 extracts the register pattern from the register list unit 27 based on the pattern number INTPTN of "1H" (PTN1) set in the pattern number register 250); and
obtaining, by using a trap vector table, an address of the memory in which the interrupt program corresponding to the second interrupt is saved by using the identifier of the second interrupt ([0105], When ending saving of the data of registers of the designated register pattern, the instruction executing section 23 executes the fetched EI instruction (interrupt permission instruction) at a clock C13. Subsequently, instruction code is fetched from an address of the interrupt handler designated by the interrupt vector "2F0H" and the interrupt handler is executed by the instruction executing section 23).
As per claim 7, Matsuyama teaches, wherein each of the common register and the dedicated register comprise a special purpose register ([0051], the 2-bit priority level register 122 is provided in each of the plurality of interrupt factor register groups 12-0 to 12-(n-1)) and a general purpose register ( [0011], interrupt processing can be executed by use of any general purpose registers) and wherein the interrupt processing method further comprises:
saving first operation values of the execution of the first interrupt in the general purpose register of the common register ([0054], A service level (priority level) of current interrupt processing is set in an ISPR register 13); and
saving second operation values of the execution of the second interrupt in the general purpose register of the dedicated register ([0010], When ending the interrupt processing, the instruction executing section 203 returns the data saved into the data memory 400 into the register file 204 in response to a return instruction).
As per claim 8, Matsuyama teaches, further comprising:
continuing the execution of the first interrupt based on the second priority of the second interrupt being less than the first priority of the first interrupt ([0056], when all the priority levels of the interrupt factors with the flags set to "1" are equal to or lower than the priority level of the current interrupt processing, the priority level determining circuit 11 waits for outputting of the interrupt vector INTVCT corresponding to the interrupt factor).
As per claim 9, Marsuyama teaches, further comprising:
finishing execution of the interrupt program of the third interrupt by using a special purpose register ([0048], interrupt controller 1 is provided … an ISPR register 13; [0054], A service level (priority level) of current interrupt processing is set in an ISPR register 13; and [0057], In response to an interrupt acceptance notice INTACK from the processor 2, the control circuit 14 sets the service level (priority level) of the interrupt processing to be executed by the processor 2 to the ISPR register 13. In response to an interrupt processing end notice INTFIN from the processor 2, the control circuit 14 resets the flag register 121 corresponding to the completed interrupt processing to "0") and a general purpose register of the common register ([0048], interrupt controller 1 is provided with … a plurality of interrupt factor register groups 12-0 to 12-(n-1); and ([0050], The plurality of interrupt signal lines INT0 to INTn-1 are assigned to different interrupt factors, respectively, and interrupt signals are transmitted on the lines, respectively. Data determined based on the interrupt signal which is transmitted on each of the interrupt signal lines are set in a corresponding one of the interrupt factor register groups 12-0 to 12-(n-1). That is, the data corresponding to different interrupt factors are set to the plurality of interrupt factor register groups 12-0 to 12-(n-1), respectively);
restoring the context of the first interrupt saved in the memory to the special purpose register and the general purpose register of the common register ([0004], After completion of the interrupt processing, the saved context can be returned to the PSW, the PC and the general purpose registers so as to restart the interrupted processing); and
resuming the execution of the first interrupt ([0004], After completion of the interrupt processing, the saved context can be returned to the PSW, the PC and the general purpose registers so as to restart the interrupted processing; [0011], When ending the interrupt processing, the instruction executing section 203 returns the data saved into the data memory 400 into the register file 204 in response to a return instruction, and restarts the interrupted processing; and [0081], the interrupt routine 2 ended, the processor 2 executes a return instruction (RET instruction) of the interrupt handler (Steps S301, S302). Here, the data saved into the data memory 4 at Step S202 are returned to the register file 24 and the suspended interrupt routine 1 is restarted).
As per claim 10, Matsuyama teaches, further comprising:
finishing execution of the interrupt program of the second interrupt by using the special purpose register ([0048], interrupt controller 1 is provided … an ISPR register 13; [0054], A service level (priority level) of current interrupt processing is set in an ISPR register 13; and [0057], In response to an interrupt acceptance notice INTACK from the processor 2, the control circuit 14 sets the service level (priority level) of the interrupt processing to be executed by the processor 2 to the ISPR register 13. In response to an interrupt processing end notice INTFIN from the processor 2, the control circuit 14 resets the flag register 121 corresponding to the completed interrupt processing to "0") and the general purpose register of the dedicated register ([0004], After completion of the interrupt processing, the saved context can be returned to the PSW, the PC and the general purpose registers so as to restart the interrupted processing); and
resuming the execution of the first interrupt by using the context saved in the common register ([0004], After completion of the interrupt processing, the saved context can be returned to the PSW, the PC and the general purpose registers so as to restart the interrupted processing; and [0011], When ending the interrupt processing, the instruction executing section 203 returns the data saved into the data memory 400 into the register file 204 in response to a return instruction, and restarts the interrupted processing).
As per claim 11, Hellwig teaches, wherein the receiving of the second interrupt during the execution of the first interrupt comprises receiving a command from an outside through an inter-chip interface ([0043], the ICU 202 can obtain the interrupts from on-chip resources, or external resources).
As per claim 12, Matsuyama teaches, an interrupt processing device ([0002], microcomputer for performing interrupt processing and an interrupt control method of a microcomputer), comprising:
an interrupt controller configured to receive interrupts ([0006], microcomputer according to the conventional example includes an interrupt controller 100) and to output an interrupt to be executed according to a priority ([0004], when an interrupt with a higher priority level than an instruction being executed is generated, the instruction being executed is interrupted and an interrupt sequence is executed), an identifier (ID) of the interrupt to be executed ([0044], designates registers based on an identifier set for every interrupt factor), and the priority of the interrupt to be executed ([0004], when an interrupt with a higher priority level than an instruction being executed is generated, the instruction being executed is interrupted and an interrupt sequence is executed);
a microprocessor ([0004], In a processer of the microcomputer, when an interrupt with a higher priority level than an instruction being executed is generated, the instruction being executed is interrupted and an interrupt sequence is executed; and [0006], microcomputer according to the conventional example includes an interrupt controller 100, a processor 200, an instruction memory 300 and a data memory 400) configured to receive, from the interrupt controller, the interrupt to be executed, the priority of the interrupt, and the ID of the interrupt to be executed ([0006], According to an inputted interrupt signal, the interrupt controller 100 sends an interrupt vector INTVCT and an interrupt request INTREQ to the processor 200. At this time, the interrupt controller 100 refers to a priority level PR set for every interrupt signal and outputs the interrupt vector IVCT with a higher priority level PR to the processor 200), and to execute an interrupt program from among the plurality of interrupt programs corresponding to the interrupt to be executed ([0007], When the interrupt request INTREQ is set to "1", the processor 200 reads an instruction corresponding to the interrupt vector INVCT from the instruction memory 300 and executes the instruction),
wherein the microprocessor comprises a control device ([0006], microcomputer according to the conventional example includes an interrupt controller 100, [and] a processor 200), a look-up table ([0157], the register pattern number PTN for each interrupt factor is stored in the pattern number register 123 provided in association with each of the interrupt factors INT0 to INTn-1 and the register pattern number is notified to the processor 2 as INTPTN), a common register ([0048], The interrupt controller 1 is provided …. a plurality of interrupt factor register groups 12-0 to 12-(n-1);), and a dedicated register ([0061], the register data saving control circuit 25, the instruction executing section 23 saves data of a part or whole of the register file 24 into the data memory 4. At this time, the register data saving control circuit 25 designates data-saved registers, from which data should be saved, for the instruction executing section 23 based on a register list selected by the register list selecting circuit 26; [0069], data of seven registers, i.e. the data of the general purpose registers R0 to R4, the EIPC register 243 and the EIPSW register 244 that may be destroyed by an interrupt handler are necessary to be saved, and this register pattern is set in the register list 270 to designate these registers as data-saved register; and [0076], Based on the notified interrupt pattern number INTPTN, the register data saving control circuit 25 can start interrupt acceptance processing, and designates the data-saved registers (register pattern) and perform the register data saving processing),
wherein the control device is configured to compare the priority of the interrupt to be executed with a priority of an interrupt being executed ([0048], The interrupt controller 1 is provided with a priority level determining circuit 11; [0054], The priority level determining circuit 11 compares the priority level set in one flag register 121 with the priority level of the current interrupt processing, and controls the processor 2 to execute the processing with the higher priority level; [0080], When a new interrupt request is permitted during execution of the interrupt routine 1, and the highest priority level of the new interrupt request is higher than the service level (priority level) of the interrupt routine 1, the new interrupt request is accepted (Steps S201, S202; and [0086], the interrupt controller 1 selects the highest priority level among the priority levels of the interrupt factors with "1" set in the flag registers 121 and determines whether or not the selected priority level is higher than the service level (priority level) of the current processing being executed),
wherein the look-up table is configured to generate a register index corresponding to the priority of the interrupt to be executed ([0055], the priority level determining circuit 11 in the present embodiment outputs a register pattern number from the pattern number register 123 of the selected interrupt factor to the processor 2) based on a comparison result indicating that the priority of the interrupt to be executed is greater than the priority of the interrupt being executed ([0054], The priority level determining circuit 11 compares the priority level set in one flag register 121 with the priority level of the current interrupt processing, and controls the processor 2 to execute the processing with the higher priority level; and [0080], When a new interrupt request is permitted during execution of the interrupt routine 1, and the highest priority level of the new interrupt request is higher than the service level (priority level) of the interrupt routine 1, the new interrupt request is accepted (Steps S201, S202). Here, since the priority level "0" of the new interrupt request is higher than the priority level "1" of the interrupt routine 1 being executed, the processor 2 accepts the new interrupt request, branches to the interrupt handler and executes an interrupt routine 2), and
wherein the microprocessor is further configured to:
based on the register index being a common index, save, in the memory, a context of the interrupt being executed that is saved in the common register ([0004], When interrupt processing is started, the processor temporarily saves in a stack memory, the data of a program status word (PSW) and a program counter (PC) and data of general purpose registers (context)), and execute the interrupt program corresponding to the interrupt to be executed by using the common register ([0004], when an interrupt with a higher priority level than an instruction being executed is generated, the instruction being executed is interrupted and an interrupt sequence is executed); and
based on the register index being a dedicated index, maintain the context of the interrupt being executed that is saved in the common register ([0009], saves data of general purpose registers R0 to R31 into the data memory 400. When saving of the data of register file 204 is completed, the instruction executing section 203 executes processing corresponding to the interrupt request; and [0083], in the multiple interrupt processing, a context of the data-saved registers (i.e. register data) corresponding to the interrupt factor are saved in response to each of interrupt requests), assign the dedicated register for execution of the interrupt to be executed ([0061], the register data saving control circuit 25, the instruction executing section 23 saves data of a part or whole of the register file 24 into the data memory 4. At this time, the register data saving control circuit 25 designates data-saved registers, from which data should be saved, for the instruction executing section 23 based on a register list selected by the register list selecting circuit 26; [0069], data of seven registers, i.e. the data of the general purpose registers R0 to R4, the EIPC register 243 and the EIPSW register 244 that may be destroyed by an interrupt handler are necessary to be saved, and this register pattern is set in the register list 270 to designate these registers as data-saved register; and [0076], Based on the notified interrupt pattern number INTPTN, the register data saving control circuit 25 can start interrupt acceptance processing, and designates the data-saved registers (register pattern) and perform the register data saving processing), and execute the interrupt program corresponding to the interrupt to be executed by using the assigned dedicated register ([0062], the instruction executing section 23 executes the instruction code fetched by the instruction fetch control circuit 22 for the interrupt processing).
Matsuyama fails to specifically teach, a memory storing a plurality of interrupt programs. However, it would have been obvious to one of ordinary skill in the art to include this step because Matsuyama teaches performing interrupt processing with register stored data. ([0009], When starting the interrupt processing, the instruction executing section 203 saves data of the register file 204 in the data memory 400 (for example, a stack memory). Specifically, the instruction executing section 203 first saves data of the PC and the PSW into the data memory 400 and then, saves data of general purpose registers R0 to R31 into the data memory 400. When saving of the data of register file 204 is completed, the instruction executing section 203 executes processing corresponding to the interrupt request; and [0060], The instruction executing section 23 executes the instruction code fetched by the instruction fetch control circuit 22 and microinstructions obtained from the register data saving control circuit 25).
Furthermore, Hellwig teaches, a memory storing a plurality of interrupt programs ([0100], interrupt control register (ICR) configuration control (ICR CTRL) that comprises a plurality of responses to various interrupt conditions related to the VMM/hypervisor and the plurality of VMs; and [0113], determining a current status of interrupt priority schemes corresponding to the VMM/hypervisor and the plurality of VMs based on information from a central processing unit (CPU) interrupt control registers (ICUs) ).
The same motivation used in the rejection of claim 1 is applicable to the instant claim.
As per claim 13, Matsuyama teaches, wherein the look-up table comprises the common index (Fig. 4, Register N0; [0073], In the example shown in FIG. 4, the register patterns (1) to (4) are associated with the register pattern numbers PTN "0" to "3", respectively, and set in the register list unit 27) and at least two dedicated indexes (Fig. 4, PTN; and [0073], The register pattern can be uniquely identified by the register pattern number PTN).
As per claim 14, Matsuyama teaches, wherein at least two interrupt priorities are assigned to the common index ([0051], when any of four priority levels is set, the 2-bit priority level register 122 is provided in each of the plurality of interrupt factor register groups 12-0 to 12-(n-1)), and a distinct interrupt priority is assigned to each of the at least two dedicated indexes ([0051], A priority level assigned to the interrupt factor is set to the priority level register 122).
As per claim 16, Marsuyama teaches, wherein each of the common register and the dedicated register comprises a special purpose register ([0008], the processor 200 includes an … the register file 204; and [0022], a microcomputer includes: a plurality of register lists having a plurality of register patterns, respectively, wherein each of plurality of register patterns designates registers, data of which are to be saved in a data memory) and a general purpose register ([0011], the interrupt processing can be executed by use of any general purpose registers), wherein the special purpose register comprises a program counter and a status register ([0065], the register file 24 includes a program counter (PC) register 241 that stores a program counter (PC), a PWS register 242 that stores a program status word (PSW), an EIPC register 243 for storing the PC in the interrupt processing, an EIPSW register 244 for storing the PSW in the interrupt processing, and a plurality of general purpose registers 240 (for example, 32-bit general purpose registers R0 to R31))), and wherein the general purpose register comprises registers configured to save operation values of execution of the first interrupt or the second interrupt ([0009], When starting the interrupt processing, the instruction executing section 203 saves data of the register file 204 in the data memory 400 (for example, a stack memory). Specifically, the instruction executing section 203 first saves data of the PC and the PSW into the data memory 400 and then, saves data of general purpose registers R0 to R31 into the data memory 400. When saving of the data of register file 204 is completed, the instruction executing section 203 executes processing corresponding to the interrupt request; and [0065], The register file 24 includes …a plurality of general purpose registers 240 (for example, 32-bit general purpose registers R0 to R31)).
As per claim 17, Matsuyama teaches, wherein a number of dedicated registers is greater than a number of common registers ([0011], the interrupt processing can be executed by use of any general purpose registers; and [0014], the registers to be saved for the interrupt processing are determined. Thereby, the registers to be saved for the interrupt processing can be changed for each user program).
As per claim 24, Hellwig teaches the invention substantially as claimed including a interrupt processing method to be performed by a processor ([0038], components of the network device/system 100 or associated interrupt interface can be implemented in one physical node or separate physical nodes including components or functions to read and execute instructions from a machine-readable or computer-readable medium (e.g., a non-transitory machine-readable storage medium)), comprising:
receiving a second interrupt assigned to a common register, during execution of a first interrupt using the common register ([0041], A single hardware CPU 202 can map interrupts with a priority that can up to about 255 as a highest/lowest priority from zero on the opposite end of the scale, which can further be encompassed or communicated via a priority vector 220 (e.g., an 8-bit priority vector) with the priority of interrupts to the CPU 204 via one or more interrupt interface bus 208; [0042], receiving the vector 220; [0043], an interrupt is being received as a service request to trigger an interrupt service routine, for example, or other interrupt process when a resource such as a VM, VMM, processing array or component is busy or in execution of another task; and [0060], The ICR registers 420, 424, 428, and 432 are configured to indicate (e.g., via the bus 150, or the like), a current task priority, a pending interrupt priority, and an interrupt enable status), a second priority of the second interrupt having being higher that a first priority of the first interrupt ([0087], a VMx task can be interrupted by any interrupt mapped to the VMx with a ICR_ VMx.PIPN > ICR _VMx.CCPN); and
saving a context of the first interrupt in a memory ([0078], The dedicated previous context information registers (PCXI) can be configured per VMx 512.sub.1-512.sub.n, and the VMM 410, as also referred to as a previous context Register (PCXR). The PCXI registers 422, 426, 430, and 434, for example, includes information about the previous/interrupted task of the VMx 412-416/VMM 410, respectively).
Hellwig fails to specifically teach, executing a first interrupt program corresponding to the second interrupt using the common register; receiving a fourth interrupt assigned to a dedicated register, during execution of a third interrupt using the common register, a fourth priority of the fourth interrupt being higher than a third priority of the third interrupt; and executing a second interrupt program corresponding to the fourth interrupt using the dedicated register, while maintaining a context of the third interrupt in the common register.
However, Matsuyama teaches, executing a first interrupt program corresponding to the second interrupt using the common register ([0004], when an interrupt with a higher priority level than an instruction being executed is generated, the instruction being executed is interrupted and an interrupt sequence is executed. When interrupt processing is started, the processor temporarily saves in a stack memory, the data of a program status word (PSW) and a program counter (PC) and data of general purpose registers (context));
receiving a fourth interrupt assigned to a dedicated register, during execution of a third interrupt using the common register, a fourth priority of the fourth interrupt being higher than a third priority of the third interrupt ([0080], When a new interrupt request is permitted during execution of the interrupt routine 1, and the highest priority level of the new interrupt request is higher than the service level (priority level) of the interrupt routine 1); and
executing a second interrupt program corresponding to the fourth interrupt using the dedicated register ([0062], the instruction executing section 23 executes the instruction code fetched by the instruction fetch control circuit 22 for the interrupt processing), while maintaining a context of the third interrupt in the common register ([0052], the register pattern is data designating the registers, data of which are to be saved, i.e., data-saved registers, when the interrupt factor has occurred. The register pattern is set in a register list; and [0083], a context of the data-saved registers (i.e. register data) corresponding to the interrupt factor are saved in response to each of interrupt requests).
The same motivation used in the rejection of claim 1 is applicable to the instant claim.
As per claim 26, Matsuyama teaches, wherein each of the common register and the dedicated register comprise a special purpose register ([0051], the 2-bit priority level register 122 is provided in each of the plurality of interrupt factor register groups 12-0 to 12-(n-1)) and a general purpose register ([0011], interrupt processing can be executed by use of any general purpose registers), and
wherein the interrupt processing method further comprises:
saving first operation values of the execution of the first interrupt in the general purpose register of the common register ([0054], A service level (priority level) of current interrupt processing is set in an ISPR register 13); and
saving second operation values of the execution of the second interrupt in the general purpose register of the dedicated register ([0010], When ending the interrupt processing, the instruction executing section 203 returns the data saved into the data memory 400 into the register file 204 in response to a return instruction)..
Claims 4-5, 15, and 25 are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Matsuyama-Hellwig as applied to independent claims 1, 12, and 24 and in further view of Tamaru et al. (US 4788639).
As per claim 4, Matsuyama teaches, further comprising:
determining a first plurality of interrupts corresponding to the at least two interrupt priorities assigned to the common index ([0049], Each of the plurality of interrupt factor register groups 12-0 to 12-(n-1) is provided with a flag register 121, a priority level (PR) register 122 and a pattern number register (PTN register) 123; [0050], Data determined based on the interrupt signal which is transmitted on each of the interrupt signal lines are set in a corresponding one of the interrupt factor register groups 12-0 to 12-(n-1). That is, the data corresponding to different interrupt factors are set to the plurality of interrupt factor register groups 12-0 to 12-(n-1), respectively; and [0051], A priority level assigned to the interrupt factor is set to the priority level register 122. The priority level register 122 is a register having a bit size for the number of priority levels. For example, when any of four priority levels is set, the 2-bit priority level register 122 is provided in each of the plurality of interrupt factor register groups 12-0 to 12-(n-1)); and
determining a second plurality of interrupts corresponding to the distinct interrupt priorities assigned to the at least two dedicated indexes ([0049], Each of the plurality of interrupt factor register groups 12-0 to 12-(n-1) is provided with a flag register 121, a priority level (PR) register 122 and a pattern number register (PTN register) 123; [0050], Data determined based on the interrupt signal which is transmitted on each of the interrupt signal lines are set in a corresponding one of the interrupt factor register groups 12-0 to 12-(n-1). That is, the data corresponding to different interrupt factors are set to the plurality of interrupt factor register groups 12-0 to 12-(n-1), respectively; and [0051], A priority level assigned to the interrupt factor is set to the priority level register 122. The priority level register 122 is a register having a bit size for the number of priority levels. For example, when any of four priority levels is set, the 2-bit priority level register 122 is provided in each of the plurality of interrupt factor register groups 12-0 to 12-(n-1)).
Matsuyama fails to specifically teach, further comprising: determining a first plurality of interrupts corresponding to the at least two interrupt priorities assigned to the common index, based on first execution frequencies of the first plurality of interrupts; and determining a second plurality of interrupts corresponding to the distinct interrupt priorities assigned to the at least two dedicated indexes, based on second execution frequencies of the second plurality of interrupts.
However, Tamaru teaches, further comprising:
determining a first plurality of interrupts corresponding to the at least two interrupt priorities assigned to the common index, based on first execution frequencies of the first plurality of interrupts (Abstract, the host computer determines a priority of the interrupt from the frequency of the signal and then executes a corresponding interrupt routine); and
determining a second plurality of interrupts corresponding to the distinct interrupt priorities assigned to the at least two dedicated indexes, based on second execution frequencies of the second plurality of interrupts (Abstract, the host computer determines a priority of the interrupt from the frequency of the signal and then executes a corresponding interrupt routine).
The combination of Matsuyama-Hellwig and Tamaru are analogous because they are each related to interrupt processing. Matsuyama teaches an interrupt processing method including a register allocation scheme to process interrupts based on priority. Hellwig teaches a method of prioritized interrupt processing where interrupt programs are stored in memory. Tamaru teaches a method of prioritized interrupt processing based on a frequency associated with an interrupt. (Abstract, each input/output control device outputs an interrupt signal of a frequency determined by a level of an interrupt to be sent to the host computer. The interrupt signal is supplied from one external terminal of the input/output control device. Upon receipt of the interrupt signals, the host computer determines a priority of the interrupt from the frequency of the signal and then executes a corresponding interrupt routine). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention that based on the combination, the teachings of the combination of Matsuyama-Hellwing and Tamaru would be modified with the frequency-based prioritization mechanism taught by Tamaru resulting in a system performs prioritized interrupt processing using interrupt frequencies. Therefore, it would have been obvious to combine the teachings of the combination of Matsuyama-Hellwig and Tamaru.
As per claim 5, Tamaru teaches, wherein the first execution frequencies of the first plurality of interrupts are smaller than the second execution frequencies of the second plurality of interrupts (Column 1, Lines 60-61, frequency which is different for each of said interrupt level).
As per claim 15, Matsuyama fails to specifically wherein a first execution frequency of a first interrupt assigned to the common index is less than a second execution frequency of a second interrupt assigned to a dedicated index of the at least two dedicated indexes.
However, Tamaru teaches, wherein a first execution frequency of a first interrupt assigned to the common index is less than a second execution frequency of a second interrupt assigned to a dedicated index of the at least two dedicated indexes (Column 1, Lines 60-61, frequency which is different for each of said interrupt level).
The same motivation used in the rejection of claim 4 is applicable to the instant claim.
As per claim 25, Matsuyama teaches, determining a register to which each of the plurality of interrupts is to be assigned based on the execution frequency ([0014], by providing a register usage identifier for identifying a register group used by a user program and designating saved registers based on the register usage identifier, the registers to be saved for the interrupt processing are determined).
The combination of Hellwig-Masuyama fails to specifically teach, further comprising: monitoring an execution frequency of each interrupt of a plurality of interrupts, the plurality of interrupts comprising the first interrupt, the second interrupt, the third interrupt, and the fourth interrupt.
However, Tamaru teaches, further comprising:
monitoring an execution frequency of each interrupt of a plurality of interrupts (Column 5, Lines 57-63, Every time the voltage level of interrupt signal INT1 changes from H level to L level, the output of inverter circuit 71 clears the contents of counter 55. The contents of counter 55 immediately before the counter is cleared is latched into counter output holding circuit 59. In this way, the interrupt level specified by the frequency of the interrupt signal INT1 is determined), the plurality of interrupts comprising the first interrupt, the second interrupt, the third interrupt, and the fourth interrupt (Column 4, Lines 17-21, PU 111 outputs the interrupt requests of four different levels. For example, when CPU 111 is controlling a LAN, it produces different levels of interrupts according to the cases).
The same motivation used in the rejection of claim 4 is applicable to the instant claim.
Claims 18-23 are rejected under 35 U.S.C. 103 as being unpatentable over Hellwig et al. (US 20190050356) in view of Matsuyama (US 20110252221) and Agarwal (US 20070198759).
As per claim 18, Hellwig teaches the invention substantially as claimed including a radio frequency integrated circuit ([0023], processors 110 (e.g… a radio-frequency integrated circuit (RFIC), another processor, or any suitable combination thereof)), comprising:
an intellectual property (IP) transceiver unit comprising a plurality of functional blocks ([0044], ICU 202 can send a single signal 220 to provide CPUx 204, which conveys information about an application or other component wants the CPU 204 to process by starting an interrupt service routine (ISR); NAD [0045], the ICU 202 can operate as processing/processor device integrated with/as part of the CPU 204 with a hypervisor or VMM support);
a latch unit comprising special function registers storing operation mode setting values of the plurality of functional blocks ([0049], CPU 302 and CPU 310 comprises a CPU Internet control register (CPU ICR) 306 that includes information sent from the ICU 202, for example, to the CPU 302, 310, or by an internal CPU component such as a VMM, VM or other component. CPU 302 and CPU 310 can also be/part of/coupled with the processor 110 or any one processor 112, 114 unit therein, for example. The information sent or received can include: a current task priority that is a priority of the CPU software of execution, the latest interrupt priority sent by the ICU 202 to the CPU 302, 304, and an additional control bit that indicates whether the CPU is now enabled to be interrupted by a new interrupt with a priority above the task/sub-task priority or that satisfies a defined threshold); and
an interrupt processor configured to receive a command from a master through an inter-chip interface, to process an interrupt ([0021], system 100 including one or more processors (or processor cores) 110, one or more memory/storage devices 120; and [0041], A single hardware CPU 202 can map interrupts with a priority that can up to about 255 as a highest/lowest priority from zero on the opposite end of the scale, which can further be encompassed or communicated via a priority vector 220 (e.g., an 8-bit priority vector) with the priority of interrupts to the CPU 204 via one or more interrupt interface bus 208), and to generate the operation mode setting values ([0049], The information sent or received can include: a current task priority that is a priority of the CPU software of execution, the latest interrupt priority sent by the ICU 202 to the CPU 302, 304, and an additional control bit that indicates whether the CPU is now enabled to be interrupted by a new interrupt with a priority above the task/sub-task priority or that satisfies a defined threshold).
Hellwig fails to specifically teach, wherein the interrupt processor comprises an interrupt controller, wherein the interrupt controller is configured to output an interrupt, an identifier (ID) of the interrupt, and a priority corresponding to the received command, wherein the microprocessor comprises a look-up table, a common register, and a dedicated register, wherein the look-up table is configured to assign at least one of the common register and the dedicated register to processing of the received interrupt according to the priority of the received interrupt, and wherein the microprocessor is further configured to: based on the common register being assigned, save a context in the memory, and execute a program corresponding to the received interrupt; and based on the dedicated register being assigned, execute the program corresponding to the received interrupt without switching the context.
However, Matsuyama teaches, wherein the interrupt processor comprises an interrupt controller ([0006], microcomputer according to the conventional example includes an interrupt controller 100), a microprocessor ([0004], In a processer of the microcomputer, when an interrupt with a higher priority level than an instruction being executed is generated, the instruction being executed is interrupted and an interrupt sequence is executed; and [0006], microcomputer according to the conventional example includes an interrupt controller 100, a processor 200, an instruction memory 300 and a data memory 400), and a memory ([0006], microcomputer according to the conventional example includes … an instruction memory 300 and a data memory 400),
wherein the interrupt controller is configured to output an interrupt, an identifier (ID) of the interrupt ([0104], the register data saving control circuit 25 extracts the register pattern from the register list unit 27 based on the pattern number INTPTN of "1H" (PTN1) set in the pattern number register 250), and a priority corresponding to the received command ([0051], a 1-bit interrupt factor flag indicating occurrence of the interrupt factor is set to the flag register 121. When the interrupt factor has occurred, the interrupt factor flag of "1" is set to the flag register 121… A priority level assigned to the interrupt factor is set to the priority level register 122; and [0054], a bit position from the bottom correspond to one of priority levels "0", "2", and "3", and data "1" is set in the bit position corresponding to the priority level of the interrupt processing),
wherein the microprocessor comprises a look-up table ([0157], the register pattern number PTN for each interrupt factor is stored in the pattern number register 123 provided in association with each of the interrupt factors INT0 to INTn-1 and the register pattern number is notified to the processor 2 as INTPTN), a common register ([0048], The interrupt controller 1 is provided …. a plurality of interrupt factor register groups 12-0 to 12-(n-1);), and a dedicated register ([0061], the register data saving control circuit 25, the instruction executing section 23 saves data of a part or whole of the register file 24 into the data memory 4. At this time, the register data saving control circuit 25 designates data-saved registers, from which data should be saved, for the instruction executing section 23 based on a register list selected by the register list selecting circuit 26; [0069], data of seven registers, i.e. the data of the general purpose registers R0 to R4, the EIPC register 243 and the EIPSW register 244 that may be destroyed by an interrupt handler are necessary to be saved, and this register pattern is set in the register list 270 to designate these registers as data-saved register; and [0076], Based on the notified interrupt pattern number INTPTN, the register data saving control circuit 25 can start interrupt acceptance processing, and designates the data-saved registers (register pattern) and perform the register data saving processing),wherein the look-up table is configured to assign at least one of the common register and the dedicated register to processing of the received interrupt according to the priority of the received interrupt), and
wherein the microprocessor is further configured to:
based on the common register being assigned, save a context in the memory ([0004], When interrupt processing is started, the processor temporarily saves in a stack memory, the data of a program status word (PSW) and a program counter (PC) and data of general purpose registers (context)), and execute a program corresponding to the received interrupt ([0004], when an interrupt with a higher priority level than an instruction being executed is generated, the instruction being executed is interrupted and an interrupt sequence is executed); and
based on the dedicated register being assigned, execute the program corresponding to the received interrupt [without switching the context] ([0061], the register data saving control circuit 25, the instruction executing section 23 saves data of a part or whole of the register file 24 into the data memory 4. At this time, the register data saving control circuit 25 designates data-saved registers, from which data should be saved, for the instruction executing section 23 based on a register list selected by the register list selecting circuit 26; [0069], data of seven registers, i.e. the data of the general purpose registers R0 to R4, the EIPC register 243 and the EIPSW register 244 that may be destroyed by an interrupt handler are necessary to be saved, and this register pattern is set in the register list 270 to designate these registers as data-saved register ; AND [0062], the instruction executing section 23 executes the instruction code fetched by the instruction fetch control circuit 22 for the interrupt processing).
Hellwig and Matsuyama are analogous because they are both related to interrupt processing. Hellwig teaches a method of prioritized interrupt processing where interrupt programs are stored in memory. ([0045], the ICU 202 can add priority information to an interrupt to provide an interrupt with an interrupt priority and arbitrate among all other pending interrupts for the CPU, and further send other information such as the interrupt size to the CPU 204; [0100], interrupt control register (ICR) configuration control (ICR CTRL) that comprises a plurality of responses to various interrupt conditions related to the VMM/hypervisor and the plurality of VMs; and [0113], determining a current status of interrupt priority schemes corresponding to the VMM/hypervisor and the plurality of VMs based on information from a central processing unit (CPU) interrupt control registers (ICUs) ). Matsuyama teaches an interrupt processing method including a register allocation scheme to process interrupts based on priority. ([0023], an interrupt control method is achieved by setting a plurality of register patterns in a plurality of register lists, respectively, wherein each of plurality of register patterns designates registers, data of which are to be saved in a data memory; by fetching instruction code from an instruction memory by an instruction fetch control circuit in response to an interrupt request issued based on occurrence of an interrupt factor; by acquiring one register pattern from one of the plurality of register lists by a register data saving control circuit in response to the interrupt request; by issuing a microinstruction based on the acquired register pattern by the register data saving control circuit in response to the interrupt request; and by executing the microinstruction prior to the fetched instruction code by an instruction executing section, to save the data of registers designated based on the acquired register pattern in the data memory; and [0024], according to the present invention, the amount of data saved in the interrupt processing can be reduced. Further, the interrupt processing time can be shortened. Furthermore, the time taken from reception of interrupt to start of saving of the context can be shortened). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention that based on the combination, the teachings of Hellwig would be modified with the prioritized interrupt processing and register allocation mechanism taught by Matsuyama resulting in a system performs prioritized interrupt processing using register allocation. Therefore, it would have been obvious to combine the teachings of Hellwig and Matsuyama.
The combination of Hellwig-Matsuyama fails to specifically teach, based on the dedicated register being assigned, execute the program corresponding to the received interrupt without switching the context.
However, Agarwal teaches, based on the dedicated register being assigned, execute the program corresponding to the received interrupt without switching the context ([0029], The interrupt handling processor (10) is coupled to the main processor (17). When a Priority Selection Block (14) arranges all the interrupt signals according to their defined times in a queue, the signal (S) is sent to the main processor depending upon the minimum defined time of an interrupt signal in the queue. The main processor (17) processes the interrupts at one go and avoids context switching).
The combination of Hellwig-Matsuyama and Agarwal are analogous because they are each related to interrupt processing. Hellwig teaches a method of prioritized interrupt processing where interrupt programs are stored in memory. Matsuyama teaches an interrupt processing method including a register allocation scheme to process interrupts based on priority. Agarwal teaches a method of register-based interrupt processing that avoids context switching. ([0029], The interrupt handling processor (10) is coupled to the main processor (17). When a Priority Selection Block (14) arranges all the interrupt signals according to their defined times in a queue, the signal (S) is sent to the main processor depending upon the minimum defined time of an interrupt signal in the queue. The main processor (17) processes the interrupts at one go and avoids context switching). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention that based on the combination, the teachings of the combination of Hellwig-Matsuyama would be modified with register-based interrupt processing mechanism taught by Agarwal resulting in a system performs prioritized interrupt processing using register allocation and avoiding context switching. Therefore, it would have been obvious to combine the teachings of the combination of Hellwig-Matsuyama and Agarwal.
As per claim 19, Matsuyama teaches, wherein the microprocessor is further configured to:
generate control signals after executing the program of the received interrupt ([0094], in response to occurrence of the interrupt factor, the priority level is determined and the register data corresponding to the accepted interrupt request are saved while the interrupt handler is fetched), the control signals being synchronized with an internal clock ([0102], At the clock C5, in the interrupt controller 1, the flag register 121 of the interrupt factor INT31 is cleared in response to the interrupt acceptance notice INTACK. Further, the second lower bit of the ISPR register 13 is set to "1" ("0010B") in response to the priority level "Pri1" of the interrupt factor INT31. Further, in the processor 2 that outputs the interrupt acceptance notice INTACK, "1" is set to the interrupt inhibition flag DI in the PSW, setting to the interrupt inhibition state) and saved in the special function registers ([0065], register file 24 includes a program counter (PC) register 241 that stores a program counter (PC), a PWS register 242 that stores a program status word (PSW), an EIPC register 243 for storing the PC in the interrupt processing, an EIPSW register 244 for storing the PSW in the interrupt processing; and [0101], when the interrupt request is accepted, the internal status of the processor 2 (values of the PC and the PSW: ins4 (PC) and ins4 (PSW)) are stored in the EIPC register 243 and the EIPSW register 244).
As per claim 20, Matsuyama teaches, wherein each of the common register and the dedicated register comprises a special purpose register and a general purpose register ([0008], the processor 200 includes an … the register file 204; and [0022], a microcomputer includes: a plurality of register lists having a plurality of register patterns, respectively, wherein each of plurality of register patterns designates registers, data of which are to be saved in a data memory), wherein the special purpose register comprises a program counter and a status register ([0065], the register file 24 includes a program counter (PC) register 241 that stores a program counter (PC), a PWS register 242 that stores a program status word (PSW), an EIPC register 243 for storing the PC in the interrupt processing, an EIPSW register 244 for storing the PSW in the interrupt processing, and a plurality of general purpose registers 240 (for example, 32-bit general purpose registers R0 to R31))), and wherein the general purpose register comprises registers configured to save operation values of execution of a first interrupt or a second interrupt ([0009], When starting the interrupt processing, the instruction executing section 203 saves data of the register file 204 in the data memory 400 (for example, a stack memory). Specifically, the instruction executing section 203 first saves data of the PC and the PSW into the data memory 400 and then, saves data of general purpose registers R0 to R31 into the data memory 400. When saving of the data of register file 204 is completed, the instruction executing section 203 executes processing corresponding to the interrupt request; and [0065], The register file 24 includes …a plurality of general purpose registers 240 (for example, 32-bit general purpose registers R0 to R31)).
As per claim 21, Hellwig teaches, wherein the look-up table is configured to assign an interrupt to a dedicated index ([0049], CPU 302 and CPU 310 comprises a CPU Internet control register (CPU ICR) 306 that includes information sent from the ICU 202, for example, to the CPU 302, 310, or by an internal CPU component such as a VMM, VM or other component. CPU 302 and CPU 310 can also be/part of/coupled with the processor 110 or any one processor 112, 114 unit therein, for example. The information sent or received can include: a current task priority that is a priority of the CPU software of execution, the latest interrupt priority sent by the ICU 202 to the CPU 302, 304, and an additional control bit that indicates whether the CPU is now enabled to be interrupted by a new interrupt with a priority above the task/sub-task priority or that satisfies a defined threshold) based on the interrupt having a number of execution occurrences during an operation period of the radio frequency integrated circuit that exceed a threshold value ([0064], the decision to enable interrupts and responding ISRs from among VMs of the same CPU 402 can be decided to be implemented directly, without a VMM call from the VMM 410, based on one or more of: the PIPN, CCPN, or additional priorities/additional priority thresholds being satisfied, as factors/functions of this decision operation by the PC 408).
As per claim 22, Hellwig the invention substantially as claimed including a slave device ([0040], system 200 includes an interrupt controller or interrupt control unit (ICU) 202/processor component communicatively coupled to a CPU 204/other processor component that arbitrates among pending interrupts mapped to a single CPU 204, which can also be the processor 110 or any one processor 112, 114 unit therein), comprising:
a memory storing instructions ([0025], instructions 150 can reside, completely or partially, within at least one of the processors 110 (e.g., within the processor's cache memory), the memory/storage devices 110, or any suitable combination thereof); and
a processor communicatively coupled to the memory ([0023], processors 110 … can include, for example, any number of processing components such as a processor 112 and a processor 114), wherein the processor is configured to execute the instructions to:
receive interrupt commands from a master through an inter-chip interface ([0021], system 100 including one or more processors (or processor cores) 110, one or more memory/storage devices 120; and [0041], A single hardware CPU 202 can map interrupts with a priority that can up to about 255 as a highest/lowest priority from zero on the opposite end of the scale, which can further be encompassed or communicated via a priority vector 220 (e.g., an 8-bit priority vector) with the priority of interrupts to the CPU 204 via one or more interrupt interface bus 208);
execute interrupts based on priorities of the interrupt commands ([0041], A single hardware CPU 202 can map interrupts with a priority that can up to about 255 as a highest/lowest priority from zero on the opposite end of the scale, which can further be encompassed or communicated via a priority vector 220 (e.g., an 8-bit priority vector) with the priority of interrupts to the CPU 204 via one or more interrupt interface bus 208; and [0042], s an interrupt or service request is received by the CPU 204 from the ICU 202 or other component it has to be serviced by the CPU 204 as a task, which can be a basic unit of programming or execution as firmware/hardware operating as a system control, which can be at least a part of a program or successive invocation of the program as a process to be executed for an application on a dedicated instance);
change setting values of special function registers based on execution of the interrupts ([0049], CPU 302 and CPU 310 comprises a CPU Internet control register (CPU ICR) 306 that includes information sent from the ICU 202, for example, to the CPU 302, 310, or by an internal CPU component such as a VMM, VM or other component. CPU 302 and CPU 310 can also be/part of/coupled with the processor 110 or any one processor 112, 114 unit therein, for example. The information sent or received can include: a current task priority that is a priority of the CPU software of execution, the latest interrupt priority sent by the ICU 202 to the CPU 302, 304, and an additional control bit that indicates whether the CPU is now enabled to be interrupted by a new interrupt with a priority above the task/sub-task priority or that satisfies a defined threshold).
Hellwig fails to specifically teach, assign at least one of a common register and a dedicated register to an interrupt to be executed, based on an execution frequency of the interrupt to be executed; based on the dedicated register being assigned, execute a program of the interrupt to be executed without performing a context switch related to an interrupt being executed; and based on the common register being assigned, perform the context switch related to the interrupt being executed, and execute the program of the interrupt to be executed.
However, Matsuyama teaches, assign at least one of a common register ([0052], the register pattern is data designating the registers, data of which are to be saved, i.e., data-saved registers, when the interrupt factor has occurred. The register pattern is set in a register list; and [0083], a context of the data-saved registers (i.e. register data) corresponding to the interrupt factor are saved in response to each of interrupt requests) and a dedicated register to an interrupt to be executed ([0022], instruction executing section is configured to execute the microinstruction prior to the fetched instruction code, to save the data of registers designated based on the acquired register pattern in the data memory; [0052], the register pattern is data designating the registers, data of which are to be saved, i.e., data-saved registers, when the interrupt factor has occurred. The register pattern is set in a register list; [0064], The register data saving control circuit 25 is provided with a RAM (not shown) for storing a micro program of microinstructions for controlling register data saving processing and outputs the microinstructions containing the register pattern to the instruction executing section 23, thereby controlling the instruction executing section 23 to execute the register data saving processing based on the microinstructions; [0066], the processor 2 accepts an interrupt request in an interrupt permission state and saves the data of registers into the data memory 4 based on the extracted register pattern; and [0080], processor 2 saves the register data uniquely into the data memory 4 in response to the accepted interrupt request), based on an execution frequency of the interrupt to be executed ([0014], by providing a register usage identifier for identifying a register group used by a user program and designating saved registers based on the register usage identifier, the registers to be saved for the interrupt processing are determined); and
based on the common register being assigned, perform the context switch related to the interrupt being executed, and execute the program of the interrupt to be executed ([0009], the instruction executing section 203 saves data of the register file 204 in the data memory 400 (for example, a stack memory). Specifically, the instruction executing section 203 first saves data of the PC and the PSW into the data memory 400 and then, saves data of general purpose registers R0 to R31 into the data memory 400. When saving of the data of register file 204 is completed, the instruction executing section 203 executes processing corresponding to the interrupt request; and [0014], by providing a register usage identifier for identifying a register group used by a user program and designating saved registers based on the register usage identifier, the registers to be saved for the interrupt processing are determined. Thereby, the registers to be saved for the interrupt processing can be changed for each user program).
The combination of Hellwig-Matsuyama fails to specifically teach based on the dedicated register being assigned, execute a program of the interrupt to be executed without performing a context switch related to an interrupt being executed; and based on the common register being assigned, perform the context switch related to the interrupt being executed, and execute the program of the interrupt to be executed.
However, Agarwal teaches, based on the dedicated register being assigned, execute a program of the interrupt to be executed without performing a context switch related to an interrupt being executed ([0029], The interrupt handling processor (10) is coupled to the main processor (17). When a Priority Selection Block (14) arranges all the interrupt signals according to their defined times in a queue, the signal (S) is sent to the main processor depending upon the minimum defined time of an interrupt signal in the queue. The main processor (17) processes the interrupts at one go and avoids context switching).
The same motivation used in the rejection of claim 18 is applicable to the instant claim.
As per claim 23, Hellwig teaches, wherein the slave device is a radio frequency integrated circuit ([0023], processors 110 (e.g… a radio-frequency integrated circuit (RFIC), another processor, or any suitable combination thereof)).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure and is as follows:
Inventor
Application No.
Teaches
Kim-Koon et al.
US 20230325243
Efficient prioritized interrupt handling:
Abstract- preemption system identifies a high priority task and a low priority task that are running on a processor… in response to determining first preemption condition and second preemption condition are satisfied, scheduling a preemption event associated with the high priority task and the low priority task
McMenamin et al.
US 8898570
Processing external interrupts based on priority and interruptibility index:
[0005], hardware component called Interrupt Directory selects a most appropriate CPU in the multiprocessor system according to an Interrupt Priority (IP) number associated with each possible external interrupt condition and an Interruptibility Index (II) assigned to each task I in every CPU of the multiprocessor system. If the Interrupt priority is greater than the Interruptibility Index, then the external interrupt is routed to a CPU executing a task with the corresponding Interruptibility Index
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/MELISSA A HEADLY/Examiner, Art Unit 2197
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