DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims.
Both claims 3 & 8 recites “a length in the second direction of the second connection part is greater than a length in the third direction of the second connection part” which is not shown in the drawing. Fig. 10 shows second connection part 42 is circular which does not satisfy the claim. Therefore, the limitation “a length in the second direction of the second connection part is greater than a length in the third direction of the second connection part” must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Both Claims 4 & 9 recites, “a length in the second direction of the first connection part is greater than a length in the third direction of the first connection part” which is not shown in drawing. Fig. 10 shows first connection part 41 is circular which does not satisfy the claim. Therefore, the limitation “a length in the second direction of the first connection part is greater than a length in the third direction of the first connection part” must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Both claim 1 (last line) & claim 6 (last line) recites “the second connection part being located on the pair of first electrode regions”. It is unclear whether it was intended to recite a second connection part being located on each of the first electrode regions of the pair of first electrode regions or being located on one of the first electrode regions of the pair of first electrode regions. Examiner is considering later interpretation and interpreting the limitation as “the second connection part being located on one of the first electrode regions of the pair of first electrode regions”.
Claims 2-5 are rejected being dependent on claim 1.
Claims 7-10 are rejected being dependent on claim 6.
Claim 8 further recites “a length in the second direction of the second connection part is greater than a length in the third direction of the second connection part” which is not clearly understood as second connection part 42 is shown circular in Fig. 10. It is unclear if it was intended to claim the shape of the second connection part 42 in Fig. 10 as rectangular shape similar to as depicted in Fig. 5 or different shape .Examiner is interpreting the shape of 42 as rectangular in the context of oval shapes of Fig. 10.
Claim 9 further recites ““a length in the second direction of the first connection part is greater than a length in the third direction of the first connection part” which is not clearly understood as first connection part 41 is shown circular in Fig. 10 .It is unclear if it was intended to claim the shape of the first connection part 41 in Fig. 10 as rectangular shape similar to as depicted in Fig. 5 or different shape. Examiner is interpreting the shape of 41 as rectangular in context of oval shapes of Fig. 10.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically teaches d as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 5-7 & 10 are rejected under 35 U.S.C. 103 as being unpatentable over KACHI et al. (US 20210273051 A1) in view of Laforet et al. (US 2017/0110573 A1) in view of Chuang et al. (US 11,456,379 B1)
Regarding claim 1, KACHI teaches,
PNG
media_image1.png
784
1019
media_image1.png
Greyscale
PNG
media_image2.png
649
553
media_image2.png
Greyscale
A semiconductor device(Fig. 3) , comprising:
a first electrode (E1, para [0030], Fig. 3);
a first semiconductor region (1, para [0035]) located on the first electrode, the first semiconductor region being of a first conductivity type (n type, para [0035]);
a second semiconductor region (2, para [0035]) located on the first semiconductor region, the second semiconductor region being of a second conductivity type (P type, para [0035]);
a third semiconductor region (3, para [0035]) located on the second semiconductor region, the third semiconductor region being of the first conductivity type (n type, para [0035]);
a second electrode (E2, para [0034]) located on the third semiconductor region; the second electrode being electrically connected with the third semiconductor region (via connection part 41, para [0042], Fig. 3);
a structure body (20, para[0037]) including an insulating part (21, para [0038]) arranged with the third semiconductor region, the second semiconductor region , and a portion of the first semiconductor region in a second direction (D2) and a third direction (D3 as marked in Fig. 3 above), the second direction being perpendicular to a first direction (D1), the first direction being from the first electrode toward the second electrode, the third direction being perpendicular to the first and second directions (as seen),
a third electrode (22, para [0037]) arranged with the first semiconductor region in the second and third directions with the insulating part interposed (Figs. 2-3),
and a fourth electrode (gate electrode 10, para [0035]) surrounding the third electrode in the second and third directions, the fourth electrode being arranged with the second semiconductor region in the second and third directions with the insulating part interposed (Figs. 2-3),
a first connection part (42, para [0042]) located on the third electrode; the first connection part being electrically connected with the third electrode (Fig. 3);
and a second connection part (43, para [0043]) located on the fourth electrode, the second connection part being electrically connected with the fourth electrode (Fig. 3),
a shape of the structure body in a plane parallel to the second and third directions being a first hexagon (A-B-C-D-E-F, Fig. 2 above) ,
the first hexagon including a pair of first sides (A-B & E-D as marked, see FIG. 2 enlarged view as annotated above ) parallel to each other,
a pair of second sides (B-C & F-E) parallel to each other, the pair of second sides crossing the pair of first sides,
and a pair of third sides (A-F & C-D) parallel to each other, the pair of third sides crossing the pair of first sides and the pair of second sides,
……the fourth electrode including a pair of first electrode regions (A-B-H-G & E-D-J-K) along the pair of first sides,
a pair of second electrode regions (B-H-I-C & F-E-K-L as marked above in Fig. 2) along the pair of second sides,
and a pair of third electrode regions (A-F-L-G & C-D-J-I) along the pair of third sides,
the second connection part (43) being located on the pair of first electrode regions (as seen)
But KACHI does not explicitly teach,
a length of the pair of first sides being greater than a length of the pair of second sides.
Meanwhile, Laforet teaches,
the cross-sectional areas of the filed plate 165 and the field structures 160 may be rectangles, regular polygon, distorted polygon ……..ellipses or ovals (para [0117], FIG. 7A, 8C) renders a varying geometric shape of a field plate structure.
And Chuang teaches,
A field plate is a conductor element that is disposed to affect the electrical filed distribution in its vicinity with proper bias (Col. 5, ll. 13-15).
Thus, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to distort the shape of the structural body 20 (to achieve a distorted polygon), with routine experiment and optimization, (such that a length of the pair of first sides being greater than a length of the pair of second sides), according to teaching of Laforet, since geometric shape of a field plate structure is important, in order to have a desired electric filed distribution in its vicinity with proper bias ,as taught by Chuang above. In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990). See also In re Boesch, 205 USPQ 215 (CCPA) (discovery of optimum value of result effective variable in known process is ordinarily within skill of art) and In re Aller, 105 USPQ 233 (CCPA 1955) (selection of optimum ranges within prior art general conditions is obvious).
Regarding claim 2, KACHI, Laforet & Chuang teaches the semiconductor device of claim 1 and further teaches, wherein a shape of the third electrode (22) in the plane parallel to the second and third directions is a second hexagon (M-N-O-P-Q-R as marked in Fig. 2 below), the second hexagon includes:
a pair of fourth sides (M-N & Q-P) parallel to each other, the pair of fourth sides being along the pair of first sides (Fig. 2 below) ;
a pair of fifth sides (N-O & R-Q) parallel to each other, the pair of fifth sides being along the pair of second sides (Fig. 2 below) ;
and a pair of sixth sides (M-R & O-P) parallel to each other, the pair of sixth sides being along the pair of third sides (Fig. 2 below),
a length of the pair of fourth sides being greater than a length of the pair of fifth sides (during routine optimization and experimentation, it would be obvious to meet this limitation).
PNG
media_image3.png
784
1019
media_image3.png
Greyscale
Regarding claim 5, KACHI, Laforet & Chuang teaches the semiconductor device of claim 1 and further teaches , wherein the first semiconductor region includes silicon (semiconductor layer is single crystal silicon, see abstract) , and the pair of first sides is along a (100) plane of a crystal of the silicon included in the first semiconductor region. (first sides A-B & E-D are extended/inclined along direction D2, which corresponds [100] direction of a crystal plane of the single crystal silicon as per para [0034]).
Regarding claim 6, KACHI teaches,
A semiconductor device (Fig. 3), comprising:
a first electrode (E1, para [0030], Fig. 3);
a first semiconductor region (1, para [0035]) located on the first electrode, the first semiconductor region being of a first conductivity type (n type, para [0035]);
a second semiconductor region (2, para [0035]) located on the first semiconductor region, the second semiconductor region being of a second conductivity type (P type, para [0035]);
a third semiconductor region (3, para [0035]) located on the second semiconductor region, the third semiconductor region being of the first conductivity type (n type, para [0035]);
a second electrode (E2, para [0034]) located on the third semiconductor region; the second electrode being electrically connected with the third semiconductor region (via connection part 41, para [0042], Fig. 3);
a structure body (20, para[0037]) including an insulating part (21) arranged with the third semiconductor region, the second semiconductor region, and a portion of the first semiconductor region in a second direction and a third direction, the second direction being perpendicular to a first direction, the first direction being from the first electrode toward the second electrode, the third direction being perpendicular to the first and second directions,
a third electrode (22, para [0037]) arranged with the first semiconductor region in the second and third directions with the insulating part interposed,
and a fourth electrode (gate electrode 10, para [0035]) surrounding the third electrode in the second and third directions, the fourth electrode being arranged with the second semiconductor region in the second and third directions with the insulating part interposed,
a first connection part (42, para [0042]) located on the third electrode; the first connection part being electrically connected with the third electrode(Fig. 3);
and a second connection part (43, para [0043]) located on the fourth electrode,
the second connection part (43) being electrically connected with the fourth electrode(Fig. 3),
BUT KACHI does not explicitly teach,
a shape of the structure body in a plane parallel to the second and third directions being a first oval, the first oval including a pair of first sides parallel to each other,
and a pair of first arcs connecting the pair of first sides to each other,
the fourth electrode including a pair of first electrode regions along the pair of first sides,
and a pair of second electrode regions along the pair of first arcs,
the second connection part being located on the pair of first electrode regions.
Meanwhile, Laforet teaches,
the cross-sectional areas of the filed plate 165 and the field structures 160 may be rectangles, regular polygon, distorted polygon ……..ellipses or ovals (para [0117], FIG. 7A, 8C) renders a varying geometric shape of a field plate structure.
And Chuang teaches,
A field plate is a conductor element that is disposed to affect the electrical filed distribution in its vicinity with proper bias (Col. 5, ll. 13-15).
Thus, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to vary the geometric shape of the structural body 20 (to form an oval shape 20 surrounded by gate electrode 10), with routine experiment and optimization, (such that a shape of the structure body in a plane parallel to the second and third directions being a first oval (20 is oval shape structure) , the first oval including a pair of first sides (straight opposing side of the oval structure 20) parallel to each other, and a pair of first arcs connecting the pair of first sides to each other (arcs of the oval structure 20 connecting the straight side) , the fourth electrode including a pair of first electrode regions along the pair of first sides (region of gate electrode along the straight side of the oval structure), and a pair of second electrode regions along the pair of first arcs (region of gate electrode 10 surrounding arc sides of the oval structure 20), the second connection part being located on the pair of first electrode regions (20 in Fig. 2 would be oval shape and second connection part 43 obviously would be on the first electrode region), according to teaching of Laforet, since geometric shape of a field plate structure is important, in order to have a desired electric filed distribution in its vicinity with proper bias ,as taught by Chuang above. In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990). See also In re Boesch, 205 USPQ 215 (CCPA) (discovery of optimum value of result effective variable in known process is ordinarily within skill of art) and In re Aller, 105 USPQ 233 (CCPA 1955) (selection of optimum ranges within prior art general conditions is obvious).
Regarding claim 7, KACHI, Laforet & Chuang teaches the semiconductor device of claim 6 and further teaches, wherein a shape of the third electrode in the plane parallel to the second and third directions is a second oval, and the second oval includes: a pair of second sides parallel to each other, the pair of second sides being along the pair of first sides and a pair of second arcs along the pair of first arcs, the pair of second arcs connecting the pair of second sides to each other (according to claim 6 rejection gate electrode 10 surrounds oval shape structural body 20 which obviously renders shape of gate electrode 10 conform to a second oval shape with pair of second sides parallel to each other and along the pair of first sides of the first oval and pair of second arcs connecting the pair of second sides and along the pair of first arcs).
Regarding claim 10, KACHI, Laforet & Chuang teaches the semiconductor device of claim 6 and further teaches , wherein the first semiconductor region includes silicon(semiconductor layer is single crystal silicon, see abstract), and the pair of first sides is along a (100) plane of a crystal of the silicon included in the first semiconductor region(first sides A-B & E-D are extended/inclined along direction D2, which corresponds [100] direction of a crystal plane of the single crystal silicon as per para [0034]).
Allowable Subject Matter
Claims 3-4, 8- 9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph and the drawing objection, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
With respect to claims 3-4, 8-9 the prior art of record does not appear to teach, suggest, or provide motivation for combination to following limitation:
wherein the pair of first sides is along the second direction, and a length in the second direction of the second connection part is greater than a length in the third direction of the second connection part (claims 3 & 8)
wherein the pair of first sides is along the second direction, and a length in the second direction of the second connection part is greater than a length in the third direction of the second connection part (claims 4 & 9 )
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHATIB A RAHMAN whose telephone number is (571)270-0494. The examiner can normally be reached on MON-FRI 8:00 am- 5:00 pm (Arizona).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor Steven Loke, can be reached on (571) 272-1657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/K.A.R/Examiner, Art Unit 2818
/STEVEN H LOKE/Supervisory Patent Examiner, Art Unit 2818
Prosecution Insights