Prosecution Insights
Last updated: April 19, 2026
Application No. 18/596,081

CONTROL CIRCUIT FOR A RESONANT CIRCUIT AND THE METHOD THEREOF

Non-Final OA §102§103
Filed
Mar 05, 2024
Examiner
TRAN, NGUYEN
Art Unit
2838
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Hangzhou Mps Semiconductor Technology Ltd.
OA Round
1 (Non-Final)
83%
Grant Probability
Favorable
1-2
OA Rounds
2y 6m
To Grant
91%
With Interview

Examiner Intelligence

Grants 83% — above average
83%
Career Allow Rate
895 granted / 1073 resolved
+15.4% vs TC avg
Moderate +8% lift
Without
With
+7.6%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
36 currently pending
Career history
1109
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
51.6%
+11.6% vs TC avg
§102
33.9%
-6.1% vs TC avg
§112
10.7%
-29.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1073 resolved cases

Office Action

§102 §103
DETAILED ACTION 1. This action is in response to the election filed on 12/23/25. Notice of Pre-AIA or AIA Status 2. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions 3. Applicant’s election without traverse of Species 1 (claims 1-3, 5, 8-12, 14, 17-25; figures 1-6 and 8) in the reply filed on 12/23/25 is acknowledged. Claim Rejections - 35 USC § 102 4. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 5. Claims 1 and 10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Elferich (US 20090316442). Regarding claim 1: Elferich discloses (i.e. figures 1-3 and 8) a control circuit (i.e. 101) for a resonant circuit (i.e. circuit of 100) having a high-side switch (i.e. S1) and a low-side switch (i.e. S2), the control circuit (i.e. 101) comprising: a low-side switch control circuit (i.e. control circuit for S2) configured to provide a low-side switch control signal (i.e. DRv2) for controlling the low-side switch (i.e. S2), wherein the low-side switch control signal (i.e. DRv2) has a first pulse (i.e. figure 8: pulse of drv2) associated with a first on-time period (i.e. on period of S2) of the low-side switch (i.e. S2), and wherein an end of the first pulse (i.e. figure 8: pulse of drv2) of the low-side switch control signal (i.e. DRv2) corresponds to a time when a voltage (i.e. figure 8: Vc) across a resonant capacitor (i.e. C) of the resonant circuit (i.e. circuit of 100) crosses zero from positive to negative (i.e. figure 8: see signals VC and Drv2). Regarding claim 10: Elferich disclsoes (i.e. figures 1-3 and 8) a resonant circuit (i.e. circuit of 100), comprising: a high-side switch (i.e. S1); a low-side switch (i.e. S2); a high-side switch control circuit (i.e. control circuit for S1) configured to provide a high-side switch control signal (i.e. DRv1) for controlling the high-side switch (i.e. S1); and a low-side switch control circuit (i.e. control circuit for S2) configured to provide a low-side switch control signal (i.e. DRv2) for controlling the low-side switch (i.e. S2), wherein the low-side switch control signal (i.e. DRv2) has a first pulse (i.e. figure 8: pulse of drv2) associated with a first on-time period (i.e. on period of S2) of the low-side switch (i.e. S2), and wherein an end of the first pulse (i.e. figure 8: pulse of drv2) of the low-side switch control signal (i.e. DRv2) corresponds to a time when a voltage (i.e. figure 8: Vc) across a resonant capacitor (i.e. C) of the resonant circuit (i.e. circuit of 100) crosses zero from positive to negative (i.e. figure 8: see signals VC and Drv2). Claim Rejections - 35 USC § 103 6. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 7. Claims 2 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Elferich (US 20090316442) in view of Halberstadt (US 10116199). Regarding claims 2 and 11: Elferich disclose (i.e. figure 8) the time when the voltage across the resonant capacitor (i.e. C) crosses zero from positive to negative (i.e. figure 8: see signal VC), but does not specifically disclose is obtained by detecting a zero-crossing detecting signal, wherein the zero-crossing detecting signal is configured to be provided by an auxiliary winding of a transformer of the resonant circuit. Halberstadt discloses a power converter (i.e. figure 18) comprising is obtained by detecting a zero-crossing detecting signal (i.e. from 1805), wherein the zero-crossing detecting signal (i.e. from 1805) is configured to be provided by an auxiliary winding (i.e. auxiliary coil) of a transformer of the resonant circuit (i.e. Col. 21, lines 63 through Col. 22, lines 1-15). Therefore, it would have been obvious to one with ordinary skill in the art before the earliest effective filing date to modify the circuit of Elferich’s invention with the converter as disclose by Halberstadt to provide better performance and overcome the problem of providing a full range of power control. 8. Claims 3, 12, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Elferich (US 20090316442) in view of Kikuchi et al. (US 20200169160). Regarding claims 3 and 12: Elferich disclose the limitation of the claim(s) as discussed above, but does not specifically disclose a switching voltage detecting circuit configured to provide a turn-on control signal to the low-side control circuit for turning on the low-side switch based on a comparison result of a switching voltage threshold and a switching voltage at a connection node of the high- side switch and the low-side switch. Kikuchi et al. disclose a power converter (i.e. figures 1, 11 and 14) comprising a switching voltage detecting circuit (i.e. 26) configured to provide a turn-on control signal to the low-side control circuit (i.e. circuit for QL) for turning on the low-side switch (i.e. Q2) based on a comparison result (i.e. from 262) of a switching voltage threshold (i.e. Vrefh) and a switching voltage (i.e. VSW) at a connection node (i.e. NS) of the high- side switch (i.e. Q1) and the low-side switch (i.e. Q2) (i.e. ¶ 147-152). Therefore, it would have been obvious to one with ordinary skill in the art before the earliest effective filing date to modify the circuit of Elferich’s invention with the converter as disclose by Kikuchi et al. to accurately perform ZVS during the turning on of the switching element and helps improve efficiency. Regarding claim 19: Elferich disclose (i.e. figures 1-3 and 8) a transformer having a primary winding, a secondary winding (i.e. primary and secondary windings of 108); wherein the resonant capacitor (i.e. C) is coupled in series with the primary winding of the transformer (i.e. 108), but does not specifically disclose an auxiliary winding. Kikuchi et al. disclose a power converter (i.e. figures 1, 11 and 14) comprising an auxiliary winding (i.e. na). Therefore, it would have been obvious to one with ordinary skill in the art before the earliest effective filing date to modify the circuit of Elferich’s invention with the converter as disclose by Kikuchi et al. to accurately perform ZVS during the turning on of the switching element and helps improve efficiency. 9. Claims 5 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Elferich (US 20090316442) in view of Kyono (US 20070263421). Regarding claims 5 and 14: Elferich disclose the limitation of the claim(s) as discussed above, but does not specifically disclose a high-side switch control circuit configured to provide a high-side switch control signal to turn off the high-side switch when a current flowing through the resonant capacitor reaches a preset peak value. Kyono disclose a power supply (i.e. figures 11 and 14) comprising a high-side switch control circuit (i.e. circuit for 3) configured to provide a high-side switch control signal (i.e. Vg2) to turn off the high-side switch (i.e. 3) when a current flowing through the resonant capacitor (i.e. 6) reaches a preset peak value (i.e. see figure 14: signal Ilr). Therefore, it would have been obvious to one with ordinary skill in the art before the earliest effective filing date to modify the circuit of Elferich’s invention with the power supply as disclose by Kyono to increase power conversion efficiency. 10. Claims 8 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Elferich (US 20090316442) in view of Xu (US 20220416644). Regarding claims 8 and 17: Elferich disclose (i.e. figures 1-3 and 8) the first pulse ends when one of following conditions is met (ii) the voltage across (i.e. figure 8: Vc) the resonant capacitor (i.e. C) crosses zero from positive to negative (i.e. see figure 8 signal VC), but does not specifically disclose the low-side switch control circuit is further configured to receive a pre-charge indicating signal, the first pulse ends when one of following conditions is met: (i) the pre-charge indicating signal indicates that a pre- charge time period of the low-side switch ends. Xu discloses a converter (i.e. figures 5-6) comprising the low-side switch control circuit (i.e. circuit for VGS2, 130, 110) is further configured to receive a pre-charge indicating signal (i.e. signal of TZVS), the first pulse ends when one of following conditions is met: (i) the pre-charge indicating signal (i.e. signal of TZVS) indicates that a pre-charge time period (i.e. figure 6: period of TZVS) of the low-side switch ends (i.e. figure 6: VGS2) (i.e. ¶ 103-108). Therefore, it would have been obvious to one with ordinary skill in the art before the earliest effective filing date to modify the circuit of Elferich’s invention with the converter as disclose by Xu for achieving more ideal dead-time setting under a wider range of input voltage and a wider range of output voltage. 11. Claims 9 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Elferich (US 20090316442) in view of Li et al. (US 20110176335) and Yang et al. (US 20240275275). Regarding claims 9 and 18: Elferich disclose (i.e. figures 1-3 and 8) the low-side switch control signal (i.e. DRv2) has a second pulse after the high-side switch is turned off (i.e. figure 3: see signal Drv1, Drv2), wherein the second pulse is associated with a second on-time period (i.e. S1 on at 303) of the low-side switch (i.e. S1), but does not specifically disclose the second pulse ends when one of following conditions is met: (i) a resonance period of a resonant inductor and the resonant capacitor ends; and (ii) a transformer of the resonant circuit is demagnetized. Li et al. discloses a power converter (i.e. figures 3-4) comprising the second pulse ends (i.e. signal Vgss2 for switch S1) when one of following conditions is met: (i) a resonance period (i.e. period of Ir, Vcr) of a resonant inductor (i.e. Ir) and the resonant capacitor (i.e. Vcr) ends (i.e. second pulse ends, when Ir and Vcr reached Immin, Vermin). Therefore, it would have been obvious to one with ordinary skill in the art before the earliest effective filing date to modify the circuit of Elferich’s invention with the converter as disclose by Li et al. for reducing output voltage ripple and audio noise and improving efficiency. Yang et al. discloses a converter (i.e. figure 4) comprising the pulse ends (i.e. SL ends) when one of following conditions is met: (ii) a transformer of the resonant circuit is demagnetized (i.e. TDS) (i.e. ¶ 33-37). Therefore, it would have been obvious to one with ordinary skill in the art before the earliest effective filing date to modify the circuit of Elferich’s invention with the converter as disclose by Yang et al. to have the second pulse ends when a transformer of the resonant circuit is demagnetized, because it increases power conversion efficiency. 12. Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Elferich (US 20090316442) in view of Kyono (US 20070263421) and Yang et al. (US 20240275275). Regarding claim 20: Elferich discloses (i.e. figures 1-3 and 8) a control method for a resonant circuit having a high-side switch (i.e. S1) and a low-side switch (i.e. S2), the control method comprising: in each switching period of multiple switching periods (i.e. switching of figure 8): turning on the low-side switch (i.e. S2); turning off the low-side switch (i.e. S2) when a pre-charge time period of the low-side switch ends, or a voltage across (i.e. figure 8: Vc) a resonant capacitor (i.e. C) of the resonant circuit crosses zero from positive to negative (i.e. figure 8: signal VC); turning on the high-side switch (i.e. S2 on); turning on the low-side switch (i.e. S1 off), but does not specifically disclose turning off the high-side switch when a current flowing through the resonant capacitor reaches a preset peak value; and turning off the low-side switch when a transformer of the resonant circuit is demagnetized, or a resonance period of a resonant inductor and the resonant capacitor of the resonant circuit ends. Kyono disclose a power supply (i.e. figures 11 and 14) comprising turning off the high-side switch (i.e. 3) when a current flowing through the resonant capacitor (i.e. 6) reaches a preset peak value (i.e. see figure 14: signal Ilr). Therefore, it would have been obvious to one with ordinary skill in the art before the earliest effective filing date to modify the circuit of Elferich’s invention with the power supply as disclose by Kyono to increase power conversion efficiency. Yang et al. discloses a converter (i.e. figure 4) comprising turning off the low-side switch (i.e. 20) when a transformer of the resonant circuit is demagnetized (i.e. figure 4: see signal SL and period TDS). Therefore, it would have been obvious to one with ordinary skill in the art before the earliest effective filing date to modify the circuit of Elferich’s invention with the converter as disclose by Yang et al. to have the second pulse ends when a transformer of the resonant circuit is demagnetized, because it increases power conversion efficiency. 13. Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Elferich (US 20090316442) in view of Kyono (US 20070263421) and Yang et al. (US 20240275275) and further in view of Kikuchi et al. (US 20200169160). Regarding claim 21: Elferich disclose the limitation of the claim(s) as discussed above, but does not specifically disclose the low-side switch is turned on when a switching voltage at a connection node of the high-side switch and the low-side switch decreases to a switching voltage threshold. Kikuchi et al. disclose a power converter (i.e. figures 1, 11 and 14) comprising the low-side switch (i.e. Q2) is turned on when a switching voltage (i.e. VSW) at a connection node of the high-side switch (i.e. Q1) and the low-side switch (i.e. Q2) decreases to a switching voltage threshold (i.e. Vrefh) (i.e. ¶ 147-152). Therefore, it would have been obvious to one with ordinary skill in the art before the earliest effective filing date to modify the circuit of Elferich’s invention with the converter as disclose by Kikuchi et al. to accurately perform ZVS during the turning on of the switching element and helps improve efficiency. 14. Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over Elferich (US 20090316442) in view of Kyono (US 20070263421) and Yang et al. (US 20240275275) and further in view of Halberstadt (US 10116199) Regarding claim 22: Elferich disclose (i.e. figure 8) the time when the voltage across the resonant capacitor (i.e. C) crosses zero from positive to negative (i.e. figure 8: see signal VC), but does not specifically disclose is obtained by detecting a zero-crossing detecting signal, wherein the zero-crossing detecting signal is configured to be provided by an auxiliary winding of a transformer of the resonant circuit. Halberstadt discloses a power converter (i.e. figure 18) comprising is obtained by detecting a zero-crossing detecting signal (i.e. from 1805), wherein the zero-crossing detecting signal (i.e. from 1805) is configured to be provided by an auxiliary winding (i.e. auxiliary coil) of a transformer of the resonant circuit (i.e. Col. 21, lines 63 through Col. 22, lines 1-15). Therefore, it would have been obvious to one with ordinary skill in the art before the earliest effective filing date to modify the circuit of Elferich’s invention with the converter as disclose by Halberstadt to provide better performance and overcome the problem of providing a full range of power control. 15. Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over Elferich (US 20090316442) in view of Kyono (US 20070263421) and Kikuchi et al. (US 20200169160). Regarding claim 23: Elferich discloses (i.e. figures 1-3 and 8) a control circuit (i.e. 101) for a resonant circuit (i.e. circuit of 100) having a first switch (i.e. S1), a second switch (i.e. S2), a transformer (i.e. 108) with a primary winding (i.e. primary winding of 108) and a secondary winding (i.e. secondary winding of 108), and a resonant capacitor (i.e. C) coupled in series with the primary winding (i.e. primary winding of 108), the control circuit (i.e. 101) comprising: configured to turn off the second switch (i.e. S2) when a voltage across the resonant capacitor (i.e. C) crosses zero (i.e. figure 8: see signals VC and Drv2), but does not specifically disclose a first switch control circuit configured to provide a first switch control signal for controlling the first switch, wherein the first switch control circuit is configured to turn off the first switch when a current flowing through the resonant capacitor reaches a preset peak value; and a second switch control circuit configured to provide a second switch control signal for controlling the second switch, wherein the second switch control circuit is configured to turn on the second switch based on a switching voltage at a connection node of the first switch and the second switch. Kyono disclose a power supply (i.e. figures 11 and 14) comprising a first switch control circuit (i.e. circuit for 3) configured to provide a first switch control signal (i.e. Vg2) for controlling the first switch (i.e. 3), wherein the first switch control circuit is configured to turn off the first switch (i.e. 3) when a current flowing through the resonant capacitor (i.e. 6) reaches a preset peak value (i.e. see figure 14: signal Ilr). Therefore, it would have been obvious to one with ordinary skill in the art before the earliest effective filing date to modify the circuit of Elferich’s invention with the power supply as disclose by Kyono to increase power conversion efficiency. Kikuchi et al. disclose a power converter (i.e. figures 1, 11 and 14) comprising a switching voltage detecting circuit (i.e. 26) configured to provide a turn-on control signal to the low-side control circuit (i.e. circuit for QL) for turning on the low-side switch (i.e. Q2) based on a comparison result (i.e. from 262) of a switching voltage threshold (i.e. Vrefh) and a switching voltage (i.e. VSW) at a connection node (i.e. NS) of the high- side switch (i.e. Q1) and the low-side switch (i.e. Q2) (i.e. ¶ 147-152). a second switch control circuit (i.e. circuit for QL) configured to provide a second switch (i.e. signal for QL) control signal for controlling the second switch (i.e. Q2), wherein the second switch control circuit (i.e. circuit for QL) is configured to turn on the second switch (i.e. Q2) based on a switching voltage (i.e. VSW) at a connection node of the first switch (i.e. Q1) and the second switch (i.e. Q2). Therefore, it would have been obvious to one with ordinary skill in the art before the earliest effective filing date to modify the circuit of Elferich’s invention with the converter as disclose by Kikuchi et al. to accurately perform ZVS during the turning on of the switching element and helps improve efficiency. 16. Claim 24 is rejected under 35 U.S.C. 103 as being unpatentable over Elferich (US 20090316442) in view of Kyono (US 20070263421) and Kikuchi et al. (US 20200169160) and further in view of Halberstadt (US 10116199). Regarding claim 24: Elferich discloses the limitation of the claim(s) as discussed above, but does not specifically disclose the second switch control circuit comprises a zero-crossing detecting circuit configured to compare a zero-crossing detecting signal with a zero-crossing threshold to detect when the voltage across the resonant capacitor crosses zero, and wherein the zero-crossing detecting signal is configured to be provided by an auxiliary winding of the transformer. Halberstadt discloses a power converter (i.e. figure 18) comprising the second switch control circuit comprises a zero-crossing detecting circuit (i.e. 1730) configured to compare a zero-crossing detecting signal (i.e. from 1805) with a zero-crossing threshold (i.e. 1810) to detect when the voltage across the resonant capacitor crosses zero (i.e. resonance capacitor crossing zero), and wherein the zero-crossing detecting signal is configured to be provided by an auxiliary winding of the transformer (i.e. auxiliary coil) (i.e. Col. 21, lines 63 through Col. 22, lines 1-15). Therefore, it would have been obvious to one with ordinary skill in the art before the earliest effective filing date to modify the circuit of Elferich’s invention with the converter as disclose by Halberstadt to provide better performance and overcome the problem of providing a full range of power control. 17. Claim 25 is rejected under 35 U.S.C. 103 as being unpatentable over Elferich (US 20090316442) in view of Kyono (US 20070263421) and Kikuchi et al. (US 20200169160) and further in view of Kikuchi et al. (US 20200169160). Regarding claim 25: Elferich disclose the limitation of the claim(s) as discussed above, but does not specifically disclose the second switch control circuit comprises a switching voltage detecting circuit for comparing a switching voltage threshold with the switching voltage at the connection node of the first switch and the second switch. Kikuchi et al. disclose a power converter (i.e. figures 1, 11 and 14) comprising the second switch control circuit (i.e. circuit for QL) comprises a switching voltage (i.e. VSW) detecting circuit for comparing a switching voltage threshold (i.e. Vrefh) with the switching voltage (i.e. VSW) at the connection node (i.e. NS) of the first switch and the second switch (i.e. Q1, Q2) (i.e. ¶ 147-152). Therefore, it would have been obvious to one with ordinary skill in the art before the earliest effective filing date to modify the circuit of Elferich’s invention with the converter as disclose by Kikuchi et al. to accurately perform ZVS during the turning on of the switching element and helps improve efficiency. Conclusion 18. Any inquiry concerning this communication or earlier communications from the examiner should be directed to NGUYEN TRAN whose telephone number is (571)270-1269. The examiner can normally be reached Flex: M-F 8-7. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Monica Lewis can be reached at 571-272-1838. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Nguyen Tran/Primary Examiner, Art Unit 2838
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Prosecution Timeline

Mar 05, 2024
Application Filed
Feb 10, 2026
Non-Final Rejection — §102, §103 (current)

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Expected OA Rounds
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2y 6m
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