DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is in response to Request for Continued Examination filed on 05/06/2026
Application is a CON of 17/601,563 which is a 371 of PCT/JP2020/017677 04/24/2020
Application claims a FP date of Apr 25, 2019
Claims 1 and 17 are independent
Claims 4-6 and 20 have been cancelled
Claims 1-3, 7-19 and 21-24 are pending
Response to Arguments
The arguments and remarks filed on 05/06/2026 have been fully considered.
Applicant's arguments filed on 05/06/2026 have been fully considered but they are not persuasive in part. Since a terminal disclaimer was not filed. Examiner has not withdrawn the double patenting rejections. Examiner has shown in the action below that the amended claims continue to be rejected on the grounds of non-statutory double patenting. Examiner would like to state that although the claims as issue are not identical, they are not patentably distinct from each other as shown in the detailed action below.
Applicant’s arguments with regards to prior art rejection appears to be persuasive and therefore the rejections have been withdrawn.
In view of the above arguments, Examiner would like to maintain the rejections as detailed in the following action.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/forms/. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to http://www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 11,961,864 B2. Although the claims at issue are not identical, they are not patentably distinct from each other as shown in the following table.
1. Application: An imaging device, comprising:
1. Patent 11,961,864 B2: An imaging device, comprising:
a first substrate part that includes a photodiode to perform photoelectric conversion and a transfer transistor electrically connected to the photodiode and transfers an electric charge from the photodiode; and
1. Patent 11,961,864 B2: a first substrate part that includes a sensor pixel to perform photoelectric conversion; and
4. Patent 11,961,864 B2: a transfer transistor that is electrically connected to the photoelectric conversion element;
a second substrate part that is disposed on one surface side of the first substrate part and includes a reading circuit to output a pixel signal based on the electric charge output from the photodiode,
1. Patent 11,961,864 B2: a second substrate part this is disposed on one surface side of the first substrate part and includes a reading circuit to output a pixel signal based on an electric charge output from the sensor pixel,
wherein the second substrate part includes: a first semiconductor substrate on which a first transistor included in the reading circuit is disposed; and
1. Patent 11,961,864 B2: wherein the second substrate part includes: a first semiconductor on which a first transistor included in the reading circuit is disposed; and
a second semiconductor substrate that is disposed on one surface side of the first semiconductor substrate and on which a first of second transistors, other than the first transistor, included in the reading circuit is disposed.
1. Patent 11,961,864 B2: a second semiconductor substrate that is disposed on one surface side of the first semiconductor substrate on which a second transistor include in the reading circuit is disposed.
4. Patent 11,961,864 B2: wherein the second transistor includes the reset transistor and the selection transistor.
wherein a second of the second transistor other than the first transistor the first of the second transistor is provided on the first semiconductor substrate, and
1. Patent 11,961,864 B2: a second semiconductor substrate … on which a second transistor included in the reading circuit is disposed.
wherein the first semiconductor substrate and the second semiconductor substrate are two separate semiconductor substrates
2. Patent 11,961,864 B2: a semiconductor substrate …., and a semiconductor film this is disposed on one surface side of the semiconductor substrate ….
2. Application: wherein the first transistor includes an amplification transistor, a reset transistor or a select transistor.
4. Patent 11,961,864 B2: wherein the second transistor includes the reset transistor and the selection transistor.
3. Application: wherein the first of the second transistor includes another of the amplification transistor, the reset transistor or the select transistor.
4. Patent 11,961,864 B2: wherein the first transistor includes the amplification transistor
7. Application: wherein the second of the second transistor includes another of the amplification transistor, the reset transistor or the select transistor.
4. Patent 11,961,864 B2: wherein the second transistor includes the reset transistor and the selection transistor.
8. Application: wherein the first substrate further includes a floating diffusion that temporarily holds the electric charge output from the photodiode via the transfer transistor.
4. Patent 11,961,864 B2: a floating diffusion that temporarily holds an electric charge outputted from the photoelectric conversion element via the transfer transistor.
9. Application: wherein the reset transistor resets a potential of the floating diffusion to a predetermined potential,
4. Patent 11,961,864 B2: a reset transistor that resets a potential of the floating diffusion to a predetermined potential;
the amplification transistor generates, as the pixel signal, a signal having a voltage according to a level of the electric charge held in the floating diffusion and the selection transistor controls a timing of outputting the pixel signal from the amplification transistor;
4. Patent 11,961,864 B2: the amplification transistor that generates, as the pixel signal, a signal having a voltage according to a level of the electric charge held in the floating diffusion; and a selection transistor that controls a timing of the outputting the pixel signals from the amplification transistor;
10. Application: wherein in a thickness direction of the second substrate part, the first transistor overlaps with the first of the second transistors
1. Patent 11,961,864 B2: wherein in a plan view from a thickness direction of the layered body, at least part of the line group is disposed to have bilateral symmetry with an amplification transistor being interposed.
11. Application: wherein the third transistor includes another of the amplification transistor, the reset transistor or the select transistor.
4. Patent 11,961,864 B2: wherein the first transistor includes the amplification transistor, and wherein the second transistor include the reset transistor and the selection transistor.
13. Application: further comprising: a plurality of photodiodes; and a first common pad electrode that is disposed on the one surface side of the first substrate part and that is disposed over a plurality of adjacent photodiodes of the plurality of photodiodes.
8. Patent 11,961,864 B2: a plurality of sensor pixels; and
a first common pad electrode that is disposed on the one surface side of the first substrate part and that is disposed over a plurality of adjacent sensor pixels of the plurality of sensor pixels.
14. Application: wherein the reading circuit is electrically connected to the plurality of photodiodes, so that one pixel unit is formed and in a plan view from the thickness direction of the second substrate, the first transistor is located in a center portion of the one pixel unit
1. Patent 11,961,864 B2: wherein in a plan view from a thickness direction of the layered body, at least part of the line group is disposed to have bilateral symmetry with an amplification transistor being interposed.
15. Application: further comprising: a plurality of photodiodes; and an element isolation layer that is disposed in the first substrate part and that is disposed between a plurality of adjacent photodiodes of the plurality of photodiodes,
10. Patent 11,961,864 B2: an element isolation layer that is disposed in the first substrate part and this is disposed between a plurality of adjacent sensor pixels of the plurality of sensor pixels
wherein the element isolation layer is disposed to be extended from the one surface of the first substrate part toward the other surface that is located opposite to the one surface.
10. Patent 11,961,864 B2: wherein the element isolation layer is disposed to be extended from the one surface of the first substrate part toward another surface that is located opposite to the one surface.
16. Application: further comprising: a plurality of photodiodes; and an element isolation layer that is disposed in the first substrate part and that is disposed between a plurality of adjacent photodiodes of the plurality of photodiodes,
10. Patent 11,961,864 B2: an element isolation layer that is disposed in the first substrate part and this is disposed between a plurality of adjacent sensor pixels of the plurality of sensor pixels
wherein the element isolation layer is disposed to be extended, toward the one surface of the first substrate part, from the other surface that is located opposite to the one surface.
10. Patent 11,961,864 B2: wherein the element isolation layer is disposed to be extended from the one surface of the first substrate part toward another surface that is located opposite to the one surface.
Claims 17-19 and 23-24 are similarly rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 11,961,864 B2 B1.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PADMA HALIYUR whose telephone number is (571)272-3287. The examiner can normally be reached Monday-Friday 7AM - 4PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Twyler Haskins can be reached at 571-272-7406. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/PADMA HALIYUR/Primary Examiner, Art Unit 2639 June 15, 2026
Prosecution Insights