DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 02/05/2026 has been entered.
Applicant(s) Response to Official Action
The response filed on 01/06/2026 has been entered and made of record.
Response to Arguments/Amendments
Presented arguments have been fully considered but are held unpersuasive. Examiner’s response to the presented arguments follows below.
Claim Rejections - 35 USC § 103
Summary of Arguments:
Regarding claim 1, the applicant argues:
“the "interrupt" in Cheng, and as identified by the Office, is not "an interrupt signal generated and transmitted from a particular pipeline of the plurality of parallel processing pipelines, wherein the interrupt signal indicates the particular pipeline has completed processing of a respective last LCU of the corresponding subset of LCU rows," as recited by amended claim 1.” [Remarks: Page 8]
“The Office's identification of Menachem "Paras. [0091], [0095]-[0098] disclose system controller 66 generating the interrupt signal causing a shut down of each pipeline based on receipt of a respective interrupt signal from each pipeline of the subset" does not combine with Cheng to disclose or make obvious "an interrupt signal generated and transmitted from a particular pipeline of the plurality of parallel processing pipelines," nor "receipt of a respective interrupt signal generated and transmitted from each pipeline of the subset," both of which are recited in amended claim 1.” [Remarks: Page 8]
“Cheng and Menachem does not disclose or make obvious … "cause a shut down of each pipeline of a subset of the plurality of parallel processing pipelines based on receipt of a respective interrupt signal generated and transmitted from each pipeline of the subset, wherein the shut down of each pipeline of the subset is based on powering off a respective individual power supply associated with the respective pipeline from which the respective interrupt signal is received," as are each recited by amended claim 1.” [Remarks: Page 9]
Regarding claim 20, the applicant argues:
“While differing in scope, independent claim 20 has been amended to recite features that are similar to distinguishing features of claim 1 discussed above. Therefore, it is respectfully submitted that claim 20 is also in condition for allowance for at least the same reasons.” [Remarks: Page 9]
Regarding claims 2-19, the applicant argues:
“The remaining claims are dependent either directly or indirectly from one of the independent claims discussed above. Applicant respectfully submits that, pursuant to 35 U.S.C. § 112(d), the dependent claims incorporate by reference all the limitations of the claim to which they refer and include their own patentable features, and are therefore in condition for allowance.” [Remarks: Page 9]
Examiner’s Response:
Regarding claim 1, the examiner contends:
To better illustrate how Cheng discloses the limitation, see paragraphs [0047] and [0049]. For example, Cheng discloses that the pipeline signals the processor when processing is complete for a context. Specifically, [0049] states the pipeline “may signal to the processor 220 that the context stop has been executed … and that the current context has finished.” This signal occurs after reaching a “valid stopping location” such as the “last block in the last row of a row group” [respective last LCU of the subset], [0047].
Cheng is not used to teach the limitations in their entirety. Cheng specifically discloses an interrupt signal generated and transmitted from a particular pipeline of the plurality of parallel processing pipelines, which has been addressed above. Further, Cheng discloses receipt of a respective interrupt signal generated and transmitted (Cheng: Paras. [0046]-[0049], [0056]-[0057] disclose the block processing pipeline’s interrupt signal may signal to the processor that the context stop has been executed in the pipeline, and causes the pipeline to stop processing.). Menachem is more detailed with respect to generated and transmitted interrupt signal from each pipeline. To elucidate, Menachem Paras. [0096], [0098] disclose managing power in parallel display pipelines and address the limitation: "receipt of a respective interrupt signal generated and transmitted from each pipeline of the subset", for example, (Menachem: [0098] discloses receiving “confirmation signals” (interrupts) indicating pipelines are ready and then transmitting a control signal to “adjust … an amount of power supplied … such as to reduce the power to zero or power off the display pipelines … or power-gate the display pipelines.”).
Cheng provides the plurality of parallel pipelines configuration (Cheng: [0028]). Menachem discloses the limitation: "cause a shut down of each pipeline of a subset of the plurality of parallel processing pipelines based on receipt of a respective interrupt signal generated and transmitted from each pipeline of the subset, wherein the shut down of each pipeline of the subset is based on powering off a respective individual power supply associated with the respective pipeline from which the respective interrupt signal is received (Menachem: [0098] discloses receiving “confirmation signals” (interrupts) indicating pipelines are ready and then transmitting a control signal to “adjust … an amount of power supplied … such as to reduce the power to zero or power off the display pipelines … or power-gate the display pipelines.” Further, Menachem: [0078], [0098] disclose applying the power-off/power-gating logic to multiple pipelines. It states the controller monitors for statuses returned from “each of the timing generators 104” or pipelines and adjusts power based on receiving the status signal.)". To recapitulate, Cheng discloses a parallel video encoding architecture where pipelines process subsets of rows (quadrows) and signal a processor upon completion of those rows (context stop/finish). Menachem discloses power management for parallel image/video processing pipelines, specifically disclosing the mechanism of receiving completion/status signals (interrupts) from individual pipelines and powering them off (power gating) to reduce power consumption when they are idle or finished processing (Menachem: [0030], [0096]-[0098]). Therefore, it would be obvious to a person of ordinary skill in the art to modify the parallel video encoding pipelines of Cheng to include the individual power-off/power-gating mechanism of Menachem. The motivation would be to conserve power (reduce leakage) when specific pipelines become idle after finishing their assigned quadrows/subsets, as taught by Menachem goal of adjusting power based on pipeline status.
Regarding claim 20, the examiner contends:
See the examiner’s response for claim 1 above.
Regarding claims 2-19, the examiner contends:
See the examiner’s response for claim 1 above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng et al., hereinafter referred to as Cheng (US 2016/0065969 A1) in view of Menachem (WO 2022/231867 A1).
As per claim 1, Cheng discloses an apparatus to process video data (Cheng: Abstract; video encoder), the apparatus comprising:
one or more memories (8800) configured to store the video data (Cheng: Fig. 14 & Para. [0114]); and
one or more processors coupled to the one or more memories, the one or more processors being configured to (Cheng: Fig. 14 & Para. [0114] discloses processors coupled to memory via communication fabric 8010 configured to):
obtain a frame of video data, wherein the frame of video data is associated with a plurality of Largest Coding Unit (LCU) rows and a plurality of LCU columns (Cheng: Paras. [0029], [0074] disclose obtaining an input video frame of any dimension and can be subdivided into 64x64 blocks (e.g., plurality of LCUs) with a plurality of rows and columns.);
process the frame of video data using a plurality of parallel processing pipelines, wherein each pipeline of the plurality of parallel processing pipelines is configured to process a corresponding subset of LCU rows of the plurality of LCU rows (Cheng: Figs. 9a-b & Paras. [0028]-[0029], [0074] disclose pipelines may be configured to run in parallel, with each pipeline processing a quadrow [i.e., corresponding subset of LCU rows of the plurality of LCU rows] from an input video frame.);
receive an interrupt signal (interrupt) generated and transmitted from a particular pipeline (240) of the plurality of parallel processing pipelines, wherein the interrupt signal indicates the particular pipeline has completed processing of a respective last LCU of the corresponding subset of LCU rows (Cheng: Fig. 4c & Paras. [0028], [0047], [0049], [0056]-[0057] disclose a block processing pipeline processing a frame by row groups has completed processing of the last block in the last row of a row group [a respective last LCU of the corresponding subset of LCU rows]. The processor receives the interrupt signal indicating a context stop has been executed. This signal occurs after reaching a “valid stopping location” such as the “last block in the last row of a row group” [respective last LCU of the subset].);
cause a shut down (stop processing) of the particular pipeline based on receipt of the interrupt signal from the particular pipeline, wherein the shut down is based on (Cheng: Paras. [0046]-[0049], [0056]-[0057] disclose the block processing pipeline’s interrupt signal may signal to the processor that the context stop has been executed in the pipeline, and causes the pipeline to stop processing.); and
cause a shut down generated and transmitted (Cheng: Paras. [0046]-[0049], [0056]-[0057] disclose the block processing pipeline’s interrupt signal may signal to the processor that the context stop has been executed in the pipeline, and causes the pipeline to stop processing.).
However, Cheng does not explicitly disclose “… wherein the shut down is based on powering off an individual power supply associated with the particular pipeline; and cause a shut down of each pipeline of a subset of the plurality of parallel processing pipelines based on receipt of a respective interrupt signal from each pipeline of the subset, wherein the shut down of each pipeline of the subset is based on powering off a respective individual power supply associated with the respective pipeline from which the respective interrupt signal is received.”
Further, Menachem is in the same field of endeavor and teaches wherein the shut down is based on powering off an individual power supply associated with the particular pipeline (Menachem: Paras. [0091], [0093], [0095] disclose the shut down is based on powering off display pipelines 60.); and
cause a shut down of each pipeline of a subset of the plurality of parallel processing pipelines based on receipt of a respective interrupt signal from each pipeline of the subset, wherein the shut down of each pipeline of the subset is based on powering off a respective individual power supply associated with the respective pipeline from which the respective interrupt signal is received (Menachem: Paras. [0068], [0071] disclose the parallel processing pipelines and Paras. [0091], [0095]-[0098] disclose system controller 66 generating the interrupt signal causing a shut down of each pipeline based on receipt of a respective interrupt signal from each pipeline of the subset, wherein the shut down powers off a respective individual power supply associated with the respective pipeline from which the respective interrupt signal is received.).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, and having the teachings of Cheng and Menachem before him or her, to modify the parallel processing pipeline architecture of Cheng to include the powering off shut down based on interrupt signals feature as described in Menachem. The motivation for doing so would have been to improve efficient power management by providing a configuration that reduces power leakage and consumption.
As per claim 2, Cheng discloses the apparatus of claim 1, wherein the one or more processors are configured to:
reactivate the particular pipeline to process a corresponding subset of LCU rows of a plurality of LCU rows of an additional frame of video data, wherein the frame of video data and the additional frame of video data are consecutive frames (Cheng: Fig. 9a & Paras. [0044], [0050], [0054], [0073] disclose using the knight’s order, the last quadrow of a video frame may be overlapped with the first row of the next [additional] video frame to be processed [the frame of video data and the additional frame of video data are consecutive frames] in the block processing pipeline).
As per claim 3, Cheng-Menachem disclose the apparatus of claim 2, wherein the particular pipeline remains shut down for one or more time cycles associated with processing the frame of video data (Menachem: when one or more of the display pipeline 60 are idle) and for one or more time cycles associated with processing the additional frame of video data (Menachem: Para. [0096] discloses the system controller 66 may power off and/or reduce power to one or more of the display pipelines 60 when one or more of the display pipeline 60 are idle, such as the duration of time between finishing processing of first image data and starting processing of second image data [additional frame of video data].).
As per claim 4, Cheng-Menachem disclose the apparatus of claim 1, wherein the one or more processors are configured to control an individual power supply associated with the particular pipeline to cause the shut down of the particular pipeline (Cheng: Paras. [0046]-[0049], [0056]-[0057] disclose the one or more processors are configured to control the pipeline to cause the pipeline to stop processing and Menachem: Paras. [0095]-[0096] disclose system controller 66 adjusting power supplied to the display pipelines 60.).
As per claim 5, Cheng-Menachem disclose the apparatus of claim 1, wherein the one or more processors are configured to:
receive the respective interrupt signal from each pipeline of the subset of the plurality of parallel processing pipelines at a different time (Menachem: Paras. [0091], [0095]-[0098] disclose system controller 66 generating the interrupt signal and each display pipelines 60 receiving the interrupt signal when one or more of the display pipeline 60 are idle, such as the duration of time between finishing processing of first image data and starting processing of second image data, therefore each pipeline can receive the interrupt signal at a different time.); and
power off the respective individual power supply associated with each pipeline of the subset according to the different time at which the respective interrupt signal is received from the respective pipeline associated with the respective individual power supply (Menachem: Paras. [0091], [0095]-[0098] disclose system controller 66 powering off the respective pipeline associated individual power supply after the interrupt signal is received according to the different time (when pipeline is idle).).
As per claim 6, Cheng discloses the apparatus of claim 1, wherein the particular pipeline remains shut down until each LCU of a plurality of LCUs included in the frame of video data has been processed (Cheng: Paras. [0036]-[0037] disclose the block processing pipeline remains shut down for a current frame and after the block processing pipeline completes processing of the low latency frame, the video encoder performs a context restart for the current frame, where the block processing pipeline continues processing of the current frame).
As per claim 7, Cheng discloses the apparatus of claim 1, wherein a first pipeline of the plurality of parallel processing pipelines does not raise the interrupt signal and does not shut down during processing of the frame of video data (Cheng: Paras. [0028], [0047], [0056] disclose at least one of the multiple pipelines may be configured to stop processing for the current context only at the end of a row group [i.e., does not raise the interrupt signal and does not shut down during processing of the frame until the end of a row group is processed]).
As per claim 8, Cheng discloses the apparatus of claim 7, wherein the one or more processors are configured to:
receive, from each remaining pipeline of the plurality of parallel processing pipelines other than the first pipeline and the particular pipeline, the respective interrupt signal, wherein the respective interrupt signal is indicative of completed LCU processing by the respective remaining pipeline from which the respective interrupt signal is received (Cheng: Fig. 14 & Paras. [0028], [0033], [0047], [0056] disclose a first pipeline not raising an interrupt signal to stop processing until a valid location is reached and since the pipelines operate in parallel for each quadrow, processors may receive a respective interrupt from each pipeline that is not the first pipeline, where each pipeline processes a quadrow from an input video frame.);
and shut down each remaining pipeline based on receipt of the respective interrupt signal (Cheng: Fig. 14 & Paras. [0028], [0033], [0047], [0056] disclose a first pipeline not raising an interrupt signal to stop processing until a valid location is reached and since the pipelines operate in parallel for each quadrow, processors may receive a respective interrupt from each pipeline that is not the first pipeline, where each pipeline processes a quadrow from an input video frame.).
As per claim 9, Cheng-Menachem disclose the apparatus of claim 1, wherein the one or more processors are configured to receive the respective interrupt signal from each pipeline of the subset at a different time during processing of the frame of video data (Menachem: Paras. [0091], [0095]-[0098] disclose system controller 66 generating the interrupt signal and each display pipelines 60 receiving the interrupt signal when one or more of the display pipeline 60 are idle, such as the duration of time between finishing processing of first image data and starting processing of second image data, therefore each pipeline can receive the interrupt signal at a different time.).
As per claim 10, Cheng discloses the apparatus of claim 1, wherein the respective last LCU is included in a last LCU row of the corresponding subset of LCU rows for the particular pipeline (Cheng: Figs. 9a-b & Paras. [0028]-[0029], [0074] disclose each pipeline processing a quadrow [i.e., corresponding subset of LCU rows] that represents each row being a LCU (64x64) [respective last LCU is included in a last LCU row of the corresponding subset of LCU rows for the particular pipeline] from an input video frame).
As per claim 11, Cheng discloses the apparatus of claim 1, wherein the last LCU row is a final LCU row assigned to the particular pipeline to process for the frame of video data (Cheng: Figs. 9a-b & Paras. [0028]-[0029], [0074] disclose each row is an LCU row with LCU blocks (64x64) of the input frame [the last LCU row is a final LCU row assigned to the particular pipeline to process for the frame of video data]).
As per claim 12, Cheng discloses the apparatus of claim 1, wherein the interrupt signal is indicative of an idle state of the particular pipeline (Cheng: Paras. [0046]-[0049], [0056]-[0057] disclose the block processing pipeline’s interrupt signal may signal to the processor that the context stop has been executed in the pipeline, and causes the pipeline to stop processing [i.e., the interrupt signal is indicative of an idle state of the particular pipeline]).
As per claim 13, Cheng discloses the apparatus of claim 1, wherein the interrupt signal indicates at least one LCU of each LCU row of the plurality of LCU rows associated with the frame of video data has been processed (Cheng: Paras. [0046]-[0049], [0056]-[0057] disclose the video encoder directs the pipeline to stop (via interrupt) the current context for the frame currently being processed. As indicated at 306 of FIG. 5, the video encoder waits for the pipeline to stop the context as the pipeline continues to process blocks from the frame until a valid stopping location is reached, such as at the end of a row group. Thus, the interrupt indicates at least one LCU among the rows of LCU rows have been processed).
As per claim 14, Cheng discloses the apparatus of claim 1, wherein the interrupt signal is indicative of zero unprocessed LCU rows remaining within the plurality of LCU rows at a time corresponding to the interrupt signal (Cheng: Paras. [0046]-[0049], [0056]-[0057] disclose the video encoder directs the pipeline to stop (via interrupt) the current context for the frame currently being processed. As indicated at 306 of FIG. 5, the video encoder waits for the pipeline to stop the context as the pipeline continues to process blocks from the frame until a valid stopping location is reached, such as at the end of a row group and notifies the other stages that the context stop is being performed at the particular location or end of row group. Since the processing doesn’t stop until at the end of a row group or quadrow, it is indicative of all the rows in that row group have been processed. Thus, the interrupt is indicative of zero unprocessed LCU rows remaining within the plurality of LCU rows at a time corresponding to the interrupt signal).
As per claim 15, Cheng-Menachem disclose the apparatus of claim 1, wherein each pipeline of the plurality of parallel processing pipelines is associated with a corresponding individually controllable power supply (Menachem: Para. [0096] discloses the system controller 66 may determine (at block 230) to adjust power supplied to the display pipelines 60. The system controller 66 may power off and/or reduce power to one or more of the display pipelines 60 when one or more of the display pipeline 60 are idle.).
As per claim 16, Cheng discloses the apparatus of claim 1, wherein the plurality of parallel processing pipelines is included in a video codec parallel processing architecture of the apparatus (Cheng: Paras. [0027]-[0028] disclose the plurality of parallel processing pipelines are implemented in video encoders and/or decoders (codecs) in which digital video frames input in one format are encoded or converted into another format).
As per claim 17, Cheng discloses the apparatus of claim 1, wherein the apparatus implements the plurality of parallel processing pipelines (Cheng: Paras. [0027]-[0028] disclose the plurality of parallel processing pipelines may be used in software and/or hardware implementations of video encoders).
As per claim 18, Cheng discloses the apparatus of claim 1, further comprising one or more cameras configured to capture the frame of video data (Cheng: Para. [0030] discloses a camera to capture the frame of video data).
As per claim 19, Cheng discloses the apparatus of claim 1, wherein the one or more processors are configured to:
output an output frame comprising processed LCUs for the frame of video data, wherein the processed LCUs are generated based on using the plurality of parallel processing pipelines to process to the frame of video data (Cheng: Fig. 6 & Paras. [0028], [0058], [0074] disclose using the plurality of parallel processing pipelines to process the input frame of video data to generate an output a processed frame of LCUs).
As per claim 20, the claim(s) recites analogous limitations to claim(s) 1 above, and
is/are therefore rejected on the same premise.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure and can be viewed in the list of references.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PEET DHILLON whose telephone number is (571)270-5647. The examiner can normally be reached M-F: 5am-1:30pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sath V. Perungavoor can be reached at 571-272-7455. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PEET DHILLON/Primary Examiner
Art Unit: 2488
Date: 02-26-2026