DETAILED ACTION
This Communication is a First Action on the Merits (FAOM). Claims 1-20, as originally filed, are pending and have been considered as follows.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 16-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 16 refers to the method of Claim 14, but Claim 14 is directed to an Information Handling System (IMS). For the purposes of examination, the Examiner is considering Claims 16-20 to be directed to and depending from the method of Claim 15.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 8 and 15 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Breakstone et al (2018/0046514 A1).
As per Claim 1, Breakstone teaches an internal Graphics Processing Unit (GPU)/Network Interface Controller (NIC) parallel switch fabric system (Figure 1 – References 100, 140, 150, 151 and 170; Page 1, Paragraph [0022] – Page 2, Paragraph [0024]), comprising: a plurality of external fabrics (Figure 5 – Reference 520; Page 8, Paragraphs [0072] and [0075]); and a computing device that is coupled to the plurality of external fabrics (Server: Figure 6 – Reference 695; Page 10, Paragraph [0091]).
(Note: In paragraph [0022], Breakstone describes a computing platform that includes among other things one or more network interface modules [i.e. Network Interface Controllers - NIC] and one or more graphical processing units [GPUs]. Breakstone also describes a PCIe fabric [i.e. internal switch fabric] made up of PCIe switch elements and corresponding PCIe links)
(Note: In paragraph [0023], Breakstone indicates that the computing platform may be included in one or more physical enclosures – e.g. rack-mountable units included in shelving or rack units that can be inserted or removed. In paragraph [0024], Breakstone indicates that the PCIe fabric selectively routes traffic among the components of a particular processor module and with external systems while maintaining logical isolation between non-included components.)
(Note: In paragraph [0075], Breakstone indicates fabric modules includes PCIe links which provide external interconnect for devices of a computing cluster as well as PCIe links which provide internal PCIe links for interlinking of PCIe switches. In paragraph [0072], Breakstone describes PCIe fabric links that provide PCIe links internal to an enclosed computing platform [e.g. server/server rack])
(Note: In paragraph [0072], Breakstone also describes Cluster PCIe fabric links that provide external PCIe links for interconnecting individual enclosures comprising a cluster [i.e. devices external to the internal Graphics Processing Unit (GPU)/Network Interface Controller (NIC) parallel switch fabric system]. The teachings of Breakstone include both an internal fabric and a plurality of external fabrics)
(Note: In paragraph [0091], Breakstone describes external systems as: host systems, management systems, end user devices, servers, other computing systems. Breakstone also indicates that external links may include Quad Small Form Factor Pluggable [QSFFP] or Quad [4-channel] Small Form Factor Pluggable [QSFP or QSFP+] jacks – i.e. ports)
Breakstone also teaches: a Network Interface Controller (NIC) set that provides access to each of the plurality of external fabrics (Figure 1 – Reference 140; Page 3, Paragraph [0030] and [0031]); a plurality of Graphics Processing Units (GPUs) (Figure 1 – Reference 170; Page 2, Paragraph [0029], [0035] and [0036]); and an internal switch fabric that is configured to couple each of the plurality of GPUs to the NIC set to provide each of the plurality of GPUs access to each of the plurality of external fabrics (Figure 5 – References 502, 504, 514, 505, 541, 551 and 554; Page 4, Paragraphs [0037] and [0038]).
(Note: In paragraphs [0030] and [0031], Breakstone indicates that network interfaces include network interface cards [NICs] which are responsible for enabling communication with other platform components [e.g. processing modules – GPUs] and/or storage units over associated PCIe links and PCIe fabrics. Breakstone also indicates each PCIe switch carries user data between NICs and GPUs)
(Note: In paragraphs [0037] and [0038], Breakstone indicates that for graphics processing operations the PCIe fabric is used to transfer graphics data and graphics processing commands between compute units/processors of a cluster so a particular compute unit/processor can control the GPU or GPUs being managed even though the received data may be associated with a different compute unit/processor)
As per Claim 8, Breakstone teaches an Information Handling System (IHS), comprising: a chassis; a Network Interface Controller (NIC) set that is included in the chassis and that provides access to each of a plurality of external fabrics; a plurality of Graphics Processing Units (GPUs) that are included in the chassis; and an internal switch fabric that is included in the chassis and configured to couple each of the plurality of GPUs to the NIC set to provide each of the plurality of GPUs access to each of the plurality of external fabrics as described in Claim 1.
As per Claim 15, Breakstone teaches a method for configuring an internal Graphics Processing Unit (GPU)/Network Interface Controller (NIC) parallel switch fabric for an Ethernet Artificial Intelligence (AI) fabric, as described in Claim 1.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2-5, 9-12 and 16-19 are rejected under 35 U.S.C. 103 as being unpatentable over Breakstone et al (2018/0046514 A1) in view of Marolia et al (2021/0042254 A1).
As per Claims 2, 9 and 16, Breakstone teaches wherein the NIC set includes a first NIC that provides access to a first external fabric included in the plurality of external fabrics, and a second NIC that provides access to a second external fabric included in the plurality of external fabrics as described in Claim 1.
Breakstone does not teach wherein the internal switch fabric is configured to: couple a first GPU included in the plurality of GPUs to each of the first NIC and the second NIC to provide the first GPU access to each of the first external fabric and the second external fabric; and couple a second GPU included in the plurality of GPUs to each of the first NIC and the second NIC to provide the second GPU access to each of the first external fabric and the second external fabric.
However, Marolia teaches coupling a first GPU included in the plurality of GPUs to each of the first NIC and the second NIC to provide the first GPU access to each of the first external fabric and the second external fabric; and coupling a second GPU included in the plurality of GPUs to each of the first NIC and the second NIC to provide the second GPU access to each of the first external fabric and the second external fabric (Figure 5 – References 504, 508, 516 and 520; Page 3, Paragraphs [0043] and [0047]).
(Note: In paragraph [0043], Maroila describes a plurality of NICs directly attached to corresponding GPUs. Maroila indicates that the direct attachment of the NICs to the GPUs enables low latency and high bandwidth communication to occur. In paragraph [0047], Maroila describes how flexible mapping of NICs [1:1 or in some similarly large ratio] with corresponding GPUs enable similar distributed performance gains)
It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the system and method taught by Breakstone with the system and method taught by Marolia to create a direct path between the network and GPU memory to establish a direct communication pathway to ensure that data-intensive workloads such as large language model (LLM) training achieve maximum throughput and minimal tail latency.
As per Claims 3, 10 and 17, the combination of Brakestone and Marolia teaches wherein the NIC set includes a first NIC that provides access to both a first external fabric and a second external fabric included in the plurality of external fabrics, and wherein the internal switch fabric is configured to: couple a first GPU included in the plurality of GPUs to the first NIC to provide the first GPU access to each of the first external fabric and the second external fabric as described in Claims 1 and 2 above.
(Note: In paragraph [0023], Breakstone describes components of the platform shown in Figure 1 being in a chassis in the form of a rack server. In paragraph [0024], Breakstone indicates the components of the platform may be coupled over the PCIe fabric and logically isolated in to any number of separate compute units [i.e. machines/compute blocks]. Additionally, any number of compute blocks may be grouped into a cluster or compute blocks for greater parallelism or capacity. This allows for a flexible design configuration to accommodate any number of scenarios)
(Note: Figure 11 of Breakstone is an illustration of a Graphical User Interface [GUI] for managing clusters and machines within clusters. In paragraph [0112], Breakstone describes the assignment of free elements/resources to existing or new machines. In paragraph [0114], Breakstone describes adding unassigned elements [e.g. NICs/GPUs] to machines. Figure 5 of Marolia illustrates a CAFÉ link which allows a user to specify multiple GPUs to parallelize AI/LLM training. Utilizing the GUI of Breakstone to connect NICs to GPUs in various external fabrics is being considered as reading on the claimed language)
It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the system and method taught by Breakstone with the system and method taught by Marolia to create a direct path between the network and GPU memory to establish a direct communication pathway to ensure that data-intensive workloads such as large language model (LLM) training achieve maximum throughput and minimal tail latency.
As per Claim 4, 11 and 18, the combination of Breakstone and Marolia teaches wherein the NIC set includes a first NIC and a second NIC that each provide access to both a first external fabric and a second external fabric included in the plurality of external fabrics as described in Claims 1 and 2.
The combination of Breakstone and Marolia also teaches coupling a first GPU included in the plurality of GPUs to the first NIC to provide the first GPU access to each of the first external fabric and the second external fabric; and couple a second GPU included in the plurality of GPUs to the second NIC to provide the second GPU access to each of the first external fabric and the second external fabric. (Note: The GUI illustrated in Figure 11 of Marolia allows for the configuration of elements [NICs and/or GPUs] to allow the coupling of resources between internal and external switch fabrics)
It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the system and method taught by Breakstone with the system and method taught by Marolia to create a direct path between the network and GPU memory to establish a direct communication pathway to ensure that data-intensive workloads such as large language model (LLM) training achieve maximum throughput and minimal tail latency.
As per Claims 5, 12 and 19, the combination of Breakstone and Marolia teaches wherein the NIC set includes a first NIC that provides access to both a first external fabric and a second external fabric included in the plurality of external fabrics, and a second NIC that provides access to both a third external fabric and a fourth external fabric included in the plurality of external fabrics, and wherein the internal switch fabric is configured to: couple a first GPU included in the plurality of GPUs to each of the first NIC and the second NIC to provide the first GPU access to each of the first external fabric, the second external fabric, the third external fabric, and the fourth external fabric; and couple a second GPU included in the plurality of GPUs to each of the first NIC and the second NIC to provide the second GPU access to each of the first external fabric, the second external fabric, the third external fabric, and the fourth external fabric.
(Note: Claim 5 differs from Claim 4 in that in Claim 5 the second NIC provides access to a third and fourth external fabric whereas in Claim 4 the first and second NIC provide access to the first and second external fabric. The GUI illustrated in Figure 11 of Marolia allows for the configuration of elements [NICs and/or GPUs] to allow the coupling of resources between internal and external switch fabrics)
It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the system and method taught by Breakstone with the system and method taught by Marolia to create a direct path between the network and GPU memory to establish a direct communication pathway to ensure that data-intensive workloads such as large language model (LLM) training achieve maximum throughput and minimal tail latency.
Claim(s) 6, 7, 13, 14 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Breakstone et al (2018/0046514 A1) in view of Marolia et al (2021/0042254 A1) as applied to Claims 5, 12 and 19 above, and further in view of SAGIE et al (2018/0359544 A1).
As per Claims 6 and 13, the combination of Breakstone and Marolia teaches the system of Claims 5 and 12; but does not teach wherein the first NIC includes a first NIC bandwidth that has been subdivided into a plurality of first NIC bandwidth subsets that are each shared by the first GPU and the second GPU, and wherein the second NIC includes a second NIC bandwidth that has been subdivided into a plurality of second NIC bandwidth subsets that are each shared by the first GPU and the second GPU.
However, Sagie teaches wherein the first NIC includes a first NIC bandwidth that has been subdivided into a plurality of first NIC bandwidth subsets that are each shared by the first GPU and the second GPU, and wherein the second NIC includes a second NIC bandwidth that has been subdivided into a plurality of second NIC bandwidth subsets that are each shared by the first GPU and the second GPU (Figures 1 and 2 – Reference 20; Page 3, Paragraphs [0054] and [0055]).
(Note: In paragraph [0054], Sagie describes a NIC card having optical transceivers [e.g. 12X25 GB each – 24 channels total]. In paragraph [0055], Sagie indicates that the NIC card has an aggregate of 300GB in bandwidth which may be split in various ways [e.g. 3X100 GB, 12X25 GB, etc.] The Examiner finds the 300 GB in bandwidth may be split in a number of different configurations [i.e. 1X100 GB and 8X 25 GB; 2X100 GB and 4X 25GB; 2X75 GB and 1X 150GB; etc.] which each segmented bandwidth being associated with a respective GPU)
It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the system taught by Breakstone and Marolia with the system taught by Sagie to enable both the NIC and the GPU to handle data transfer directly via direct memory access which allows the host CPU to be less involved in networking tasks freeing up the CPU to manage other critical operations.
As per Claims 7, 14 and 20 the combination of Breakstone, Marolia and Sagie teaches wherein the first NIC includes a first NIC bandwidth that has been subdivided into a plurality of first NIC bandwidth subsets that are each dedicated to a respective one of the first GPU and the second GPU, and wherein the second NIC includes a second NIC bandwidth that has been subdivided into a plurality of second NIC bandwidth subsets that are each dedicated to a respective one of the first GPU and the second GPU as described in Claim 6.
It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the system and method taught by Breakstone and Marolia with the system and method taught by Sagie to enable both the NIC and the GPU to handle data transfer directly via direct memory access which allows the host CPU to be less involved in networking tasks freeing up the CPU to manage other critical operations.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Skirmont et al (2024/0184732 A1), Lien (10,585,833 B1), Long et al (2020/0264998 A1), Cannata et al (2023/0169019 A1) and Akhter (2016/0292117 A1). Each of these describes systems and methods of establishing connection between network elements within a communication system.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHARYE POPE whose telephone number is (571)270-5587. The examiner can normally be reached Monday - Friday 8AM - 4PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ahmad Matar can be reached at 571-272-7488. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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KHARYE POPE
Primary Examiner
Art Unit 2693
/KHARYE POPE/Primary Examiner, Art Unit 2693
Prosecution Insights