DETAILED ACTION
This office action is in response to the amendment filed on 04/08/2026. Claims 27-41 are pending, of which claims 27, 29-30, 34, 38-40 are amended, and claims 28, 35, 41 are cancelled by the current amendment.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 29 is rejected under 35 U.S.C. 102(a)(1) and/or (a)(2) as being anticipated by Sakurai et al. (US Patent or PG Pub. No. 20050276110, hereinafter ‘110).
Claim 29, ‘110 teaches a semiconductor device (e.g., see Abstract, [0042], Fig. 1-5) comprising: a logic control circuit (e.g., 2 and/or18) issuing a command (e.g., the corresponding command based on C1-C7 from 18 requesting 19 ON and 20 OFF, see Fig. 1-2) associated with a first operation mode (e.g., the corresponding regulator received command to be turned ON) and a second operation mode (e.g., the corresponding regulator received command to be turned OFF, see [0048], Fig. 2-5); and
a first regulator (e.g., 19) and a second regulator (e.g., 20, see Fig. 1-3), wherein in response to the command, the first regulator outputs a first output voltage associated with the first operation mode (e.g., 19 being ON in response to the command from 18 requesting 19 ON and 20 OFF, see, Fig. 1-5), and in response to the command, the second regulator circuit outputs a second output voltage associated with the second operation mode (e.g., 20 being OFF in response to the command from 18 requesting 19 ON and 20 OFF, see Fig. 1-2),
wherein the first regulator operates in the first operation mode when the second regulator operates in the second operation mode (e.g., 19 ON and 20 being OFF in response to the command from 18 requesting 19 ON and 20 OFF, see Fig. 1-2).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1,148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103(a) are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating
obviousness or nonobviousness.
Claim 30 is rejected under 35 U.S.C. 103(a) as being unpatentable over Sakurai et al. (US Patent or PG Pub. No. 20050276110, hereinafter ‘110), in view of Brittner et al. (US Patent or PG Pub. No. 20210257041, hereinafter ‘041).
Claim 30, ‘110 teaches a semiconductor device (e.g., see Abstract, [0042], Fig. 1-5) comprising: a logic control circuit (e.g., 2 and/or18) issuing a command associated with a first operation mode (e.g., the command associated with the NORMAL Operation mode) and a second operation mode (e.g., the command associated with the STANDBY mode, see Fig. 2); and a first regulator and a second regulator (e.g., the circuits comprising 19, 20, 21 respectively, see Fig. 1-3), wherein in response to the command, the first regulator outputs a first output voltage associated with the first operation mode (e.g., VDDP under NORMAL operation mode, see Fig. 2), and in response to the command, the second regulator circuit outputs a second output voltage associated with the second operation mode (e.g., VDDP under STANDBY operation mode, see Abstract, [0042], Fig. 2, 3), wherein the first output voltage is applied to control circuits having processing logic circuits to generate and output command signal (e.g., 12, see [0044]).
‘110 does not explicitly disclose that a processor.
‘041 discloses a semiconductor-based storage device (e.g., 1000a) further having a processor to perform a data recovery operation on the non-volatile memory or to control the overall operation of the storage controller (e.g., 110_1, 110_2, see [0113][0116], Fig. 8).
Therefore, It would have been obvious to one having ordinary skill in the art before the effective filing date to modify ‘110 by include the professors in the storage device as taught by ‘041 in order of being able to provide the ability to to perform a data recovery operation on the non-volatile memory or to control the overall operation of the storage controller (e.g., see [0113][0116], Fig. 8).
Allowable Subject Matter
Claims 27, 31-34, 36-40 are allowable.
The following is a statement of reasons for the indication of allowable subject matters:
For claims 27, 31-33, the closet prior art (which has been made of record) fail to disclose (by themselves or in combination): “a precharge circuit coupled to an output terminal and, in response to the mode switch signal, configured to: (a) be decoupled from the regulator circuit in the first operation mode, and (b) be coupled to the regulator circuit in the second operation mode, wherein an operation current of the regulator circuit in the first operation mode is smaller than the operation current in the second operation mode” in combination with the additionally claimed features, as are claimed by Applicant.
For claims 34, 36-39, the closet prior art (which has been made of record) fail to disclose (by themselves or in combination): “a precharge circuit coupled to an output terminal and, in response to the mode switch signal, configured to: (a) be decoupled from the regulator circuit in the first operation mode, and (b) be coupled to the regulator circuit in the second operation mode, wherein an operation current of the regulator circuit in the first operation mode is smaller than the operation current in the second operation mode” in combination with the additionally claimed features, as are claimed by Applicant.
For claim 40, the closet prior art (which has been made of record) fail to disclose (by themselves or in combination): “a precharge circuit coupled to the output terminal and, in respond to the mode switch signal, wherein the regulator is configured to generate an output voltage and compare a reference voltage and a voltage coupled to the output voltage by a feedback loop, and the precharge circuit is coupled to the output terminal and, in response to the mode switch signal, is configured to:(a) be decoupled from the regulator circuit in the first operation mode, and(b) be coupled to the regulator circuit in the second operation mode, and an operation current of the regulator circuit in the first operation mode is smaller than the operation current in the second operation mode” in combination with the additionally claimed features, as are claimed by Applicant.
These features taken alone or in combination are neither disclosed nor suggested by the prior art of record as a whole, either alone or in combination. Therefore, Applicant's claims are determined to be novel and non-obvious.
Examiner's Note:
Examiner has cited particular columns and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JUE ZHANG whose telephone number is (571)270-1263. The examiner can normally be reached on M-F: 8:30AM-5:00PM
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Monica Lewis can be reached on 571-272-2838. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JUE ZHANG/
Primary Examiner, Art Unit 2838
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