DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-7, 9, 14-20, and 22 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Trans et al (2003/0016770).
Regarding claims 1 and 14, Trans discloses a method and communication apparatus, comprising a receiver, which is disposed in proximity to a transmitter, the receiver comprising: an input buffer (see elastic buffer in figure 63 and paragraph 0818; data is put in a queue, the bucket, and at regular intervals, data is taken from the queue and put onto the medium in paragraph 0840) configured to receive from the transmitter aggressor data (see Near ECHO data from the transmitter (T) to the receiver R in figure 10), the aggressor data being timed by a transmitter clock clocking the transmitter (see the RN transmitter's clock in paragraph 0495); a front end (see analog front-end in figure 29) configured to receive data over a communication link, the data being serialized (see ADC in figure 29; transferred in serial fashion in paragraph 0505) according to a receiver clock clocking the receiver, the receiver clock operating independently of the transmitter clock (see the PN receiver's clock in paragraph 0494), the front end further configured to generate a stream of data samples corresponding to the received data (see The receivers recover the clock and phase from the received signal and use it for the sample timing to recover the data in paragraph 0027); and an adaptive resampling circuit configured to resample the aggressor data, and to generate resampled data timed by the receiver clock (see before further processing, the demodulated data has to be re-synchronized (re-sampled) with FSYM_SYS clock in paragraph 1399); and a crosstalk cancellation circuit configured to estimate, based on the resampled data, a crosstalk error signal related to the aggressor data, and to subtract the estimated crosstalk error signal from the stream of data samples (see crosstalk error and canceller in paragraph 0221; A NEXT (near-end crosstalk) canceller and the output signal of the canceller is subtracted from the received signal immediately after the AID in paragraph 0226 and figure 20A).
Regarding claims 2 and 15, Trans discloses wherein both the transmitter and the receiver are disposed within a same Serializer/Deserializer (SerDes) device (see Tx (transmitter), DAC (deserializer), Rx (receiver), ADC (serializer) in figure 29).
Regarding claims 3 and 16, Trans discloses wherein the transmitter and the receiver are disposed in different respective SerDes devices (see NEXT_21, NEXT_31, and NEXT_41 in figure 10).
Regarding claims 4 and 17, Trans discloses wherein the adaptive resampling circuit is configured to resample the aggressor data according to an estimated time-varying phase shift between the transmitter clock and the receiver clock (see adaptive filters and algorithms that model the estimated signal and channel responses to optimize signal recovery for improving the signal to noise ratio (SNR) of the Com2000.TM. system in paragraph 0223; the newly introduced Decision Precursor ISI Canceller (DPIC). The DPIC makes use of the D detected symbols from the output of the Slicer to estimate the precursor ISI which still exists at the input sample of the Slicer. The estimation of the residual ISI value is done by a D-tap Finite Impulse Filter (FIR) in paragraph 0292; The phase shift in paragraph 0771).
Regarding claims 5 and 18, Trans discloses wherein the receiver comprises a phase detector circuit, configured to estimate a frequency offset value from which the time-varying phase shift is derived, by generating a sequence of training symbols in synchronization with the transmitter clock, and sampling the training symbols in the sequence in synchronization with the receiver clock (see a sequence of training symbols in paragraphs 0383, 0385, 0462).
Regarding claims 6 and 19, Trans discloses wherein the phase detector circuit comprises a Digital-to-Analog Converter (DAC) (see ADC in figure 29), and wherein the phase detector circuit is configured to generate the sequence of training symbols by generating a sequence of pseudorandom bits, and converting the pseudorandom bits in the sequence into corresponding analog training symbols using the DAC (see DAC in figure 29; a Pseudo Random (PN) noise training sequence in paragraph 0615; a selected predefined node ID of specific Pseudo Random Noise (PN) sequence code, is used as the preamble bits for Master and Slave to perform as the background Sounding sequence autocorrelation for channel adaptation and also as a station code ID for security access purpose in paragraphs 0647; the Phase Residual Detector in paragraph 0221).
Regarding claims 7 and 20, Trans discloses wherein the phase detector circuit comprises an Analog-to-Digital Converter (ADC) (see ADC in figure 29), configured to sample the sequence of training symbols (see a sequence of training symbols in paragraph 0383) using a sampling clock (see the system sampling clock in paragraph 1368) that is synchronized with the receiver clock and shifted from the receiver clock by a sampling phase that is indicative of the time-varying phase shift between the transmitter clock and the receiver clock (see receives sampling clock from Synchronizer in paragraph 1501; a synchronization between sender and receiver is needed so that they are attached and connected to the same bitstream in paragraph 0046; The phase shift in paragraph 0771).
Regarding claims 9 and 22, Trans discloses wherein the crosstalk cancellation circuit comprises a digital filter, which is configured to filter the resampled data to generate the crosstalk error signal (see FIR filtering schemes in multi-channel signal coding (advance adaptive equalization) that enhance the channel Inter-symbol Interference (ISI) and Cross Talk noise suppression for wireline and Multipath Noise and Fading Suppression for wireless applications in paragraph 0015; errors in paragraphs 0546, 0571, 0631).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 8 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Trans.
Regarding claims 8 and 21, Trans discloses a clock can generate different frequencies (see paragraphs 0471-0475) but doesn't specifically disclose a clock used for generating the sequence of training symbols is slower than the transmitter clock, and the sampling clock used for sampling the ADC is slower than the receiver clock. However, to use one frequency over the other for a specific signal is a matter of design choice. A person of ordinary skill in the art at the time the invention was made to select a frequency from available frequencies in order to meet specific needs.
Allowable Subject Matter
Claims 10-13 and 23-26 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/BRIAN D NGUYEN/Primary Examiner, Art Unit 2475