Prosecution Insights
Last updated: July 17, 2026
Application No. 18/597,208

MEMORY, OPERATION METHOD THEREOF, AND MEMORY SYSTEM

Final Rejection §102
Filed
Mar 06, 2024
Priority
Nov 28, 2023 — CN 2023116208314
Examiner
FAAL, BABOUCARR
Art Unit
2138
Tech Center
2100 — Computer Architecture & Software
Assignee
Yangtze Memory Technologies Co., Ltd.
OA Round
2 (Final)
80%
Grant Probability
Favorable
3-4
OA Rounds
5m
Est. Remaining
95%
With Interview

Examiner Intelligence

Grants 80% — above average
80%
Career Allowance Rate
432 granted / 537 resolved
+25.4% vs TC avg
Moderate +14% lift
Without
With
+14.5%
Interview Lift
resolved cases with interview
Typical timeline
2y 10m
Avg Prosecution
23 currently pending
Career history
570
Total Applications
across all art units

Statute-Specific Performance

§101
2.7%
-37.3% vs TC avg
§103
75.3%
+35.3% vs TC avg
§102
15.3%
-24.7% vs TC avg
§112
2.8%
-37.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 537 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-4, 11-16 and 19-21 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Seo 20200152256 herein Seo. Per claim 1, Seo discloses: a memory cell array comprising a plurality of word lines; and a peripheral circuit coupled to the memory cell array, (fig. 1) wherein the operation method comprises: applying a precharge voltage to a selected word line of the plurality of word lines at a first moment; (fig. 8, t_n, ¶0082; the memory device 100 may receive the precharge command PRE from the memory controller 11. In operation S250, the memory device 100 may apply the first deactivation voltage VDA1 to the selected wordline; the examiner notes that the voltage pulse is merely a voltage applied to the to prepare for the pre precharge) changing a voltage applied to a non-selected word line adjacent to the selected word line from a first voltage to a second voltage at a second moment before the first moment, wherein the first voltage is greater than the second voltage; (fig. 8, ¶0080;; At a first time point t1 when the reference time interval T_ref elapses from the 0-th time point t0, the memory device 100 may apply the second deactivation voltage VDA2 to the unselected wordlines. For example, at the first time point t1, the memory device 100 may decrease a voltage of the unselected wordlines from the first deactivation voltage VDA1 to the second deactivation voltage VDA2.) and applying a voltage pulse to the selected word line at a third moment before the first moment (fig. 8, t_n, ¶0080; at the 0-th time point t0, the memory device 100 may apply the first activation voltage VA1 to the selected wordline and may apply the first deactivation voltage VDA1 to the unselected wordlines.; ¶0082; In operation S250, the memory device 100 may apply the first deactivation voltage VDA1 to the selected wordline). Per claim 2, Seo discloses: wherein the third moment is not earlier than the second moment (fig. 8, ¶0080; t_0, t_1 and t_n). Per claim 3, Seo discloses: wherein applying the voltage pulse to the selected word line at the third moment before the first moment comprises: starting to apply a third voltage to the selected word line at the third moment before the first moment, wherein the third voltage (VDA1) is greater than an absolute value of a difference between the first voltage (VDA1) and the second voltage (VDA2) (fig. 8, ¶0082; In operation S250, the memory device 100 may apply the first deactivation voltage VDA1 to the selected wordline; ¶0083; during the wordline activation period tRAS, the memory device 100 may decrease a voltage of unselected wordlines from the first deactivation voltage VDA1 to the second deactivation voltage VDA2. As such, deterioration of memory cells connected to the unselected wordlines due to a high voltage (i.e., the first activation voltage VA1) of the selected wordline during the wordline activation period tRAS may be reduced). Per claim 4, Seo discloses: wherein applying the voltage pulse to the selected word line at the third moment before the first moment further comprises: finishing applying the third voltage to the selected word line at a fourth moment after the third moment and before the first moment (fig. 8, ¶0082; In operation S250, the memory device 100 may apply the first deactivation voltage VDA1 to the selected wordline; ¶0083; during the wordline activation period tRAS, the memory device 100 may decrease a voltage of unselected wordlines from the first deactivation voltage VDA1 to the second deactivation voltage VDA2. As such, deterioration of memory cells connected to the unselected wordlines due to a high voltage (i.e., the first activation voltage VA1) of the selected wordline during the wordline activation period tRAS may be reduced). Per claim 11, Seo discloses: wherein when the selected word line is an nth word line, the adjacent non-selected word line comprises an (n−1)th word line and an (n+1)th word line, n being a natural number (fig. 9, ¶0086; The memory device 100 may apply the first deactivation voltage VDA1 or the second deactivation voltage VDA2 to the unselected wordlines. For example, the memory device 100 may apply the second deactivation voltage VDA2 to unselected wordlines (e.g., the third and fifth wordlines WL3 and WL5) adjacent to the selected wordline (e.g., the fourth wordline WL4) and may apply the first deactivation voltage VDA1 to the remaining unselected wordlines (e.g., the first, second, sixth, seventh, and eighth wordlines WL1, WL2, WL6, WL7, and WL8)). Per claim 12, Seo discloses: wherein the adjacent non-selected word line further comprises a word line spaced apart from the selected word line by m word lines, m being a natural number greater than or equal to 1 and less than or equal to 4 (fig. 9, ¶0086; the memory device 100 may apply the second deactivation voltage VDA2 to unselected wordlines (e.g., the third and fifth wordlines WL3 and WL5) adjacent to the selected wordline (e.g., the fourth wordline WL4) and may apply the first deactivation voltage VDA1 to the remaining unselected wordlines (e.g., the first, second, sixth, seventh, and eighth wordlines WL1, WL2, WL6, WL7, and WL8)). Claims 13-16 are the memory claim corresponding to the method claims 1-4 and are rejected under the same reasons set forth in connection with the rejection of claims 1-4. The rejection is silent to the driving circuit, control circuits and select signals implementing the method of claim 1. However, Seo discloses voltage/control circuits in fig. 13 & 16, ¶0110-0113. Per claim 19, Seo discloses: comprising a dynamic random access memory (fig. 18, ¶0123; a plurality of DRAM devices 1210 to 1290, and a plurality of data buffers DB. The RCD 1100 may receive a command/address CA and a clock signal CK from an external device (e.g., a host or a memory controller). In response to the received signals, the RCD 1100 may transmit the command/address CA to the plurality of DRAM devices 1210 to 1290 and may control the plurality of data buffers DB). Claim 20 is the system claim corresponding to the method claim 1 and is rejected under the same reasons set forth in connection with the rejection of claim 1. Per claim 21, Seo discloses: wherein applying the voltage pulse to the selected word line at the third moment before the first moment comprises: starting to apply a third voltage to the selected word line at the third moment before the first moment, wherein the third voltage (VDA1) is greater than an absolute value of a difference between the first voltage (VDA1) and the second voltage (VDA2) (fig. 8, ¶0082; In operation S250, the memory device 100 may apply the first deactivation voltage VDA1 to the selected wordline; ¶0083; during the wordline activation period tRAS, the memory device 100 may decrease a voltage of unselected wordlines from the first deactivation voltage VDA1 to the second deactivation voltage VDA2. As such, deterioration of memory cells connected to the unselected wordlines due to a high voltage (i.e., the first activation voltage VA1) of the selected wordline during the wordline activation period tRAS may be reduced). Allowable Subject Matter Claims 5-10, 17-18 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Response to Arguments Applicant's arguments filed 2/24/26 have been fully considered but they are not persuasive. The applicant argues: To reject Applicant's claimed third moment, the Office Action relies on Seo's t0. To reject Applicant's claimed second moment, the Office Action relies on Seo's t1. Seo's t0 precedes Seo's t1. However, as amended herein, Applicant's claims require that the third moment is not earlier than the second moment. Therefore, the temporal arrangement Seo's t0 and t1, as interpreted by the Office Action, is directly contradictory to Applicant's claimed temporal arrangement of the second and third moments, as amended herein. The examiner respectful disagrees and asserts that the claim merely requires three moments wherein the moments are defined by the function being performed. While the moments are defined as first, second and third, they don’t follow an order with the 2nd being the first, the 3rd being the second and the 1st being the third. Based on the order presented by the claim, the naming convention presented in the claims are merely labels. The 2nd moment is mapped to the t0 wherein a voltage VDA1 in view of a precharge command is applied. The 3rd moment is mapped to t1 wherein VDA2 is applied to the to the non-selected wordlines. The first moment is mapped to tn. Therefore, Seo discloses the moments are presented in temporal order based on each moments associated function. Remark Examiner respectfully requests, in response to this Office action, support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line number(s) in the specification and/or drawing figure(s). This will assist Examiner in prosecuting the application. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Kim 20080186776 discloses a precharged programming scheme: The controller controls the driver in a programming operation, and is configured to drive all wordlines of the memory cells to a first pass voltage for coupling a string precharge voltage provided by the source line to the memory cells, the string precharge voltage being greater than the first pass voltage; to continue driving all the wordlines except a first wordline corresponding to a first memory cell adjacent to the a selected memory cell to second pass voltage greater than the first pass voltage, the first memory cell being positioned between the selected memory cell and the string select device; to drive a second wordline corresponding to a second memory cell adjacent to the selected memory cell to a first supply voltage for turning off the second memory cell; to drive a third wordline corresponding to the selected memory cell to a programming voltage greater than the second pass voltage, and to couple the bitline to the selected memory cell. THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to BABOUCARR FAAL whose telephone number is (571)270-5073. The examiner can normally be reached M-F 8:30-5:30 EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Tim VO can be reached at 5712723642. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. BABOUCARR . FAAL Primary Examiner Art Unit 2138 /BABOUCARR FAAL/Primary Examiner, Art Unit 2138
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Prosecution Timeline

Mar 06, 2024
Application Filed
Nov 28, 2025
Non-Final Rejection mailed — §102
Feb 24, 2026
Response Filed
Jun 12, 2026
Final Rejection mailed — §102 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
80%
Grant Probability
95%
With Interview (+14.5%)
2y 10m (~5m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 537 resolved cases by this examiner. Grant probability derived from career allowance rate.

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