DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. This action is responsive to the application filed March 06, 2024.
Claims 1-5 are pending and are presenting for examination
Claim Objections
3. Claims 1-5 are objected to because of the following informalities:
Claim 1:
Lines 4-5, “the predetermined sequences” lacks proper antecedent basis.
Line 5 replacing “, optionally” with --or-- might be better.
Line 6, should “an instruction” be --instructions--?
Line 8, “the processors” lacks proper antecedent basis.
Lines 13-15, “wherein case the N+1th instruction selected is a local instruction, and otherwise, the N+1th instruction selected is a read access instruction (R) or a write access instruction (W)” does not appear to be clear what is claimed.
Claim 2:
Line 3, “the ratio” and “the number” lack proper antecedent basis.
Line 4, “the total number of instructions” may not have proper antecedent basis.
Line 5, “the ratio” lacks proper antecedent basis. Further, “read access instruction (W)” should have been either --read access instructions (R)-- or --write access instructions (W)--.
Line 8, “the memory addresses” lacks proper antecedent basis.
Claim 3:
Line 3, “the read access instructions (R)” is unclear whether it refer to “read access instructions (R)” in lines 3-4 or 5 of claim 2. Further, “(R)” is used for “read access instruction” (see claim 1) and “the read access instructions” (see claim 2), and (W) is used for “write access instruction” (see claim 1) and “write access instructions” (see claim 2).
Claim 4:
Line 6, “the Shannon entropy (Ep)” lacks proper antecedent basis.
Line 8, “the entropy E” lacks antecedent basis.
Line 9, “the distance” lacks proper antecedent basis. Further, “the previous one” is not clear.
Line 11, “the interleaving (Iv)” lacks proper antecedent basis.
Line 15, “that” is not clear.
Further, “type” may have an issue since it is not clear what “type” means, e.g., type of function, type of read access instruction, type of write instruction, etc. The specification also simply states “type”.
Appropriate correction is required.
Claim 5 is also objected to for being depended upon the objection of base claim 1.
Claim Rejections - 35 USC § 101
4. 35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
5. Claims 1-5 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Independent Claim 1 recites:
A method for iteratively generating automatically a sequence of Nmax instructions in assembly language, the sequence being executable error-free by a multi-core processor, the method comprising steps of:
[a] initializing registers of the processor, then selecting a first instruction of the predetermined sequence, optionally at random; and
[b] selecting, provided that N<Nmax, an N+1th instruction among an instruction to read from a memory connected to the cores of the processor by a memory bus, an instruction to write to said memory, and a local instruction using only the registers of the processors, according to rules and to priorities between said rules,
said rules using respective differences between statistical-metric values of statistical metrics of a memory access pattern (P) of a sequence of N previous instructions having statistical-metric values, and setpoint values;
the rules comprising a first test rule if memory intensity (Im) is greater than a memory-intensity setpoint (Im_c), wherein case the N+1th instruction selected is a local instruction, and otherwise, the N+1th instruction selected is a read access instruction (R) or a write access instruction (W).
The claim1 recites the limitation of:
[a] initializing registers of the processor, then selecting a first instruction of the predetermined sequence, optionally at random; and
[b] selecting, provided that N<Nmax, an N+1th instruction among an instruction to read from a memory connected to the cores of the processor, an instruction to write to said memory, and a local instruction using only the registers of the processors, according to rules and to priorities between said rules,
said rules using respective differences between statistical-metric values of statistical metrics of a memory access pattern (P) of a sequence of N previous instructions having statistical-metric values, and setpoint values;
the rules comprising a first test rule if memory intensity (Im) is greater than a memory-intensity setpoint (Im_c), wherein case the N+1th instruction selected is a local instruction, and otherwise, the N+1th instruction selected is a read access instruction (R) or a write access instruction (W).
These limitations of steps [a] and [b] as draft, are functions that, under its broadest reasonable interpretation, recite the abstract idea of a mental process. The limitations encompass a human mind carrying out the function through observation, evaluation judgment and /or opinion, or even with the aid of pen and paper. Thus, this limitation recites and falls within the “Mental Processes” grouping of abstract ideas under Prong 1.
Step 2A – Prong 2:
Under Prong 2, this judicial exception is not integrated into a practical application. The claims recite the following additional elements: “the sequence being executable error-free by a multi-core processor” and “by a memory bus” merely recite instructions to implement an abstract idea on a generic computer, or merely use a generic computer or computer components as a tool to perform the abstract idea, thus is not a practical application under Prong 2. See MPEP 2106.05(f).
Step 2B:
Under Step 2B, the claims do not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of “the sequence being executable error-free by a multi-core processor” and “by a memory bus” are amount to no more than mere instructions, or generic computer/computer components as a tool to carry out the exception. Accordingly, the claims are not patent eligible under 35 USC 101.
Regarding to claim 2, the limitation “wherein the statistical metrics of the memory access pattern of the sequence of N previous instructions comprise: a memory intensity (Im) corresponding to the ratio of the number of read access instructions (R) or write access instructions (W) to the total number of instructions N; a read/memory ratio (Rwr) corresponding to the ratio of read access instructions (W) to memory access instructions (R, W); and an access Shannon entropy (E) of the memory access pattern (P), representative of the random aspect of the memory addresses accessed” further define the statical metrics of the memory access pattern which recites further mental process
Regarding to claim 3, the limitation “wherein the statistical metrics of the memory access pattern of the sequence of N previous instructions further comprise an interleaving (Iv) of the read access instructions (R) and of the write access instructions (W)” further define the statical metrics of the memory access pattern which recites further mental process.
Regarding to claim 4, the limitation “wherein the rules comprise rules applied after the first rule, in any order: a second test rule if the read/memory ratio (Rwr) is greater than a read/memory-ratio setpoint (Rwr_c), wherein case the N+1th instruction selected is a read access instruction (R), and otherwise, the N+1th instruction selected is a write access instruction (W); a third test rule if the Shannon entropy (Ep) of the memory access pattern (P) is greater than a Shannon-entropy setpoint (Ep_c), wherein case the memory address of the N+1th instruction is selected so as to reduce the entropy E, through employment of an address already in use or an address the distance of which from the previous one is already known, and otherwise, the memory address of the N+1th instruction is selected at random; and a fourth test rule if the interleaving (Iv) is greater than an interleaving setpoint (Iv_c), wherein case the N+1th instruction selected is a read access instruction (R) or a write access instruction (W) of the same type as the Nth instruction, and otherwise, the N+1th instruction selected is a read access instruction (R) or a write access instruction (W) of opposite type to that of the Nth instruction” further define the order of rules which recites further mental process.
Regarding to claim 5, the limitation “integrating the sequence of Nmax instructions in assembly language into an execution loop to generate executable software or a stub” merely apply the abstract idea which is neither a practical application under prong 1, or amount to significantly more under step 2B.
Conclusion
6. The prior art made of record and not relied upon (cited on 892 form) is considered pertinent to application disclosure.
Hu et al. (US 11726671 B2) disclose selecting memory access mode in memory sub-system i.e. memory devices such as non-volatile memory device, involves selecting read mode for use in performance of random operation, and performing random operation using selected read mode to sense data written in set of memory cells.
Chen et al. (US-20020089882-A1) discloses arranging memory access operations to minimize memory bank conflicts between such operations.
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/MARINA LEE/Primary Examiner, Art Unit 2192