DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendments
Acknowledgment is made of the amendment filed August 19, 2026, in which: claims 1, 11, and 16 are amended; claims 9, 10, 13-15, and 17-20 are cancelled; and the rejection of the claims are traversed. Claims 1-8, 11, 12, and 16 are currently pending an Office action on the merits as follows.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 11, and 16 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chung (US 20170062408 A1), in view of Hwu (US 20200359499 A1).
Regarding independent claim 1, Chung teaches an electronic device, having a peripheral area ([0044, “The display panel 100 may include a display area DA including the plurality of pixels 105 and a peripheral area PA surrounding the display area DA.”, Fig. 2, PA]) and comprising: a first data line and a second data line, extending along a first direction ([0044], “…a plurality of data lines D1 to Dm…”, Fig. 8, DL1, DL2]), a first transistor and a second transistor, adjacently disposed in the peripheral area and respectively electrically connected to the first data line and the second data line([0105], “…a plurality of switching elements TFT each connected to a corresponding one of first to third data lines DL1 to DL3…”, Fig. 8, TFT), and a first signal line and a second signal line, extending along the first direction and at least partially disposed between the first transistor and the second transistor ([0045], “…and a plurality of first global signal lines 128 extended lengthwise from the first common line 126 to the display area DA…”, Fig. 8, #128). However, Chung does not teach that the first signal line and the second signal line are different layers, and wherein the first signal line and the second signal line are electrically isolated.
However, in the same field of endeavor, Hwu teaches the first signal line and the second signal line are different layers, and wherein the first signal line and the second signal line are electrically isolated (Fig. 1, SL1, SL2; [0043], " In particular, the first signal lines SL1 and the second signal lines SL2 may be respectively disposed on opposite sides of the flexible substrate 210 and be (electrically) isolated from each other.").
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the electronic device of Chung with the electrically isolated signal lines of Hwu so as "to enable the active devices [transistors]", (Hwu, [0044]).
Claim(s) 2, 5, 6, 7, 8 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chung (US 20170062408 A1) in further view of Hwu (US 20200359499 A1) and Zhang (US 20150318305 A1).
Regarding dependent claim 2, Chung, as previously modified by Hwu, teaches the electronic device according to claim 1. However, as previously combined, they do not teach comprising an insulation layer disposed between the first signal line and the second signal line.
However, in the same field of endeavor, Zhang teaches comprising an insulation layer disposed between the first signal line and the second signal line ([0052], “…and an insulation layer provided between the two conductive layers”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the electronic device as described by the combination of Chung and Hwu with the insulation layer of Zhang “in order to reduce the resistance”, (Zhang,[0058]).
Regarding dependent claim 5, Chung, as modified by Hwu, teaches the electronic device according to claim 1. Chung further teaches a display area adjacent to the peripheral area and a pixel structure disposed in the display area ([0044], “The display panel 100 may include a display area DA including the plurality of pixels 105 and a peripheral area PA surrounding the display area DA”, Fig. 2, DA, #105).
Regarding dependent claim 6, Chung, as previously modified by Hwu, teaches the electronic device according to claim 1. However, as previously combined, they do not teach the pixel structure is implemented by a multi-layer conductive layer, and the first signal line and the second signal line are manufactured by two different layers of the multi-layer conductive layer.
However, in the same field of endeavor, Zhang teaches that the pixel structure is implemented by a multi-layer conductive layer, and the first signal line and the second signal line are manufactured by two different layers of the multi-layer conductive layer ([0063, “As above mentioned, when the signal lines are gate lines, the plurality of conductive layers in different layers comprise a gate metal layer, a data line layer disposed in the gate line region and a pixel electrode layer disposed in the gate line region.”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the electronic device as described by the combination of Chung and Hwu with the multi-layer conductive layer of Zhang so that “the resistance of the signal lines is reduced”, (Zhang, [0068[).
Regarding dependent claim 7, Chung, as previously modified by Hwu, teaches the electronic device according to claim 1. Chung further teaches that the first transistor and the second transistor are arranged in a second direction and there is no other transistor between the first transistor and the second transistor (Fig. 8, TFT (Two transistors corresponding to two data lines are adjacent in a direction perpendicular to the data line direction)).
Regarding dependent claim 8, Chung, as previously modified by Hwu, teaches the electronic device according to claim 1.
However, as previously combined, they do not teach wherein contour orthographic projections of the first signal line and the second signal line on a plane of an X-axis and a Y-axis are substantially aligned with each other.
However, in the same field of endeavor, Zhang teaches wherein contour orthographic projections of the first signal line and the second signal line on a plane of an X-axis and a Y-axis are substantially aligned with each other ([0011], “When the projections of at least two signal lines on the base substrate overlaps, each of the signal line only comprise one conductive layer at the overlapping point.”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the electronic device as described by the combination of Chung and Hwu with the alignment of signal lines of Zhang so that “the conductive layer will be conducted alternately”, (Zhang, [0066]).
Regarding dependent claim 16, Chung, as previously modified by Hwu, teaches the electronic device according to claim 1, and further teaches wherein the first transistor and the second transistor are arranged in at least two columns (Fig. 2, P; [0053], “The pixels P may form a plurality of pixel rows and pixel columns. In some embodiments, each of the pixels P may include first to third sub-pixels.”; Fig. 5, M1, M2; [0077], “In some embodiments, the pixel circuit 105A may include first to third transistors M1 to M3…”).
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chung (US 20170062408 A1) in further view of Zhang (US 20150318305 A1) and Lohstroh (US 4019197 A).
Regarding dependent claim 3, Chung, as previously modified by Hwu, teaches the electronic device according to claim 1. However, as previously combined, they do not teach a separation distance between the first conductive layer and the second conductive layer in a thickness direction is greater than or equal to 0.5 microns.
However, in the same field of endeavor, Lohstroh teaches a separation distance between the first conductive layer and the second conductive layer in a thickness direction is greater than or equal to 0.5 microns (Description (4), “…being separated from the first conductive layer 4 by an at least 0.01 micron thick, in this example approximately 0.015 microns (150 Angstrom) thick, part of the insulating layer 3…”). Given that Lohstroh gives a lower bound of 0.01 microns, the 0.5 micron thickness as claimed is included in Lohstroh’s range.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the electronic device as described by the combination of Chung and Hwu with the thickness of the insulating layer as described by Lohstroh in order to make a barrier “…through which thus no charge carriers can tunnel” (Lohstroh, Description, (4)).
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chung (US 20170062408 A1), in view of Hwu (US 20200359499 A1) and Youn (US 20210159298 A1).
Regarding dependent claim 11, Chung, as previously modified by Hwu, teaches the electronic device according to claim 1. However, as previously combined, they do not teach wherein the first transistor and the second transistor respectively comprise a gate, a source, and a drain.
However, in the same field of endeavor, Youn teaches wherein the first transistor and the second transistor respectively comprise a gate, a source, and a drain ([0065], “…may include a source region, a drain region, and a channel region positioned between the source and drain regions for constituting a first transistor T1 together with a first gate electrode GE1.” [0071], “may include a source region, a drain region, and a channel region positioned between the source and drain regions for constituting a second transistor T2 together with a second gate electrode GE2.”, Fig. 2, SE, GE, DE).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the electronic device as described by the combination of Chung and Hwu with the gate, source, and drain of Youn “for constituting a transistor together with a gate electrode”, (Youn, [0065]).
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chung (US 20170062408 A1), in view of Hwu (US 20200359499 A1), Youn (US 20210159298 A1), and Qing (US 20220077273 A1).
Regarding dependent claim 12, Chung, as previously modified by Hwu and Youn, teaches the electronic device according to claim 11. However, as previously combined, they do not teach wherein the first data line is connected to one of the source and the drain of the first transistor, and the second data line is connected to one of the source and the drain of the second transistor.
However, in the same field of endeavor, Qing teaches wherein the first data line is connected to one of the source and the drain of the first transistor, and the second data line is connected to one of the source and the drain of the second transistor ([0132], “…and a source or drain electrode of the switch transistor is connected to the data line 102 to receive a data signal.”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the electronic device as described by the combination of Chung, Hwu, and Youn with the data line connections of Qing to allow the transistor to receive a data signal (Qing, [0132]).
Conclusion
Pertinent Art
5. The prior art made of record and not relied upon is considered pertinent to the applicant's disclosure:
Kang (US 20190252479 A1), which details a display apparatus including a peripheral area with transistors and data lines.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
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/TIMOTHY JAMES MATTABONI/Examiner, Art Unit 2897 /CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
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