DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103, which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over US 20190165736 A1 (Khesbak), in view of US 20210091796 A1 (US 20210091796 A1) and in further view of US 20150084701 A1 (Perreault).
Regarding Claims 1, 14 and 20:
A communication device comprising: a radio frequency system; and a signal processing circuit coupled to the radio frequency system, wherein the radio frequency system comprises: a tracker module; and a power amplifier that is coupled to the tracker module and is configured to amplify and output a radio frequency transmission signal that is outputted from the signal processing circuit, wherein the power amplifier is disposed on a module laminate, wherein the tracker module further includes: a first IC chip disposed on the module laminate; and a second IC chip configured to control the power amplifier, wherein the first IC chip includes: at least one switch included in a switched-capacitor circuit that is configured to generate a plurality of discrete voltages based on an input voltage; and at least one switch included in a supply modulator that is configured to selectively output at least one of the plurality of discrete voltages to the power amplifier, and wherein the second IC chip is disposed on the module laminate and coupled to the first IC chip (Khesbak: Figs. 1-2, a radio system that comprises a baseband unit, an envelope tracking and adjustment unit, an envelope modulator, and a PA among others; Figs. 2-3A-D illustrate various envelope trackers; Figs. 5A-B are for PA supply voltage vs. time that supply voltage is modulated; Figs. 7-8 and par. 149-157 illustrate a multi-chip module with at least two dies on a substrate 320; “the power amplifier module 351 and/or the envelope tracking module 352 are implemented using one or more instantiations of the module 300 shown in FIGS. 7A-7B”).
Khesbak does not teach explicitly on a laminate based multi-chip module. However, Shinozaki teaches (Shinozaki: e.g., Figs. 2A-B and par. 67, the module board may use “a low temperature co-fired ceramic (LTCC) board having a stacked structure of a plurality of dielectric layers”. Where LTCC is inherently a laminate technology).
It would have been obvious for one of ordinary skill in the art before the effective filling date of the claimed invention was made to modify Khesbak with a laminate based multi-chip module as further taught by Shinozaki. The advantage of doing so is to ensure sufficient isolation between the input and output signals of the power amplifier (Shinozaki: Background).
Khesbak does not teach explicitly on using switched capacitor to supply discrete power levels to PA. However, Perreault teaches (Perreault: Figs. 1-3, 6-7, and par. 4-5 27-34, “The switched-capacitor voltage balancer stage (which may be more generally referred to as a multi-output switched-capacitor voltage converter) functions to regulate relative voltages on a set of capacitors, such that the capacitor voltages with respect to a common potential maintain a desired radiometric relationship. These voltages represent, for example, a set of discrete supply voltages utilized for supply switching. The at least one output switching stage is coupled to rapidly select among these ratiometrically-related voltage levels and supply at least one output voltage. The output can be selected directly as one of these voltages, or additional filtering or other processing can be performed to provide a continuously-variable output voltage signal. Thus, the magnetic stage regulates the voltage, while the SC voltage balancer stage maintains the voltage ratios”).
It would have been obvious for one of ordinary skill in the art before the effective filling date of the claimed invention was made to modify Khesbak with using switched capacitor to supply discrete power levels to PA as further taught by Perreault. The advantage of doing so is providing means to create multiple supply levels from a single supply input, possibly including regulation of the multiple discrete supply voltages; and providing means to rapidly and efficiently switch among the discrete supply voltage (Perreault: Background).
Regarding Claims 2 and 15, Khesbak as modified further teaches:
The tracker module according to Claim 1, further comprising another module laminate that is separated from the module laminate, and the power amplifier is disposed on the other module laminate (Khesbak: Figs. 7-8 and par. 149-157 illustrate a multi-chip module with at least two dies on a substrate 320; “the power amplifier module 351 and/or the envelope tracking module 352 are implemented using one or more instantiations of the module 300 shown in FIGS. 7A-7B”).
Regarding Claims 3 and 16, Khesbak as modified further teaches:
The tracker module according to Claim 1, wherein: the module laminate has a first principal surface and a second principal surface that is opposite to the first principal surface, the tracker module further comprises an external connection terminal disposed on the second principal surface of the module laminate, the first IC chip is disposed on the second principal surface of the module laminate, and the second IC chip is disposed on the first principal surface of the module laminate (Shinozaki: Figs. 2B, 3B; Khesbak: Figs, 7A-B).
Regarding Claims 4 and 17, Khesbak as modified further teaches:
The tracker module according to Claim 1, wherein: the module laminate has a first principal surface and a second principal surface that is opposite to the first principal surface, the tracker module further comprises an external connection terminal disposed on the second principal surface of the module laminate, the first IC chip is disposed on the first principal surface of the module laminate, and the second IC chip is disposed on the second principal surface of the module laminate (Shinozaki: Figs. 2B, 3B; Khesbak: Figs, 7A-B).
Regarding Claims 5 and 18, Khesbak as modified further teaches:
The tracker module according to Claim 1, wherein: the module laminate has a first principal surface and a second principal surface that is opposite to the first principal surface, and the first IC chip and the second IC chip are disposed on one of the first principal surface and the second principal surface of the module laminate (Shinozaki: Figs. 2B, 3B; Khesbak: Figs, 7A-B, where placing the 1st chip and 2nd chip on the same surface or different surface depend on the design and application constrains and requirements).
Regarding Claim 6, Khesbak as modified further teaches:
The tracker module according to Claim 5, wherein each of the first IC chip and the second IC chip is a respective integrated circuit (Khesbak: Figs, 7A-B, two dies on a module package).
Regarding Claims 7 and 19, Khesbak as modified further teaches:
The tracker module according to Claim 1, further comprising a signal generation unit that is configured to generate a control signal for controlling the supply modulator based on an envelope of a radio frequency signal (Perreault: par. 28 “control and level-shifting circuitry required in this exemplary implementation are simpler, require lower complexity and die area and are more easily implemented than in other circuits and can be easily implemented on the same CMOS die”).
Regarding Claim 8, Khesbak as modified further teaches:
The tracker module according to Claim 7, wherein the signal generation unit is included in the first IC chip (Shinozaki: 2A, 2C, 3A illustrate different chip partition and integration, where separating and integrating functions into a chip set is known processing in electronic system).
Regarding Claim 9, Khesbak as modified further teaches:
The tracker module according to Claim 1, further comprising a control terminal that is coupled between the second IC chip and the power amplifier, and is configured to output a control signal generated from the second IC chip to the power amplifier for controlling the power amplifier (Khesbak: Figs, 7A-B).
Regarding Claim 10, Khesbak as modified further teaches:
The tracker module according to Claim 9, wherein the control terminal is disposed on the module laminate and overlaps the second IC chip in a thickness direction of the module laminate (Shinozaki: par. 74-75, module board 91, PA control circuit 13 and switch 52 at least partially overlap, where overlapping chips/dies are known optimization procedures in RF module).
Regarding Claim 11, Khesbak as modified further teaches:
The tracker module according to Claim 1, further comprising a first circuit component that is disposed on the module laminate, coupled to the first IC chip, and includes at least one capacitor of the switched-capacitor circuit (Perreault: par. 28: “the implementation requires a number of off-die connections which is relatively small compared with the number of off-die connections required in prior art approaches, principally at nodes connecting to C.sub.1-C.sub.4 and C.sub.T1-C.sub.T3”).
Regarding Claim 12, Khesbak as modified further teaches:
The tracker module according to Claim 11, further comprising a second circuit component that is disposed on the module laminate and includes at least one capacitor of the switched-capacitor circuit (Khesbak: Figs. 7A-B, par. 150, The packaged module 300 includes a first die 301, a second die 302, surface mount components 303) .
Regarding Claim 13, Khesbak as modified further teaches:
The tracker module according to Claim 12, further comprising a third circuit component that is disposed on the module laminate and includes the power amplifier (Khesbak: Figs. 7-8 and par. 149-157 illustrate a multi-chip module with at least two dies on a substrate 320; “the power amplifier module 351 and/or the envelope tracking module 352 are implemented using one or more instantiations of the module 300 shown in FIGS. 7A-7B”).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ZHITONG CHEN whose telephone number is (571) 270-1936. The examiner can normally be reached on M-F 9:30am - 5pm.
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/ZHITONG CHEN/
Primary Examiner, Art Unit 2649
Prosecution Insights