Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claims 1-14 are presented in the case.
Priority
Acknowledgment is made of applicant's claim for foreign priority based on application JP2021-146742 filed in Japan on 09/09/2021. Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statements submitted on 03/07/2024 and 05/18/2026 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: "Machine Learning Device with Shared Computation Circuit".
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) are: “a data conversion unit configured to convert time series data inputted thereto into frequency feature quantity data;” and “a machine learning inference unit configured to perform machine learning inference based on the frequency feature quantity data;” in claim 1.
“a learning unit configured to perform machine learning of the machine learning inference unit, and” in claim 12.
Because these claim limitations are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, they are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof. See PGPUB ¶23 and ¶33.
If applicant does not intend to have these limitations interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitations to avoid them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitations recite sufficient structure to perform the claimed function so as to avoid hem being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 3 and 13 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 3 recites the phrase “wherein the types are at least two of a matrix, a vector, and a scalar.”. It is unclear whether this should be interpreted as supporting two types of input or are two types needed as input at a time.
Claim 13 recites the phrase “the first step in a subsequent execution of the computation processing is started before the computation processing is completed.”. It is unclear whether this is referring to while current processing or preceding a prior execution.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-14 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more. The analysis of the claims will follow the 2019 Revised Patent Subject Matter Eligibility Guidance, 84 Fed. Reg. 50 (“2019 PEG”)
Claim 1 has the following abstract idea analysis.
Step 1: The claim is directed to “a device (apparatus)”. The claim is directed to the statutory categories accordingly.
Step 2A Prong 1: claim recites the abstract idea limitation of "convert time series data inputted thereto into frequency feature quantity data;". The limitation includes mathematical concept see MPEP § 2106.04(a)(2)) where it cites textual recitation can still be mathematical "determining a ration of A to B". The specification also provides example math using Fourier and cosine functions (See USPGPUB ¶21). See USPTO 2024 example 48 where STFT conversion and determining vectors by formula were treated as mathematical operations. Thus, the limitation is an abstract idea in the “mathematical concept”. Other sections of the claims such as "data conversion unit" "machine learning inference unit", "machine learning inference" and "a computation circuit unit" are advanced processes, too generic or high level to be listed as a judicial exception given the available descriptions and MPEP comparisons.
Step 2A Prong 2: The judicial exceptions recited in these claims are not integrated into a practical application. Merely invoking "data conversion unit" "machine learning inference unit", "machine learning inference" and "a computation circuit unit" does not yield eligibility. Claims are still in line with mathematical concepts such as claim 1 are not specific to a practical application. The additional elements, as such are processors and instructions which do not include specialized hardware. See MPEP § 2106.05(a). Math is just being used to produce a result. Claim 1 does not include a more specific field but even doing so may not be sufficient to overcome the abstract idea rejection. Merely applying an math to a field without an advancement in the new field or new hardware is ineligible. See MPEP § 2106.05(h).
Step 2B: The claim does not contain significantly more than their judicial exceptions. Processors, memory and other hardware are in their standard forms in the field. Note generic processors are recited not new quantum processors. These additional elements are well-understood, routine, and conventional activity, see MPEP 2106.05(d)(II). Claims lacks any particular "how" or algorithm for a solution in a field in a novel way. Claims require more specificity on processes that would be incapable of simple mathematics, mental processes or use more substantial structure than conventional devices such as non-textbook implementations.
Regarding claims 2-14 they merely narrow the previously recited abstract idea limitations with more abstract concepts and/or routine fundamental processes. For the reasons described above with respect to claim 1 this judicial exception is not meaningfully integrated into a practical application, or significantly more than the abstract idea. Abstract idea steps 1, 2A prong 1 and 2 remain the same as independent analysis above. See specification for more practical application concepts as none are seen in claims 2-14.
With respect to step 2B These claims disclose similar limitations described for the dependent claims above and do not provide anything significantly more than organizing human activity concepts. Claims 2-14 recite the additional elements of "the computation circuit unit is configured to be capable of executing computation by using an operator configured to output a computation output based on a first computation input and a second computation input, and the machine learning device includes a control unit configured to be capable of executing first control to select at least either a type or a size of at least either the first computation input or the second computation input and second control to select a method of computation to be executed by the operator. wherein the types are at least two of a matrix, a vector, and a scalar. wherein the control unit is a processor configured to execute the first control and the second control by executing a program. wherein the control unit is a control circuit configured to execute the first control and the second control based on communication with an outside of the machine learning device. wherein the data conversion unit is configured to convert the time series data into the frequency feature quantity data via a Hadamard transform, by the computation circuit unit computing a product of a Hadamard matrix and an input vector by using an adder and a subtractor. wherein the data conversion unit is configured to convert the time series data into the frequency feature quantity data via a discrete Fourier transform or a discrete cosine transform, by the computation circuit unit computing a product of a conversion matrix having a trigonometric function value as a table value and an input vector. wherein the machine learning inference unit is configured to perform machine learning inference by using a neural network, the neural network includes a fully-connected layer, and the computation circuit unit is configured to execute computation in the fully-connected layer. wherein the computation circuit unit is configured to compute, in the fully-connected layer, a product of a weight matrix and an input vector. wherein the computation circuit unit is configured to execute, in the fully-connected layer, via max (a, b) to output whichever of a and b is the larger, computation of an activation function f(x)=max (x, 0). wherein the computation circuit unit is configured to execute, in the fully-connected layer, via max (a, b) to output whichever of a and b is the larger and min (a, b) to output whichever of a and b is the smaller, computation of an activation function f(x)=min (max (0.25x+0.5,0), 1). wherein there is further included a learning unit configured to perform machine learning of the machine learning inference unit, and the computation circuit unit is configured to be commonly used by the data conversion unit, the machine learning inference unit, and the learning unit. wherein the computation circuit unit is configured to be capable of executing computation by using an operator configured to output a computation output based on a first computation input and a second computation input, computation processing executed by the computation circuit unit includes a first step of calculating a memory address of where each of the first computation input, the second computation input, the computation output, and data regarding the operator is stored, a second step of reading each of the first computation input, the second computation input, and the data regarding the operator from the memory address, a third step of executing computation based on the first computation input, the second computation input and the operator, and a fourth step of writing the computation output to the memory address, and the first step in a subsequent execution of the computation processing is started before the computation processing is completed capable of having vibration data from a sensor inputted thereto as the time series data.". These elements are more abstract concepts, generic applications to a field of use or well-understood, routine, conventional activity (see MPEP § 2106.05(d) and can't be simply appended to qualify as significantly more or being a practical application. What type of application, or structure of components beyond generic machine learning is still unknown for these claims. Therefore claims 2-14 also recites abstract ideas that do not integrate into a practical application or amount to significantly more than the judicial exception, and are rejected under U.S.C. 101.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 7, 12 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Schuster et al. (US 20210116904 A1) hereinafter Schuster in view of Langhammer (US 20210326111 A1)
As to independent claim 1, Schuster teaches a machine learning device, comprising: [ML based controller Fig. 7 700 ¶17-18]
a data conversion unit [Data prep module Fig. 7 712 ¶116] configured to convert time series data inputted thereto into frequency feature quantity data; [manipulates vibration timewave (time-series ¶114) into proper format FFT (frequency feature) ¶116-117 "data set preparation module 712 performs fast Fourier transforms (FFTs) for each timewave associated with a vibration data set. The FFTs can represent the timewaves in a frequency domain such that the vibration data sets can be more easily processed by ML models 714"]
a machine learning inference unit [ML Model Fig. 7 714 ¶120] configured to perform machine learning inference based on the frequency feature quantity data; and [models infer (predict) probability of abnormality ¶120 "ML models that can determine probabilities that a vibration data set includes at least one abnormality based on FFT spectra. For example, an ML model of ML model 714 may predict"]
a computation circuit unit [processing unit Fig. 7 702 ¶111]
Schuster does not specifically teach a computation circuit unit configured to be commonly used by the data conversion unit and the machine learning inference unit.
However, Langhammer teaches a computation circuit unit configured to be commonly used by the data conversion unit and the machine learning inference unit. [A DSP that performs AI applications (ML ) and traditional DSP (conversion ¶35 including FFT ¶62) reducing units needed ¶24 "DSP blocks may perform virtual artificial intelligence applications in addition to traditional DSP functionalities that utilize FP32 values and INT16 values using the same DSP block logic components"]
Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the anomaly detection by Schuster by incorporating the computation circuit unit configured to be commonly used by the data conversion unit and the machine learning inference unit disclosed by Langhammer because both techniques address the same field of machine learning and by incorporating Langhammer into Schuster improves computational density and reduces power consumption [Langhammer ¶24].
As to dependent claim 7, the rejection of claim 1 is incorporated, Schuster and Langhammer further teach wherein the data conversion unit is configured to convert the time series data into the frequency feature quantity data via a discrete Fourier transform or a discrete cosine transform, [Schuster discrete cosine and FFT ¶119 "perform discrete cosine transforms"]
by the computation circuit unit computing a product of a conversion matrix having a trigonometric function value as a table value and an input vector. [Langhammer matrix and products ¶33 and tables ¶28]
As to dependent claim 12, the rejection of claim 1 is incorporated, Schuster and Langhammer further teach wherein there is further included a learning unit configured to perform machine learning of the machine learning inference unit, and the computation circuit unit is configured to be commonly used by the data conversion unit, the machine learning inference unit, and the learning unit. [Schuster processing circuit Fig. 7 702 (computation) including data prep (conversion) Fig. 7 712 and ML inference (Fig. 7 714) ¶111, ¶120 "ML model of ML model 714 may predict"]
As to dependent claim 14, the rejection of claim 1 is incorporated, Schuster and Langhammer further teach configured to be capable of having vibration data from a sensor inputted thereto as the time series data. [Schuster vibration data from accelerometers (sensors) ¶114]
Claims 2-5 are rejected under 35 U.S.C. 103 as being unpatentable over Schuster in view of Langhammer, as applied in the rejection of claim 1 above, and further in view of Burdick et al. (US 20120226639 A1) hereinafter Burdick.
As to dependent claim 2, Schuster and Langhammer teach the method of claim 1 above that is incorporated,
Schuster and Langhammer further teach wherein the computation circuit unit is configured to be capable of executing computation by using an operator configured to output a computation output based on a first computation input and a second computation input, and [Langhammer DSP computes products (operator) based on 2 inputs ¶31-32 " determine the product of the inputted data"]
the machine learning device includes a control unit configured to be capable of executing first control to select at least either a type or a size of at least either the first computation input or the second computation input and [Langhammer set sizes/precision (type/size) ¶50 "values of a first size (e.g., INT16 values, FP32 values) may be converted into values of a smaller size (e.g., INT8 values, INT9 values),"]
Schuster and Langhammer do not specifically teach second control to select a method of computation to be executed by the operator.
However, Burdick teaches second control to select a method of computation to be executed by the operator. [select operators for method of computation (multiplication, division, addition etc.) ¶79, ¶26 " Arithmetic operators include multiplication, division, addition, and subtraction."]
Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the computation circuits disclosed by Schuster and Langhammer by incorporating the second control to select a method of computation to be executed by the operator disclosed by Burdick because all techniques address the same field of machine learning and by incorporating Burdick into Schuster and Langhammer reduces manual tuning and provides improved execution strategies for ML algorithms [Burdick ¶2-4].
As to dependent claim 3, the rejection of claim 2 is incorporated, Schuster, Langhammer and Burdick further teach wherein the types are at least two of a matrix, a vector, and a scalar. [Burdick ¶22 " three main data types: matrices, vectors, and scalars"]
As to dependent claim 4, the rejection of claim 2 is incorporated, Schuster, Langhammer and Burdick further teach wherein the control unit is a processor configured to execute the first control and the second control by executing a program. [Langhammer program (OpenCL) " designer may specify a high-level program to be implemented, such as an OpenCL program"]
As to dependent claim 5, the rejection of claim 2 is incorporated, Schuster, Langhammer and Burdick further teach wherein the control unit is a control circuit configured to execute the first control and the second control based on communication with an outside of the machine learning device. [Langhammer communicates with a host outside of DSP with ML ¶26 " host program 22, the host 18 may communicate instructions from the host program 22 to the integrated circuit device 12 via a communications link 24, which may be, for example, direct memory access (DMA) communications or peripheral component interconnect express (PCIe) communications. In some embodiments, the kernel programs 20 and the host 18 may enable configuration of one or more DSP blocks 26 on the integrated circuit device 12"]
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Schuster in view of Langhammer, as applied in the rejection of claim 1 above, and further in view of Carbajal Ipenza (US 10158375 B1)
As to dependent claim 6, Schuster and Langhammer teach the method of claim 1 above that is incorporated,
Schuster and Langhammer do not specifically teach wherein the data conversion unit is configured to convert the time series data into the frequency feature quantity data via a Hadamard transform, by the computation circuit unit computing a product of a Hadamard matrix and an input vector by using an adder and a subtractor.
However, Carbajal Ipenza teaches wherein the data conversion unit is configured to convert the time series data into the frequency feature quantity data via a Hadamard transform, by the computation circuit unit computing a product of a Hadamard matrix and an input vector by using an adder and a subtractor. [Hadamard with adder and a subtractor Col. 3 ln. 30-52 "FWH requires only N.Math.log.sub.2(N) additions or subtractions as further described herein"]
Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the computation circuits disclosed by Schuster and Langhammer by incorporating the wherein the data conversion unit is configured to convert the time series data into the frequency feature quantity data via a Hadamard transform, by the computation circuit unit computing a product of a Hadamard matrix and an input vector by using an adder and a subtractor disclosed by Carbajal Ipenza because all techniques address the same field of machine learning and by incorporating Carbajal Ipenza into Schuster and Langhammer provide a less expensive and complex solution supporting more diverse applications [Carbajal Ipenza Col. 1 ln. 34-46]
Claims 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Schuster in view of Langhammer, as applied in the rejection of claim 1 above, and further in view of Ross et al. (US 20160342891 A1) hereinafter Ross.
As to dependent claim 8, Schuster and Langhammer teach the method of claim 1 above that is incorporated,
Schuster and Langhammer do not specifically teach wherein the machine learning inference unit is configured to perform machine learning inference by using a neural network, the neural network includes a fully-connected layer, and the computation circuit unit is configured to execute computation in the fully-connected layer.
However, Ross teaches wherein the machine learning inference unit is configured to perform machine learning inference by using a neural network, the neural network includes a fully-connected layer, and the computation circuit unit is configured to execute computation in the fully-connected layer. [Fully-connected neural network layer ¶23, ¶59]
Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the computation circuits disclosed by Schuster and Langhammer by incorporating the wherein the machine learning inference unit is configured to perform machine learning inference by using a neural network, the neural network includes a fully-connected layer, and the computation circuit unit is configured to execute computation in the fully-connected layer disclosed by Ross because all techniques address the same field of machine learning and by incorporating Ross into Schuster and Langhammer enhances efficiency and speed while reducing power of ML units [Ross ¶7]
As to dependent claim 9, the rejection of claim 8 is incorporated, Schuster, Langhammer and Ross further teach wherein the computation circuit unit is configured to compute, in the fully-connected layer, a product of a weight matrix and an input vector. [Ross product weight and input ¶6]
Claim 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Schuster in view of Langhammer and Ross, as applied in the rejection of claim 8 above, and further in view of Kang et al (US 20210264247 A1) hereinafter Kang.
As to dependent claim 10, Schuster, Langhammer and Ross teach the method of claim 1 above that is incorporated,
Schuster, Langhammer and Ross do not specifically teach wherein the computation circuit unit is configured to execute, in the fully-connected layer, via max (a, b) to output whichever of a and b is the larger, computation of an activation function f(x)=max (x, 0).
However, Kang teaches wherein the computation circuit unit is configured to execute, in the fully-connected layer, via max (a, b) to output whichever of a and b is the larger, computation of an activation function f(x)=max (x, 0). [ReLU activation filter with Max function ¶24]
Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the computation circuits disclosed by Schuster, Langhammer and Ross by incorporating wherein the computation circuit unit is configured to execute, in the fully-connected layer, via max (a, b) to output whichever of a and b is the larger, computation of an activation function f(x)=max (x, 0). the disclosed by Kang because all techniques address the same field of machine learning and by incorporating Kang into Schuster, Langhammer and Ross facilitates further efficiency withing neural networks for accurate low-cost outputs [Kang ¶18-19].
As to dependent claim 11, Schuster, Langhammer and Ross teach the method of claim 1 above that is incorporated,
Schuster, Langhammer and Ross further teach min (a, b) to output whichever of a and b is the smaller, computation of an activation function f(x)=min (max (0.25x+0.5,0), 1). [Schuster ReLU (max) and Sigmoid (min) combo ¶171 "all layers use ReLU activation, except for the binary classification layer which uses “sigmoid.” L2 regularization (lambda=1.0)"]
Schuster, Langhammer and Ross do not specifically teach wherein the computation circuit unit is configured to execute, in the fully-connected layer, via max (a, b) to output whichever of a and b is the larger, computation of an activation function f(x)=max (x, 0).
However, Kang teaches wherein the computation circuit unit is configured to execute, in the fully-connected layer, via max (a, b) to output whichever of a and b is the larger, computation of an activation function f(x)=max (x, 0). [ReLU activation filter with Max function ¶24]
Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the computation circuits disclosed by Schuster, Langhammer and Ross by incorporating wherein the computation circuit unit is configured to execute, in the fully-connected layer, via max (a, b) to output whichever of a and b is the larger, computation of an activation function f(x)=max (x, 0). the disclosed by Kang because all techniques address the same field of machine learning and by incorporating Kang into Schuster, Langhammer and Ross facilitates further efficiency withing neural networks for accurate low-cost outputs [Kang ¶18-19].
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Schuster in view of Langhammer, as applied in the rejection of claim 1 above, and further in view of Sodani et al. (US 10896045 B2) hereinafter Sodani.
As to dependent claim 13, Schuster and Langhammer teach the method of claim 1 above that is incorporated,
Schuster and Langhammer further teach wherein the computation circuit unit is configured to be capable of executing computation by using an operator configured to output a computation output based on a first computation input and a second computation input, computation processing executed by the computation circuit unit includes [Langhammer DSP computes products (operator) based on 2 inputs ¶31-32 " determine the product of the inputted data"]
Schuster and Langhammer do not specifically teach a first step of calculating a memory address of where each of the first computation input, the second computation input, the computation output, and data regarding the operator is stored, a second step of reading each of the first computation input, the second computation input, and the data regarding the operator from the memory address, a third step of executing computation based on the first computation input, the second computation input and the operator, and a fourth step of writing the computation output to the memory address, and the first step in a subsequent execution of the computation processing is started before the computation processing is completed.
However, Sodani teaches a first step of calculating a memory address of where each of the first computation input, the second computation input, the computation output, and data regarding the operator is stored, [starting address and number of lines Col. 9 ln. 40-50]
a second step of reading each of the first computation input, the second computation input, and the data regarding the operator from the memory address, [streamers read and feed operator Fig.7 704, 706 Col. 27 ln. 28-42]
a third step of executing computation based on the first computation input, the second computation input and the operator, and [operator 702 performs operation of input streams Col. 27 ln. 28-65]
a fourth step of writing the computation output to the memory address, and [output stored in a buffer Fig. 7 712 Col. 27-28 ln. 28-21]
the first step in a subsequent execution of the computation processing is started before the computation processing is completed. [fetch ahead (start before computation is completed) Col. 14 ln. 22-38 " A register to fetch ahead next portions of the A matrix before they are needed "]
Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the computation circuits disclosed by Schuster and Langhammer by incorporating the a first step of calculating a memory address of where each of the first computation input, the second computation input, the computation output, and data regarding the operator is stored, a second step of reading each of the first computation input, the second computation input, and the data regarding the operator from the memory address, a third step of executing computation based on the first computation input, the second computation input and the operator, and a fourth step of writing the computation output to the memory address, and the first step in a subsequent execution of the computation processing is started before the computation processing is completed disclosed by Sodani because all techniques address the same field of machine learning and by incorporating Sodani into Schuster and Langhammer improves efficiency by reducing the work or overhead needed to be executed [Sodani Col. 1-2 ln. 46-19].
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Applicant is required under 37 C.F.R. § 1.111(c) to consider these references fully when responding to this action.
Bunazawa et al. (US 12024180 B2) teaches abnormality determination using machine learning and time-series data (See Col. 1 ln. 41-57).
It is noted that any citation to specific pages, columns, lines, or figures in the prior art references and any interpretation of the references should not be considered to be limiting in any way. A reference is relevant for all it contains and may be relied upon for all that it would have reasonably suggested to one having ordinary skill in the art. In re Heck, 699 F.2d 1331, 1332-33, 216 U.S.P.Q. 1038, 1039 (Fed. Cir. 1983) (quoting In re Lemelson, 397 F.2d 1006, 1009, 158 U.S.P.Q. 275, 277 (C.C.P.A. 1968)).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Beau Spratt whose telephone number is 571 272 9919. The examiner can normally be reached 8:30am to 5:00pm (PST).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jennifer Welch can be reached at 571 272 7212. The fax phone number for the organization where this application or proceeding is assigned is 571 483 7388.
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/BEAU D SPRATT/Primary Examiner, Art Unit 2143
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