CTNF 18/598,692 CTNF 101694 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 1-9 are rejected under 35 U.S.C. 103 as being unpatentable over Nomura (2023/0208360 A1) in view of Puscasu (2019/0068144 A1) . Regarding claim 1: Nomura, Fig. 19; (paragraph 139-140, 155) teaches an amplifier circuit (100F) comprising: an input stage (110F) having a non-inverting input (INP) and an inverting input (INN) for receiving a differential input voltage (INP- INN), the input stage (110F) being configured to provide an output signal (Vb1, Vb2) that represents the differential input voltage (INP-INN), (page 8, paragraph [0139], lines 5 – 8); an output stage (130, 130F) configured to receive, as input signal, the output signal (Vb1, Vb2) of the input stage (110, 110F) and further configured to provide, at an output (OUT), an output voltage (OUT) based on the input signal; (paragraphs 140, 156-157); Normura also teaches a feed-forward circuit (150B, 150D) is configured to activate a current path coupled to the output (OUT) to provide additional output current (IAUX). Nomura also teaches the assist circuitry turning on when a control voltage exceeds a threshold condition and turning off when the control voltage falls below the threshold condition (paragraph [0090]). However, Nomura does not explicitly teach a feed-back path. Puscasu, Fig. 2, teaches a feed-back path that couples the output (OUT) of the output stage (AMP 234) with the inverting input (IN-) of the input stage (AMP 224), (Puscasu, page 4, paragraph [0030], lines 2–4) It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to incorporate the feedback path of Puscasu into Nomura to provide feedback from the output to the inverting input in order to improve control of the amplifier output. Regards to Claim 2: Puscasu, Fig. 2, further teaches the amplifier circuit of wherein the inverting input (IN-) is connected to a first input node (210) via a first resistor (214) and the non-inverting input (IN+) is connected to a second input node (208) via a second resistor (212), and wherein the second input node (208) and the first input node (210) are connected by a current sense resistor (206). Regards to Claim 3: Puscasu, Fig. 2, further teaches wherein the feed-back path includes a third resistor (218) (Puscasu, page 4, paragraph [0030], lines 2–4). Claim 4: Puscasu, Fig. 2, further teaches wherein the non-inverting input (IN+) is connected to a reference voltage source signal (REF) via a fourth resistor (216) (paragraph [0030], lines 10-11). Regarding Claim 5: Nomura, Fig. 5, further teaches wherein the current path of the feed-forward circuit (150A, 150B, 150D) includes controllable current sources (CS11, CS12, CS21, CS22) coupled to the output of the output stage (OUT). Further, Nomura teaches activation and deactivation of the assist circuitry based on comparison of a control voltage to a threshold condition, wherein activation occurs when a control voltage crosses a predetermined threshold condition (paragraphs [0088], line 1, [0090], Line1-4, [0092] lines 7-11, [0095] lines 3-7). Regarding Claim 6: Nomura, Fig. 19, further teaches an output stage (130F) including source-follower (paragraph [0107], lines 1-2, [0140] lines 1-2) transistors (MH and ML) configured to drive output node OUT. Regarding Claim 7: Nomura, Fig. 19, further teaches the source follower comprising an n-channel field effect transistor (ML) (paragraph [0033] line 1-2, [0056], line 6-7), and teaches assist circuit (150A) becoming active in a sink mode and sinking auxiliary current (IAUX) from output terminal (OUT) (paragraph [0088], lines 1-3, [0092], lines 6-11), wherein activation occurs when a control voltage falls below a predetermined voltage condition [0095]. Also, as taught by Nomura, the differential input stage 110 generates intermediate signal Vb from differential input signals Vp and Vn, and Vb is applied as gate voltage VgL. Accordingly, the disclosed condition in which VgL falls below predetermined voltage Vm [0095] corresponds to the claimed differential input voltage falling below a threshold value. Regarding Claim 8 Nomura, Fig. 19, further teaches wherein the source follower comprises of a p-channel field effect transistor (MH) (paragraph [0038] line 1-2, [0056], line 4). Furthermore, Nomura teaches assist circuit 150C becoming active in a source mode and sourcing auxiliary current IAUX from output terminal OUT (112, [0116], wherein activation occurs when a control voltage exceeds a predetermined voltage condition (paragraphs [0114]-[0116]). Also, as taught by Nomura, the differential input stage 110 generates intermediate signal Vb from differential input signals Vp and Vn (paragraph [0055]), and the control voltage used to activate the assist circuitry is derived from that differential input signal path. Accordingly, the disclosed condition in which the control voltage exceeds a predetermined voltage condition (paragraphs [0114-0116]) corresponds to the claimed differential input voltage exceeding a threshold value. Regarding Claim 9: Nomura, Fig. 19, teaches A method comprising: providing, by an input stage (110F) of an amplifier (AMP), an output signal (Vb1, Vb2) that represents a differential input voltage (INP-INN) of the input stage (110F); providing, by an output stage (130F) of the amplifier (100F), an output voltage (OUT) based on the output signal (Vb1, Vb2) of the input stage (110F) at an amplifier output (OUT), and activating a current path coupled to the amplifier output (OUT) to provide an additional output current (IAUX) when assist circuits (150B, 150D) provide auxiliary current to output node OUT when activated (paragraphs [0088], [0092], [0116], when the differential input voltage (Vp-Vn) crosses a threshold value (Vth). However, Nomura does not teach a feedback path coupling the amplifier output (OUT) with an inverting input of the input stage. Puscasu, Fig. 2, teaches a feedback path that couples the output (OUT) of output stage (234) with the inverting input (IN-) of the input stage (224). It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to incorporate the feedback path of Puscasu into Nomura in order to improve control of the amplifier output . 07-21-aia AIA Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Puscasu (2019/0068144 A1) in view of Nomura (2023/0208360 A1) . Claim 10: A current sense amplifier (CSA 200) comprising: a first input node (210) and a second input node (208) configured to sense a voltage drop, a differential voltage across sense resistor (206)) across a current sense resistor (206); an input stage (224) including an inverting input (IN-), which is coupled to the first input node (210) via a first resistor (214), and a non-inverting input (IN+), which is coupled to the second input node (208) via a second resistor (212), wherein the input stage (224) is configured to provide an output signal to output stage (234) that represents a differential input voltage applied to input terminals (208, 210) received at the inverting input (IN-) and the non-inverting inputs (IN+); a feed-back path including resistor (218) that couples the output (OUT) of the output stage (234) with the inverting input (IN-) of the input stage (224). However, Puscasu does not teach an output stage that includes a source follower. Nomura, Fig. 19, teaches an output stage (130F) that includes a source follower (transistors MH, ML), (paragraph [0140], configured to receive, as input signal, the output signal (Vb1, Vb2) of the input stage (110F), (paragraph [0139]) and further configured to provide, at an amplifier output (OUT), an output voltage (OUT) based on the input signal (paragraphs [0139]-[0140]; Norma further teaches a feed-forward circuit (150B, 150D) is configured to activate a current path coupled to the output (OUT) to provide an additional output current (IAUX) (paragraphs [0088], [0092] is provided when a control voltage reaches a predetermined voltage condition corresponding to the claimed differential input voltage crossing a threshold value (paragraphs [0093]-[0095]. It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to modify the current sense amplifier of Puscasu to incorporate the source-follower output stage and feed-forward circuitry taught by Nomura in order to improve output driving capability and control of the amplifier output. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATASHA Y MARANO whose telephone number is (571)272-9512. The examiner can normally be reached Mon - Fri 7:30am - 3:30pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Han can be reached at 571-272-2078. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. NATASHA Y. MARANO Examiner Art Unit 2843 /JOHN W POOS/Primary Examiner, Art Unit 2843 Application/Control Number: 18/598,692 Page 2 Art Unit: 2843 Application/Control Number: 18/598,692 Page 3 Art Unit: 2843 Application/Control Number: 18/598,692 Page 4 Art Unit: 2843 Application/Control Number: 18/598,692 Page 5 Art Unit: 2843
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