Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendments
Examiner acknowledges the amendments to claims 1, 9, and 10
Examiner acknowledges the cancellation of claim 6
Examiner acknowledges the new claims 11, 12, and 13
Response to Arguments
Applicant’s arguments, see pages 2-8, filed August 4, 2026, with respect to the rejection of claim 1-5, 7-10 under Nomura (US 2023/0208360 A1) in view of Puscasu (US 2019/0068144 A1), hereafter referred to as Nomura and Puscasu, respectively, have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground of rejection is made in view of Tsai.
Applicant’s arguments with respect to newly added claims 11-13 have also been fully considered. The cited prior art of record does not teach or suggest the additional limitations recited in claims 11-13. Concerning generation of a replica current and an offset current and driving a controllable current source based on a difference between the replica current and the offset current. Accordingly, claims 11-13 are addressed separately below.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1-5, 7-9 is rejected under 35 U.S.C. 103 as being unpatentable over Nomura (US 2023/0208360 A1) in view of Puscasu (US 2019/0068144 A1) in further view of Tsai (US 10613560 B2).
Regarding claim 1: Nomura, Fig. 19, (paragraph 139-140, 155) teaches an amplifier circuit (100F) comprising: an input stage (110F) having a non-inverting input (INP) and an inverting input (INN) for receiving a differential input voltage (INP- INN), the input stage (110F) being configured to provide an output signal (Vb1, Vb2) that represents the differential input voltage (INP-INN), (page 8, paragraph [0139], lines 5 – 8); an output stage (130, 130F) configured to receive, as input signal, the output signal (Vb1, Vb2) of the input stage (110, 110F) and further configured to provide, at an output (OUT), an output voltage (OUT) based on the input signal; (paragraphs 140, 156-157); Normura, also teaches a feed-forward circuit (150B, 150D) is configured to activate a current path coupled to the output (OUT) to provide additional output current (IAUX). Nomura also teaches the assist circuitry turning on when a control voltage exceeds a threshold condition and turning off when the control voltage falls below the threshold condition (paragraph [0090]).
However, Nomura does not explicitly teach a source follower and a feed-back path that couples the output of the output stage with the inverting input of the input stage.
Puscasu, Fig. 2, teaches a feed-back path that couples the output (OUT) of the output stage
(AMP 234) with the inverting input (IN-) of the input stage (AMP 224), (Puscasu, page 4, paragraph [0030], lines 2–4).
It would have been obvious to one of ordinary skill in the art at the time the invention was
effectively filed to incorporate the feedback path of Puscasu into Nomura to provide feedback from the output to the inverting input in order to improve control of the amplifier output.
However, Normura in combination with Puscasu does not teach wherein the output stage includes a source follower.
Tsai, fig. 2, discloses a buffer stage (200) that includes a source follower (250), wherein the source follower (250) includes a first N-type transistor (MN1) having a first terminal coupled to an output node (NOUT) and a control terminal coupled to a first node (N1) (column 5, lines 28-36).
It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to further modify the output stage of the amplifier of Nomura as modified by Puscasu, to include the source follower taught by Tsai, because Tsai teaches that a source follower is typically used as a voltage buffer and provides reduced resistance relative to the driving voltage source, thereby providing a buffered output. (column 1, lines 20-26; column 13, lines 66-67; column 14, lines 1-3).
Regarding claim 2: Nomura in combination of Tsai does not disclose the amplifier circuit of wherein the inverting input is connected to a first input node via a first resistor and the non-inverting input is connected to a second input node via a second resistor, and wherein the second input node and the first input node are connected by a current sense resistor.
Puscasu, Fig. 2, further teaches the amplifier circuit of wherein the inverting input (IN-) is connected to a first input node (210) via a first resistor (214) and the non-inverting input (IN+) is connected to a second input node (208) via a second resistor (212), and wherein the second input node (208) and the first input node (210) are connected by a current sense resistor (206).
It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to modify the amplifier circuit of Nomura in view of Tsai to include the input-node, resistor, and current-sense-resistor configuration taught by Puscasu in order to provide differential sensing of a voltage across the current sense resistor.
Regarding claim 3: Nomura in combination of Tsai does not disclose the amplifier circuit of wherein the feed-back path includes a third resistor.
Puscasu, Fig. 2, further teaches wherein the feed-back path includes a third resistor (218) (Puscasu, page 4, paragraph [0030], lines 2–4).
It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to modify the amplifier circuit of Nomura in view of Tsai to include the third resistor in the feedback path as taught by Puscasu in order to provide feedback from the amplifier output to the inverting input of the input stage.
Regarding claim 4: Nomura in combination of Tsai does not disclose wherein the non-inverting input is connected to a reference voltage source via a fourth resistor.
Puscasu, Fig. 2, further teaches wherein the non-inverting input (IN+) is connected to a reference voltage source signal (REF) via a fourth resistor (216) (paragraph [0030], lines 10-11).
It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to modify the amplifier circuit of Nomura in view of Tsai to connect the non-inverting input to a reference voltage source via a fourth resistor as taught by Puscasu in order to provide the reference voltage to the non-inverting input of the input stage.
Regarding Claim 5: Nomura, Fig. 5, further teaches wherein the current path of the feed-forward circuit (150A, 150B, 150D) includes controllable current sources (CS11, CS12, CS21, CS22) coupled to the output of the output stage (OUT). Further, Nomura teaches activation and deactivation of the assist circuitry based on comparison of a control voltage to a threshold condition, wherein activation occurs when a control voltage crosses a predetermined threshold condition (paragraphs [0088], line 1, [0090], lines 1-4, [0092] lines 7-11, [0095] lines 3-7).
Regarding Claim 7: Nomura, Fig. 19, further teaches an n-channel field effect transistor (ML) associated the output node OUT (paragraph [0033] line 1-2, [0056], line 6-7), and teaches assist circuit (150A) becoming active in a sink mode and sinking auxiliary current (IAUX) from output terminal (OUT) (paragraph [0088], lines 1-3, [0092], lines 6-11), wherein activation occurs when a control voltage falls below a predetermined voltage condition [0095]. Also, as taught by Nomura, the differential input stage 110 generates intermediate signal Vb from differential input signals Vp and Vn, and Vb is applied as gate voltage VgL. Accordingly, the disclosed condition in which VgL falls below predetermined voltage Vm (paragraph [0095]) corresponds to the claimed differential input voltage falling below a threshold value.
Regarding Claim 8 Nomura, Fig. 19, further teaches wherein a p-channel field effect transistor (MH) associated with output node OUT (paragraph [0038] line 1-2, [0056], line 4). Furthermore, Nomura teaches assist circuit 150C becoming active in a source mode and sourcing auxiliary current IAUX from output terminal OUT (112, [0116], wherein activation occurs when a control voltage exceeds a predetermined voltage condition (paragraphs [0114]-[0116]). Also, as taught by Nomura, the differential input stage 110 generates intermediate signal Vb from differential input signals Vp and Vn (paragraph [0055]), and the control voltage used to activate the assist circuitry is derived from that differential input signal path. Accordingly, the disclosed condition in which the control voltage exceeds a predetermined voltage condition (paragraphs [0114-0116]) corresponds to the claimed differential input voltage exceeding a threshold value.
Regarding Claim 9: Nomura, Fig. 19, teaches A method comprising: providing, by an input stage (110F) of an amplifier (AMP),an output signal (Vb1, Vb2) that represents a differential input voltage (INP-INN) of the input stage (110F); providing, by an output stage (130F) of the amplifier (100F), an output voltage (OUT) based on the output signal (Vb1, Vb2) of the input stage (110F) at an amplifier output (OUT), and activating a current path coupled to the amplifier output (OUT) to provide an additional output current (IAUX) when assist circuits (150B, 150D) provide auxiliary current to output node OUT when activated (paragraphs [0088], [0092], [0116], when the differential input voltage (Vp-Vn) crosses a threshold value (Vth).
However, Nomura does not teach a feedback path coupling the amplifier output (OUT) with an inverting input of the input stage.
Puscasu, Fig. 2, teaches a feedback path that couples the output (OUT) of output stage (234) with the inverting input (IN-) of the input stage (224).
It would have been obvious to one of ordinary skill in the art at the time the invention was
effectively filed to incorporate the feedback path of Puscasu into Nomura in order to improve control of the amplifier output.
However, Normura in combination with Puscasu does not teach wherein the output stage includes a source follower.
Tsai, fig. 2, discloses a buffer stage (200) that includes a source follower (250), wherein the source follower (250) includes a first N-type transistor (MN1) having a first terminal coupled to an output node (NOUT) and a control terminal coupled to a first node (N1) (column 5, lines 28-36).
It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to further modify the output stage of the amplifier of Nomura as modified by Puscasu, to include the source follower taught by Tsai, because Tsai teaches that a source follower is typically used as a voltage buffer and provides reduced resistance relative to the driving voltage source, thereby providing a buffered output. (column 1, lines 20-26; column 13, lines 66-67; column 14, lines 1-3).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Puscasu (2019/0068144 A1) in view of Nomura (2023/0208360 A1) in further view of Tsai (US 10613560 B2).
Regarding claim 10: Puscasu, Fig. 2, discloses a current sense amplifier (CSA 200) comprising: a first input node (210) and a second input node (208) configured to sense a voltage drop, a differential voltage across sense resistor (206)) across a current sense resistor (206); an input stage (224) including an inverting input (IN-), which is coupled to the first input node (210) via a first resistor (214), and a non-inverting input (IN+), which is coupled to the second input node (208) via a second resistor (212), wherein the input stage (224) is configured to provide an output signal to output stage (234) that represents a differential input voltage applied to input terminals (208, 210) received at the inverting input (IN-) and the non-inverting inputs (IN+); a feed-back path that couples the amplifier output (OUT) of the output stage (234) with the inverting input (IN-) of the input stage (224), a feed-back path including resistor (218) that couples the output (OUT) of the output stage (234) with the inverting input (IN-) of the input stage (224).
However, Puscasu does not teach an output stage that includes a source follower configured to receive, as input signal, the output signal of the input stage and further configured to provide, at an amplifier output, an output voltage based on the input signal; and a feed-forward circuit configured to activate a current path coupled to the amplifier output to provide an additional output current when the differential input voltage crosses a threshold value.
Nomura, Fig. 19, teaches an output stage (130F) configured to receive, as input signal, the output signal (Vb1, Vb2) of the input stage (110F), (paragraph [0139]) and further configured to provide, at an amplifier output (OUT), an output voltage (OUT) based on the input signal (paragraphs [0139]-[0140]; Norma further teaches a feed-forward circuit (150B, 150D) configured to activate a current path coupled to the amplifier output (OUT) to provide an additional output current (IAUX) (paragraphs [0088], [0092] is provided when a control voltage reaches a predetermined voltage condition corresponding to the claimed differential input voltage crossing a threshold value (paragraphs [0093]-[0095]).
It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to modify the current sense amplifier of Puscasu to incorporate the output stage and feed-forward circuitry taught by Nomura in order to improve output driving capability and control of the amplifier output.
However, Puscasu in combination with Nomura does not teach an output stage that includes a source follower.
Tsai, fig. 2, discloses a buffer stage (200) that includes a source follower (250), wherein the source follower (250) includes a first N-type transistor (MN1) having a first terminal coupled to an output node (NOUT) and a control terminal coupled to a first node (N1) (column 5, lines 28-36).
It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to further modify the output stage of the amplifier of Puscasu as modified by Nomura, to include the source follower taught by Tsai, because Tsai teaches that a source follower is typically used as a voltage buffer and provides reduced resistance relative to the driving voltage source, thereby providing a buffered output. (column 1, lines 20-26; column 13, lines 66-67; column 14, lines 1-3).
Allowable Subject Matter
Claims 11, 12, 13 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance:
Regarding claim 11, none of the references teach a replica current mirror configured to generate a replica current of an output current of the input stage, an offset current source configured to generate an offset current, and a current mirror configured to drive a controllable current source based on a difference between the replica current and the offset current.
Regarding claim 12, none of the references teaches activating the current path by generating a replica current of an output current of the input stage, generating an offset current, and driving a controllable current source based on a difference between the replica current and the offset current.
Regarding claim 13, none of the references teaches a feed-forward circuit including a replica current mirror configured to generate a replica current of an output current of the input stage, an offset current source configured to generate an offset current, and a current mirror configured to drive a controllable current source based on a difference between the replica current and the offset current.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The prior art of record, including:
Parkhurst (US 2013/0187620 A1) discloses an amplifier circuitry employing an auxiliary current path to provide additional output current and improve amplifier output performance
Shen et al. (2020/0176978 A1) discloses amplifier circuitry employing current-mirror arrangements to generate and control currents associated with amplifier signal path.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to /NATASHA Y MARANO/ whose telephone number is (571) 272-9512. The examiner can normally be reached Mon - Fri 7:30am - 3:30pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Han can be reached at 571-272-2078. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/NATASHA Y MARANO/ Examiner, Art Unit 2843
/Jessica Han/ Supervisory Patent Examiner, Art Unit 2843
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