DETAILED ACTION
This action is responsive to the Application filed on 03/07/2024. Claims 1-20 are pending in the case. Claims 1, 11, and 17 are independent claims.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims and 11 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 11 of U.S. Patent No. 11,928,590. Although the claims at issue are not identical, they are not patentably distinct from each other because while they use slightly different words in parts of the claim, the effective coverage would be the same, as shown by the chart below.
U.S. Pat. App. 18/598,738
U.S. Pat. No. 11,928,590
1. A system, comprising:
1. A system, comprising:
a processor configured to initiate transmission of a stream of data; and
a processor configured to initiate transmission of a stream of data; and
a state machine engine coupled to the processor, wherein the state machine engine comprises:
a state machine engine coupled to the processor, wherein the state machine engine comprises:
an input configured to receive the stream of data;
an input configured to receive the stream of data;
blocks coupled to the input, each block of the blocks comprising configurable elements configured to analyze at least a portion of the stream of data and to selectively provide a result therefrom;
blocks coupled to the input, each block of the blocks comprising... configurable elements... configured to analyze at least a portion of the stream of data and to selectively provide a result therefrom;
a programming interface coupled to the blocks and configured to receive programming instructions separate from the stream of data received at the input and initially configure the configurable elements based on the programming instructions; and
a programming interface coupled to the blocks and configured to receive programming instructions separate from the stream of data received at the input and initially configure the configurable elements based on the programming instructions; and
block activation logic corresponding to a first block of the blocks, wherein the block activation logic is configured to power-up the first block based at least in part on the programming instructions.
block activation logic corresponding to a block of the blocks, wherein the block activation logic is configured to dynamically power-up the block, wherein the block activation logic comprises a register initially configured based on the programming instructions from the programming interface....
11. A system, comprising:
11. A device, comprising:
an input configured to receive a first indication of whether a block of configurable elements configured to analyze at least a portion of a stream of data and to selectively provide a result is to be involved in an analysis of the stream of data;
an input that when in operation receives a first indication of whether a block of configurable elements configured to analyze at least a portion of a stream of data and to selectively provide a result is to be involved in an analysis of the stream of data;
a register configured to generate a second indication of whether the portion of the stream of data to be analyzed by the block of configurable elements is at a start of the stream of data; and
a register corresponding to the block of configurable elements, wherein the register when in operation generates a second indication of whether the portion of the stream of data to be analyzed by the block is at a start of the stream of data; and
an output configured to provide a first activation signal for the block of configurable elements based at least in part on the first indication and second indication.
an output that when in operation provides a first activation signal for the block of configurable elements based at least in part on the first indication and second indication.
Claim Rejections - 35 U.S.C. § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. §§ 102 and 103 (or as subject to pre-AIA 35 U.S.C. §§ 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. § 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 11 and 15-20 are rejected under 35 U.S.C. § 102(a)(1) as being anticipated by Noyes et al. (U.S. Pat. App. Pub. No. 2011/0145271, hereinafter Noyes-Brown).
As to independent claim 11, Noyes-Brown discloses:
A system, comprising:
an input configured to receive a first indication of whether a block of configurable elements configured to analyze at least a portion of a stream of data and to selectively provide a result is to be involved in an analysis of the stream of data (Paragraph 81, "a search mode, the pattern-recognition processor 14 may interpret the data signals 138 as the input data stream 12 (FIG. 2)". Paragraphs 74 and 75. Paragraph 75, "groups of feature cells 30 may form parallel finite state machines that specify a search criterion or search criteria. Thus, each row 94, and block 96, may be programmed and used to search a data stream according to one or more search criteria". Paragraph 27);
a register configured to generate a second indication of whether the portion of the stream of data to be analyzed by the block of configurable elements is at a start of the stream of data (Paragraph 90, "(Start_SME) At least one start of a starting search term is contained in the block "); and
an output configured to provide a first activation signal for the block of configurable elements based at least in part on the first indication and second indication (Figure 15. Paragraphs 93 et seq.).
As to dependent claim 15, Noyes-Brown discloses a second input configured to receive a third indication of whether any configurable elements of the block of configurable elements are active and a fourth input configured to receive at least a portion of a fourth indication corresponding to a result of an analysis of at least a second portion of the stream of data to be analyzed from a second block of configurable elements (Paragraph 88, "The Block Still Active Sense component 100 may receive and/or detect signals from a block that indicate if the block is still active (according to the resolution provided by such detection). For example, the Block Still Active Sense component may receive or detect an active feature cell 30, row 94, or other activity in the block 96 and output, for example, a Row_Active signal that indicates a row of a block is still active." Paragraph 104, "the activate_next_block signal may be generated, when block 118B progresses to state B during the pattern search. Thus, the activate_next_block signal is generated at an earlier state than the cross-over signal. The activate_next_block signal from block 118A may be received by a block activation logic 124 of block 118B. The block activation logic 122 may activate block 118B in response to the received activate_next_block signal. Block 118B may then be ready to respond when the pattern search crosses-over to block 118B (e.g., when block 118B receives the cross-over signal provided from block 118A)").
As to dependent claim 16, Noyes-Brown discloses the output is configured to provide the first activation signal for the block of configurable elements based at least in part on the third indication or the fourth indication (Figure 15, Row_Active contributes to Activity Re-trigger and ultimately Block_Active. Block_Activate path likewise contributes to block activation. Figure 16).
As to independent claim 17, Noyes-Brown discloses:
A method, comprising:
receiving a first indication relating to whether a block of configurable elements is to be involved in an analysis of at least a portion of data (Paragraph 91, "The Flow_Enable signal may also be determined by the compiler and may change during operation of the processor 14, depending on the finite state machines processing data");
receiving a second indication of whether the portion of data to be analyzed is to be initially analyzed in the block of configurable elements (Paragraph 90, "(Start_SME) At least one start of a starting search term is contained in the block "); and
providing a block activation signal configured to allow the block of configurable elements to be powered based at least in part on the first and second indications (Paragraph 93, "The Block_On/Off signal and the Start_SME signal may be provided to a second AND gate 102B that outputs a “Force_Block_Enable” Signal to OR gate 108, indicating that a block includes a starting search term and should be active").
As to dependent claim 18, Noyes-Brown discloses receiving a third indication of whether any of the block of configurable elements of the block are active (Paragraph 88, " the Block Still Active Sense component may receive or detect an active feature cell 30, row 94, or other activity in the block 96 and output, for example, a Row_Active signal that indicates a row of a block is still active").
As to dependent claim 19, Noyes-Brown discloses receiving a fourth indication of a result of an analysis of at least a portion of the data to be analyzed from a second block of configurable elements (Paragraph 105, "The activate_next_block signal may be generated at any state of block 118A, to ensure that the block 118B is activated in time for the cross-over of the pattern search. For example, the activate_next_block signal may be generated at state A or any earlier state of block 118A, depending on the architecture of the pattern-recognition processor 14").
As to dependent claim 20, Noyes-Brown discloses providing the block activation signal configured to allow the block of configurable elements to be powered based at least in part on the third and fourth indications (Figure 15, Row_Active contributes to Activity Re-trigger and ultimately Block_Active. Block_Activate path likewise contributes to block activation. Figure 16).
Claim Rejections - 35 U.S.C. § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. §§ 102 and 103 (or as subject to pre-AIA 35 U.S.C. §§ 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. § 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 12-14 are rejected under 35 U.S.C. § 103 as being unpatentable over Noyes-Brown in view of Noyes et al. (U.S. Pat. App. Pub. No. 2010/0169538, hereinafter Noyes).
As to dependent claim 12, the rejection of claim 11 is incorporated.
Noyes-Brown does not appear to expressly teach a programming interface coupled to the block of configurable elements and configured to receive programming instructions separate from the stream of data.
Noyes teaches a programming interface coupled to the block of configurable elements and configured to receive programming instructions separate from the stream of data (Paragraph 78, "reading and writing data to and from the registers 97, register access logic 98 may manage the access to the registers 97").
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the reducing power consumption in a pattern recognition processor of Noyes-Brown to include the configuring a device of Noyes to perform pattern recognition tasks quickly while receiving data (see Noyes at paragraph 4).
As to dependent claim 13, Noyes-Brown further teaches at least a portion of the programming interface is configured to transmit the first indication based on the programming instructions (Paragraph 91, "The software compiler may determine which finite state machines are needed (and, thus, what blocks are needed) and set the Flow_Enable signal to activate or deactivate a block for a data stream").
As to dependent claim 14, Noyes further teaches the programming interface is configured to initially configure the register based on the programming instructions (Paragraph 77, "application instructions that may be loaded into memory 95 and executed by the CPU 20." Paragraph 78, "register access logic 98 may manage the access to the registers 97.").
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the reducing power consumption in a pattern recognition processor of Noyes-Brown to include the configuring a device of Noyes to perform pattern recognition tasks quickly while receiving data (see Noyes at paragraph 4).
Claims 1-10 are rejected under 35 U.S.C. § 103 as being unpatentable over Noyes-Brown in view of Noyes and Pawlowski et al. (U.S. Pat. App. Pub. No. 2010/0174887, hereinafter Pawlowski).
As to independent claim 1, Noyes-Brown teaches:
A system, comprising (Figure 1, system 10 and pattern-recognition processor 14. Paragraph 18):…
a state machine engine coupled to the processor, wherein the state machine engine comprises (Paragraph 74, "the pattern recognition processor 14 may include any arrangement of feature cells 30 (also referred to as state machine elements (SME's))". Paragraphs 26 and 27. Figure 1, CPU 20 and pattern-recognition processor 14):…
blocks coupled to the input, each block of the blocks comprising configurable elements configured to analyze at least a portion of the stream of data and to selectively provide a result therefrom (Paragraphs 74 and 75. Paragraph 75, "groups of feature cells 30 may form parallel finite state machines that specify a search criterion or search criteria. Thus, each row 94, and block 96, may be programmed and used to search a data stream according to one or more search criteria". Paragraph 27);…
block activation logic corresponding to a first block of the blocks, wherein the block activation logic is configured to power-up the first block based at least in part on the programming instructions (Paragraph 78, "each block 96 may be coupled to a power control circuit 98." Figure 15. Paragraph 90).
Noyes-Brown does not appear to expressly teach a programming interface coupled to the blocks and configured to receive programming instructions separate from the stream of data received at the input and initially configure the configurable elements based on the programming instructions.
Noyes teaches a programming interface coupled to the blocks and configured to receive programming instructions separate from the stream of data received at the input and initially configure the configurable elements based on the programming instructions (Paragraph 78, "the pattern-recognition processor 14, or the device 94 having the pattern-recognition processor 14, may include a plurality of registers 97 to store information related to the pattern-recognition system described above. To facilitate reading and writing data to and from the registers 97, register access logic 98 may manage the access to the registers 97". Paragraph 79. Paragraph 77, "application instructions that may be loaded into memory 95 and executed by the CPU 20". Paragraphs 91-94).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the reducing power consumption in a pattern recognition processor of Noyes-Brown to include the configuring a device of Noyes to perform pattern recognition tasks quickly while receiving data (see Noyes at paragraph 4).
Noyes-Brown does not appear to expressly teach a processor configured to initiate transmission of a stream of data; and an input configured to receive the stream of data.
Pawlowski teaches a processor configured to initiate transmission of a stream of data (Paragraph 82, "After the search results are received by the CPU 20, the CPU 20 may direct the pattern-recognition processor 14 to re-enter the search mode, and the CPU 20 may transmit the data stream 12 (FIG. 1) to the pattern-recognition processor 14 through the data lines 138". Figures 13 and 14); and an input configured to receive the stream of data (Paragraph 81, "a search mode, the pattern-recognition processor 14 may interpret the data signals 138 as the input data stream 12 (FIG. 2)".).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the reducing power consumption in a pattern recognition processor of Noyes-Brown to include the buses for pattern-recognition processors of Pawlowski to more quickly search for a large number of patterns with hardware (see Pawlowski at paragraph 5).
As to dependent claim 2, Noyes-Brown further teaches the block activation logic is configured to power up the first block when the programming instructions include an indication that data at a start of the stream of data is to be analyzed in the first block (Paragraph 90, "The states of the Block_On/Off signal, the Start_SME signal, and the Indefinite_SME signal may be determined via a software compiler operating the pattern-recognition processor 14 and generated via other logic components of the pattern-recognition processor 14. For example, the Block_On/Off, the Start_SME signal, and the Indefinite_SME signal may be generated from a programming and control logic 112. The software complier may specify the power configuration, based on the placement and routing of the different finite state machines programmed into the pattern-recognition processor").
As to dependent claim 3, Noyes further teaches the programming interface comprises a register initially configured based on the programming instructions (Paragraph 78, "registers 97, register access logic 98". Paragraphs 78 et seq.).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the reducing power consumption in a pattern recognition processor of Noyes-Brown to include the configuring a device of Noyes to perform pattern recognition tasks quickly while receiving data (see Noyes at paragraph 4).
As to dependent claim 4, Noyes-Brown further teaches the register is configured to provide a signal to the block activation logic that the first block is to be involved in a particular search of the stream of data (Paragraph 91, "the Flow_Enable signal to activate or deactivate a block for a data stream").
As to dependent claim 5, Noyes-Brown further teaches the block activation logic is configured to power-up the first block based at least in part on the signal provided from the register (Paragraph 93, "The Block_Activate signal and the Flow Enable signal may be provided to a third AND gate 102B that outputs a Conditional_Block Enable_Start signal to the re-triggerable deactivation timer 106").
As to dependent claim 6, Noyes-Brown further teaches the block activation logic is configured to dynamically power-up the first block based at least in part on signal received from a second block of the blocks (Paragraph 104, "During processing in block 118A, an “activate next block” signal may be generated, by a second signal generation logic 122, and provided from block 118A to block 118A, based on another state of block 118A. For example, as shown in FIG. 16, the activate_next_block signal may be generated, when block 118B progresses to state B during the pattern search". Paragraphs 101 et seq.).
As to dependent claim 7, Noyes further teaches the processor is configured to transmit the programming instructions to the state machine engine (Paragraphs 76-82. Figure 13).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the reducing power consumption in a pattern recognition processor of Noyes-Brown to include the configuring a device of Noyes to perform pattern recognition tasks quickly while receiving data (see Noyes at paragraph 4).
As to dependent claim 8, Pawlowski further teaches the state machine engine is configured to transmit the result to the processor (Paragraph 82, "The CPU 20 (FIG. 13) may respond to the output interrupt signal 114 being selected by directing the pattern-recognition processor 14 to enter the search-report mode").
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the reducing power consumption in a pattern recognition processor of Noyes-Brown to include the buses for pattern-recognition processors of Pawlowski to more quickly search for a large number of patterns with hardware (see Pawlowski at paragraph 5).
As to dependent claim 9, Pawlowski further teaches a memory coupled to the processor and the state machine engine, wherein the memory is configured to transmit the stream of data to be analyzed to the state machine engine (Figure 13. Paragraphs 72-76. Figure 1).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the reducing power consumption in a pattern recognition processor of Noyes-Brown to include the buses for pattern-recognition processors of Pawlowski to more quickly search for a large number of patterns with hardware (see Pawlowski at paragraph 5).
As to dependent claim 10, Noyes-Brown further teaches the block activation logic is configured to receive an indication of whether any of the configurable elements of the first block are active and dynamically power-up the first block based at least in part on the indication (Paragraph 100, "The output of the power control circuit is a Block_Active signal that activates or deactivates a block based on the Refresh_Access signal, the Force_Block_Enable_BX signal, or the Timer_Block_Enable signal. Thus, based on the various control signals, the Block_Active signal may activate or deactivate a block based on if the block is to be refreshed, is enabled for a data stream, is active or inactive for a data stream, is part of a “once activated, always active” search criteria, etc.").
Conclusion
It is noted that any citation to specific pages, columns, lines, or figures in the prior art references and any interpretation of the references should not be considered to be limiting in any way. A reference is relevant for all it contains and may be relied upon for all that it would have reasonably suggested to one having ordinary skill in the art. In re Heck, 699 F.2d 1331, 1332-33, 216 U.S.P.Q. 1038, 1039 (Fed. Cir. 1983) (quoting In re Lemelson, 397 F.2d 1006, 1009, 158 U.S.P.Q. 275, 277 (C.C.P.A. 1968)).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Casey R. Garner whose telephone number is 571-272-2467. The examiner can normally be reached Monday to Friday, 8am to 5pm, Eastern Time.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexey Shmatov can be reached on 571-270-3428. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Casey R. Garner/Primary Examiner, Art Unit 2123
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