Prosecution Insights
Last updated: October 23, 2026
Application No. 18/598,952

CHIP RESISTOR

Non-Final OA §103
Filed
Mar 07, 2024
Priority
Oct 29, 2021 — JP 2021-177313 +2 more
Examiner
LEE, KYUNG S
Art Unit
2831
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Rohm Co., Ltd.
OA Round
1 (Non-Final)
87%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
96%
With Interview

Examiner Intelligence

Grants 87% — above average
87%
Career Allowance Rate
1015 granted / 1164 resolved
+19.2% vs TC avg
Moderate +8% lift
Without
With
+8.3%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 0m
Avg Prosecution
17 currently pending
Career history
1186
Total Applications
across all art units

Statute-Specific Performance

§101
0.8%
-39.2% vs TC avg
§103
41.6%
+1.6% vs TC avg
§102
39.5%
-0.5% vs TC avg
§112
9.8%
-30.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1164 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-5 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Dunn et al., US Pub. 2004/0239474 in view of Yun et al., Pub. 2018/0130578. Regarding claim 1, Dunn teaches a chip resistor (starting paragraph 0020 and figs. 4-5) comprising: an insulating substrate (circuit substrate 400) provided with a first main surface (top), a first side surface (side by reference number 400 in fig. 4), and a second side surface (side by reference number 414 in fig. 4) opposite to the first side surface; a first electrode (electrode 435 closer to reference number 400); a second electrode (another electrode 435 closer to reference number 414) separated from the first electrode, the second electrode being provided closer to the second side surface than the first electrode in a plan view of the first main surface; a first resistive element (first resistor 420) provided on the first main surface; a second resistive element (second resistor 410) provided on the first main surface, the second resistive element being separated from the first resistive element; and an intermediate electrode (center electrode 430) provided on the first main surface and arranged between the first resistive element (420) and the second resistive element (410), wherein the first side surface and the second side surface are each connected to the first main surface (see fig. 5), in the plan view of the first main surface, the first electrode (430 by “400”; see fig. 4)) is provided closer to the first side surface than the second electrode, the first electrode includes a first front electrode (435) provided on the first main surface, the second electrode includes a second front electrode (435) provided on the first main surface, the second front electrode being separated from the first front electrode, the first resistive element (420) is in contact with the first front electrode (435) and the intermediate electrode (430), the second resistive element (410) is in contact with the second front electrode (435) and the intermediate electrode (430), and a first length of the first resistive element (420) in a first direction in which the first resistive element (420) and the second resistive element (410) are separated from each other is longer than a second length of the second resistive element in the first direction (the first resistor 420 is 4 square and the second resistor 410 is 2 square and that the first resistor is about twice the length of the second resistor; see paragraphs 0017 and 0020). Dunn teaches the claimed invention except for the first resistive element is provided with a first trimming groove, and the second resistive element is provided with a second trimming groove. Yun teaches a chip resistor (see fig. 4) having laser trim (grooves) formed on the first resistor (331) and the second resistor (332), the groves being formed for the purpose of controlling the resistor characteristics (see paragraphs 0031-0032). It would have been obvious to one skilled in the before the effective filing date of the claimed invention to combine the teachings of Yun with Dunn, since forming grooves to the resistor body allows for controlling the resistor characteristics to reach a target resistance for the resistor device of Dunn. Regarding claims 2 and 3, Dunn teaches the first resistor having the length twice the length of the second resistor (see at least paragraphs 0017 and 0020). Regarding claims 4 and 5, Dunn teaches the claimed invention except for “trim grooves.” Yun teaches the chip resistor, wherein the first trimming groove (groove for resistor “331”; see fig. 4 and at least paragraph 0045) includes a first trimming groove portion and a second trimming groove portion connected to the first trimming groove portion (L-shaped), in the plan view of the first main surface, a longitudinal direction of the first trimming groove portion extends along a second direction perpendicular to the first direction (crosses the length of the resistor device; see fig. 4), in the plan view of the first main surface, a longitudinal direction of the second trimming groove portion extends along the first direction (extends along the length of the resistor device), in the plan view of the first main surface, the longitudinal direction of the second trimming groove extends along the second direction (crosses the length of the resistor device; see fig. 4), and a first ratio of a trimming groove absent portion in the first resistive element in a second direction perpendicular to the first direction in the plan view of the first main surface is substantially equal to a second ratio of a trimming groove absent portion in the second resistive element in the second direction (groove are formed equally distanced; see fig. 4). It would have been obvious to one skilled in the before the effective filing date of the claimed invention to combine the teachings of Yun with Dunn, since forming grooves to the resistor body allows for controlling the resistor characteristics to reach a target resistance for the resistor device of Dunn. Regarding claim 7, Dunn teaches the claimed invention except for the first trimming groove is provided close to the first front electrode and the first side surface with respect to a first centerline of the first resistive element in the first direction, and the second trimming groove is provided close to the second front electrode and the second side surface with respect to a second centerline of the second resistive element in the first direction. Yun teaches the first trimming groove placed closer to the first front electrode (321) and the second trimming groove placed closer to the second front electrode (332). Yun teaches a chip resistor (see fig. 4) having laser trim (grooves) formed on the first resistor (331) and the second resistor (332), the groves being formed for the purpose of controlling the resistor characteristics (see paragraphs 0031-0032). It would have been obvious to one skilled in the before the effective filing date of the claimed invention to combine the teachings of Yun with Dunn, since forming grooves to the resistor body allows for controlling the resistor characteristics to reach a target resistance for the resistor device of Dunn. Allowable Subject Matter Claims 6 and 8-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Regarding claim 6, the prior art does not teach or suggest the chip resistor having the first trimming groove portion is provided on a first centerline of the first resistive element in the first direction or close to the first front electrode with respect to the first centerline, and the second trimming groove portion extends from the first trimming groove portion toward the first front electrode. Claim 8 depends on claim 6. Regarding claim 9, the prior art does not teach or suggest the chip resistor having the insulating protective layer electrically isolates the first electrode and the second electrode from each other and electrically isolates the first electroconductive resin layer and the second electroconductive resin layer from each other, and in the plan view of the first main surface, the first electroconductive resin layer covers at least a part of the first trimming groove and the second electroconductive resin layer covers at least a part of the second trimming groove. Claims 10-19 depend on claim 9. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to KYUNG S LEE whose telephone number is (571)272-1994. The examiner can normally be reached 7AM-3PM M-F. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Renee Luebke can be reached at 571-272-2009. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /KYUNG S LEE/Primary Examiner, Art Unit 2831
Read full office action

Prosecution Timeline

Mar 07, 2024
Application Filed
Sep 30, 2026
Non-Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
87%
Grant Probability
96%
With Interview (+8.3%)
2y 0m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1164 resolved cases by this examiner. Grant probability derived from career allowance rate.

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