DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3-8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tsukada (US Pub. 2009/0115568).
Regarding claim 1, Tsukada teaches a chip resistor module (plurality of resistors on a substrate; see at least figs. 11-13 and paragraphs 0056+) comprising:
a wiring board (2);
a plurality of chip resistors (5); and
a pair of terminal electrodes (terminal electrode 3 comprising of top electrode 14 and the side electrode 9), wherein
the wiring board includes an insulating substrate (insulating substrate 2) and an electrical wire (wiring connections 8 and 10) provided on the insulating substrate,
the plurality of chip resistors (5) are bonded to the electrical wire (8 and 10), and the pair of terminal electrodes is electrically connected to the electrical wire (8 and 10).
Regarding claims 3 and 4, Tsukada teaches the chip resistor module according to claim 1, further comprising an insulating sealing member (resin coating 6; paragraph 0038) with which the plurality of chip resistors are sealed,
the chip resistor module, further comprising a thermally conductive sheet (glass coating 7; paragraph 0038) higher in thermal conductivity than the insulating sealing member (glass coating having a thermal conductivity of 0.5 to 1.4 W/m·k and resin coating having a thermal conductivity of 0.15 to 0.3 W/m·k), wherein the thermally conductive sheet covers the plurality of chip resistors and is electrically insulating (see fig. 12), and
the thermally conductive sheet is in contact with the pair of terminal electrodes (sheet 7 is in an indirect contact with the terminal electrode 3).
Regarding claim 6, Tsukada teaches the chip resistor module according to claim 1, wherein the insulating substrate is provided with a front surface (top), a back surface (bottom), and a side surface connected to the front surface and the back surface, the electrical wire (wires 8 and 10) is formed on the front surface, and the pair of terminal electrodes (comprising of connections 14 and 9; see fig. 12) is provided on the electrical wire, the side surface, and the back surface.
Regarding claim 7, Tsukada teaches the chip resistor module according to claim 1, wherein the insulating substrate is provided with a front surface (top), the electrical wire is formed on the front surface (wires 8 and 10), and in a plan view of the front surface, the plurality of chip resistors are two-dimensionally aligned (sides 2a and 2b are aligned).
Regarding claim 8, Tsukada teaches the chip resistor module according to claim 1, the chip resistor module being a discharging resistor (power applied to the plurality of resistors is divided to allow for temperature suppression or heat discharging; paragraphs 0007-0008).
Allowable Subject Matter
Claim 2 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 2, the prior art does not teach or suggest the chip resistor module, wherein in a direction in which the pair of terminal electrodes is separated from each other, an interval between each pair of adjacent chip resistors among the plurality of chip resistors is greater toward a center of the insulating substrate.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KYUNG S LEE whose telephone number is (571)272-1994. The examiner can normally be reached 7AM-3PM M-F.
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/KYUNG S LEE/Primary Examiner, Art Unit 2831
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