Prosecution Insights
Last updated: April 19, 2026
Application No. 18/599,084

DEEP LEARNING-BASED DIGITAL HOLOGRAPHIC CONTINUOUS PHASE NOISE REDUCTION METHOD FOR MICROSTRUCTURE MEASUREMENT

Non-Final OA §112
Filed
Mar 07, 2024
Examiner
DUNNING, RYAN S
Art Unit
2872
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Zhejiang Sci-Tech University
OA Round
1 (Non-Final)
77%
Grant Probability
Favorable
1-2
OA Rounds
3y 0m
To Grant
99%
With Interview

Examiner Intelligence

Grants 77% — above average
77%
Career Allow Rate
322 granted / 420 resolved
+8.7% vs TC avg
Strong +22% interview lift
Without
With
+21.9%
Interview Lift
resolved cases with interview
Typical timeline
3y 0m
Avg Prosecution
34 currently pending
Career history
454
Total Applications
across all art units

Statute-Specific Performance

§103
41.9%
+1.9% vs TC avg
§102
31.1%
-8.9% vs TC avg
§112
20.6%
-19.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 420 resolved cases

Office Action

§112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 1-9 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. Claim 1 recites the phrase: “simulating a MEMS microstructure to generate an object phase image through generation of random matrix superposition, simultaneously simulating noise in a digital holographic continuous phase map to generate a noise grayscale image”. It is believed that the word “simultaneous” refers to the simultaneous nature of the two simulating actions (i.e., “simulating a MEMS microstructure” and “simulating noise”) and thus should be stated as a single step relative to the other sub-steps (“adding”, “treating”, “designing”, “inputting”) of the claimed “step one”. See, e.g., paragraphs [0006] and [0046] of the originally-filed specification. Thus, for examination, the above phrase will be treated as: “simulating a MEMS microstructure to generate an object phase image through generation of random matrix superposition and simultaneously simulating noise in a digital holographic continuous phase map to generate a noise grayscale image”. Claims 2-9 inherit the deficiencies of Claim 1. Appropriate correction is required. Allowable Subject Matter Claims 1-9, as best understood, would be allowable if rewritten to overcome the rejections based on 35 USC 112(b) explained above. The following is a statement of reasons for the indication of allowable subject matter. With respect to Claim 1, although the prior art discloses various phase noise reduction methods, including simulation of noise, the prior art does not appear to disclose or suggest the several claimed method steps and their particular features and requirements. With respect to Claims 2-9, these claims each depend from Claim 1, and are therefore allowable for at least the reasons stated above. Related Art The following references are cited to show examples of holographic methods including noise simulation, but which do not appear to otherwise disclose or suggest the present invention: (1) U.S. Pat. No. 6,809,845 of Kim et al.; (2) U.S. Pat. No. 9,360,299 of Kim; and (3) U.S. Pat. Appl. Pub. No. 2010/0046848 A1 of Witzgall et al. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to RYAN S DUNNING whose telephone number is 571-272-4879. The examiner can normally be reached Monday thru Friday 10:30AM to 7:00PM Eastern Time Zone. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, BUMSUK WON can be reached at 571-272-2713. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /RYAN S DUNNING/Primary Examiner, Art Unit 2872
Read full office action

Prosecution Timeline

Mar 07, 2024
Application Filed
Feb 21, 2026
Non-Final Rejection — §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
77%
Grant Probability
99%
With Interview (+21.9%)
3y 0m
Median Time to Grant
Low
PTA Risk
Based on 420 resolved cases by this examiner. Grant probability derived from career allow rate.

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