DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, Species K in the reply filed on 09/03/2026 is acknowledged. Claims 4, 6, 7, 13-17 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected group and species, there being no allowable generic or linking claim.
Claim 10 is directed to a non-elected species (Fig. 9) because it requires a connection terminal. Accordingly, claim 10 is withdrawn from consideration as being directed to a non-elected invention. See 37 CFR 1.142(b) and MPEP § 821.03.
To preserve a right to petition, the reply to this action must distinctly and specifically point out supposed errors in the restriction requirement. Otherwise, the election shall be treated as a final election without traverse. Traversal must be timely. Failure to timely traverse the requirement will result in the loss of right to petition under 37 CFR 1.144. If claims are subsequently added, applicant must indicate which of the subsequently added claims are readable upon the elected invention.
Should applicant traverse on the ground that the inventions are not patentably distinct, applicant should submit evidence or identify such evidence now of record showing the inventions to be obvious variants or clearly admit on the record that this is the case. In either instance, if the examiner finds one of the inventions unpatentable over the prior art, the evidence or admission may be used in a rejection under 35 U.S.C. 103 or pre-AIA 35 U.S.C. 103(a) of the other invention.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2, 3, 5 and 8 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 2 recites the limitation "an impedance value of the patterned circuit layer matches an impedance value of a die coupled to the patterned circuit layer through the first conduction structure" in lines 4-5, however, this limitation appears to be functional language as it does not provide the structure that is required to perform that function. The Examiner notes that the use of functional language in a claim may fail "to provide a clear-cut indication of the scope of the subject matter embraced by the claim" and thus be indefinite. In re Swinehart, 439 F.2d 210, 213 (CCPA 1971). For example, when claims merely recite a description of a problem to be solved or a function or result achieved by the invention, the boundaries of the claim scope may be unclear. Halliburton Energy Servs., Inc. v. M-I LLC, 514 F.3d 1244, 1255, 85 USPQ2d 1654, 1663 (Fed. Cir. 2008) (noting that the Supreme Court explained that a vice of functional claiming occurs "when the inventor is painstaking when he recites what has already been seen, and then uses conveniently functional language at the exact point of novelty") (quoting General Elec. Co. v. Wabash Appliance Corp., 304 U.S. 364, 371 (1938)); see also United Carbon Co. v. Bonney & Smith Co., 317 U.S. 228, 234 (1942)). It is unclear what structure is required to have matched impedance value. For purposes of compact prosecution, the Examiner will interpret the structure describe in claim 1 and 2 as the structure required to perform the function of having "an impedance value of the patterned circuit layer matches an impedance value of a die coupled to the patterned circuit layer through the first conduction structure”.
Claim 3 recites the limitation "a plurality of first conduction structure" and further, claim 1 recites “ a first conduction structure”. It is unclear if the “first conduction structure” includes “a plurality of first conduction structure”. There is insufficient antecedent basis for this limitation in the claim. The Examiner will interpret the structure to represent the plurality of first conduction structure to include the first conduction structure. For clarity, the language of claim one may be interpreted as “at least one first conduction structure”
Claim 5 recites the limitation “a thickness in a vertical direction greater than or equal to twice a diameter” however in this case, the vertical thickness can be the diameter of the first conduction structure. The language does not establish which orientation the diameter is being measured as such the language is not clear and concise. The plain meaning of “diameter” is a straight line passing through the center of a circle or sphere, connecting two points on its boundary. In an effort of compact prosecution, the Examiner will interpret the claim to be: first conduction structure has a minor axis (diameter) and a major axis (vertical thickness) in which the major axis is two times larger than the minor axis. A shape has to be established (sphere, cylinder, etc).
Claim 8 recites the limitation " a plurality of dies" and further, claim 1 recites “ die”. It is unclear if the “die” includes “a plurality of dies”. There is insufficient antecedent basis for this limitation in the claim. The Examiner will interpret the structure to represent the plurality of first conduction structure to include the first conduction structure. For clarity, the language of claim one may be interpreted as “at least one die” .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 8 and 9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al. [US 2019/0164933 A1], “Lee”.
Regarding claim 1, Lee discloses a chip package structure (Fig. 15, 100A – see Fig. 15* annotated for easier referencing), comprising:
a first connection layer (Fig. 15*, 1stCL) having an upper surface and a lower surface, wherein the upper surface and the lower surface are opposite to each other (as shown);
a die (120A) disposed on the upper surface (as shown) of the first connection layer (1stCL), wherein the die is coupled to the first connection layer (as shown, ¶[0073]);
a first conduction structure (150) disposed on an upper surface of the die (120A), wherein the first conduction structure is coupled to the die (as shown, ¶[0068]);
a first plastic package layer (130, ¶[0088]) covering the die (120A) and the first conduction structure (150), wherein at least a part of the first conduction structure is exposed from an upper surface of the first plastic package layer (as shown); and
a rewiring layer (140) disposed on the first plastic package layer (130), wherein the rewiring layer is coupled to the first conduction structure (as shown).
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Regarding claim 2, Lee discloses claim 1, Lee further discloses the rewiring layer (Fig. 15, 140) includes a patterned circuit layer (142) and a first protection layer (141), the first protection layer is configured to protect the patterned circuit layer (as shown), and an impedance value of the patterned circuit layer matches an impedance value of a die coupled to the patterned circuit layer through the first conduction structure (see 112 rejection).
Regarding claim 8, Lee discloses claim 1, Lee further discloses a plurality of dies, wherein at least two dies (120A and 120B), of the plurality of dies, have different thicknesses in a vertical direction (t1 vs t2).
Regarding claim 9, Lee discloses claim 1, Lee further discloses the die (Fig. 120A) is coupled to the upper surface of the first connection layer through a second connection layer, or the die is directly coupled to the upper surface of the first connection layer (as shown).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over by Lee et al. [US 2019/0164933 A1], “Lee” as applied to claim 1 further in view of Ismail [US 2007/0202680 A1].
Regarding claim 3, Lee discloses claim 1, Lee discloses a plurality of first conduction structures (see Fig. 15). Lee does not explicitly disclose at least one of the pluralities of first conduction structures includes a plurality of solder balls stacked in a vertical direction.
However, Ismail discloses a plurality of semiconductor dice (Fig. 9, 100) with a plurality of first conduction structures (110), wherein at least one of the pluralities of first conduction structures includes a plurality of solder balls stacked in a vertical direction (as shown) in order to form provide a simple and inexpensive method of packaging one or more semiconductor dice (¶[0003]). Each of the stacks (Fig. 3, 20) with the solder balls can be adjusted to prevent crack formation in the bottom-most bumps (i.e. the first set of bumps 14) and to avoid differences in the size of the exposed portions of the top-most bumps (18), shifting of the exposed portions of the top-most bumps (18) from the desired locations on the surface (28) of the package (26), the bumps peeling off one another, and co-planarity issues.
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use a conduction structures includes a plurality of solder balls stacked in a vertical direction as taught in Ismail in the device of Lee because such a modification will provide an alternative, simple and inexpensive method of packaging one or more semiconductor dice and making electrical connection to a packaging device that is (¶[0003]).
Regarding claim 5, Lee discloses claim 1, Lee discloses a plurality of first conduction structures (see Fig. 15). Lee does not explicitly disclose the first conduction structure has a thickness in a vertical direction greater than or equal to twice a diameter of the first conduction structure.
However, Ismail discloses a plurality of semiconductor dice (Fig. 9, 100) with a plurality of first conduction structures (110), wherein at least one of the pluralities of first conduction structures includes a plurality of solder balls stacked in a vertical direction (as shown) in order to form provide a simple and inexpensive method of packaging one or more semiconductor dice (¶[0003]). Each of the stacks (Fig. 3, 20) with the solder balls can be adjusted to prevent crack formation in the bottom-most bumps (i.e. the first set of bumps 14) and to avoid differences in the size of the exposed portions of the top-most bumps (18), shifting of the exposed portions of the top-most bumps (18) from the desired locations on the surface (28) of the package (26), the bumps peeling off one another, and co-planarity issues. Further as shown in Fig. 9, the first conduction structure (110) has a thickness in a vertical direction greater than or equal to twice a diameter of the first conduction structure.
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use a conduction structures with a plurality of solder balls stacked in a vertical direction as taught in Ismail in the device of Lee because such that the first conduction structure has a thickness in a vertical direction greater than or equal to twice a diameter of the first conduction structure a modification will provide an alternative, simple and inexpensive method of packaging one or more semiconductor dice and making electrical connection to a packaging device that is (¶[0003]).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over by Lee et al. [US 2019/0164933 A1], “Lee” as applied in claim 1 and further in view of Xi et al. [US 2020/0328159 A1 “Xi”.
Regarding claim 11, Lee discloses claim 1, Lee does not discloses a chip disposed on the rewiring layer; a second conduction structure disposed on the rewiring layer; a second plastic package layer covering the chip and the second conduction structure, wherein at least a part of the second conduction structure is exposed from an upper surface of the second plastic package layer; a third connection layer disposed on the second plastic package layer, wherein the third connection layer is coupled to the second conduction structure; and a second protection layer configured to protect the third connection layer.
However, Xi discloses a chip package structure, comprising: a first connection layer a die disposed on the upper surface of the first connection layer (Fig. 11, 10), wherein the die is coupled to the first connection layer (as shown); a first conduction structure (21) disposed on an upper surface of the die, wherein the first conduction structure is coupled to the die; a first plastic package layer (30) covering the die and the first conduction structure and a rewiring layer (40) disposed on the first plastic package layer, wherein the rewiring layer is coupled to the first conduction structure. Further Xi discloses a chip (Fig. 11, 60) disposed on the rewiring layer (40); a second conduction structure (70) disposed on the rewiring layer; a second plastic package layer (31) covering the chip (60) and the second conduction structure (70), wherein at least a part of the second conduction structure is exposed from an upper surface of the second plastic package layer (as shown); a third connection layer (81/80) disposed on the second plastic package layer (31), wherein the third connection layer is coupled to the second conduction structure (70); and a second protection layer (as shown) configured to protect the third connection layer.
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to add discloses a chip disposed on the rewiring layer; a second conduction structure disposed on the rewiring layer; a second plastic package layer covering the chip and the second conduction structure, wherein at least a part of the second conduction structure is exposed from an upper surface of the second plastic package layer; a third connection layer disposed on the second plastic package layer, wherein the third connection layer is coupled to the second conduction structure; and a second protection layer configured to protect the third connection layer as taught in Xi in the device of Lee because adding the die and redistribution layer will create panel-level chip device with the ability to for electrical connection to both internal device and external devices (¶[0048] and ¶[0071] of Xi).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over by Lee et al. [US 2019/0164933 A1], “Lee” in view of Xi et al. [US 2020/0328159 A1 “Xi” as applied in claim 11 and further Huang et al. [US 2021/0175191 A1], “Huang”.
Regarding claim 12, Lee as modified discloses claim 11, Lee as modified by Xi further disclose the second conduction structure (70) may be made of a material having desired electrical conductivity, e.g., copper, iron, or nickel, etc.(¶[0067] of Xi). Lee as modified does not explicitly disclose the second conduction structure (70) includes: a plurality of solder balls stacked in a vertical direction, at least one wire, or a planted pin.
However, Huang discloses a suitable alternative conduction structure. Huang discloses The through vias (Fig. 3E, 310) can also be metal wire studs placed by a wire bonding process, such as a copper wire bonding process. The use of a wire bonding process may eliminate the need for depositing a seed layer, depositing and patterning a photoresist, and plating to form the through vias (310) (¶[0027] of Huang).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use a suitable alternative wire conduction structure as taught by Huang in the device of Lee as modified such that the second conduction structure includes at least one wire because the use of a wire bonding process may eliminate the need for addition processing steps required when plating (¶[0027] of Huang). Further, the selection of a suitable alternative material and the selection of a known material based on its suitability for its intended use supports a determination of obviousness (See MPEP §2144.07).
Claims 18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over by Lee et al. [US 2019/0164933 A1], “Lee” further in view of Tsai et al. [US 2020/0105663 A1], “Tsai”.
Regarding claim 18, Lee discloses an electronic device (Fig. 15*), comprising:
a chip package structure (100A); and
chip package structure comprises:
a first connection layer (1stCL) having an upper surface and a lower surface, wherein the upper surface and the lower surface are opposite to each other (as shown);
a die (120A) disposed on the upper surface (as shown) of the first connection layer (1stCL), wherein the die is coupled to the first connection layer (as shown, ¶[0073]);
a first conduction structure (150) disposed on an upper surface of the die (150A), wherein the first conduction structure is coupled to the die (as shown, ¶[0068]);
a first plastic package layer (130, ¶[0088]) covering the die (120A) and the first conduction structure (150), wherein at least a part of the first conduction structure is exposed from an upper surface of the first plastic package layer (as shown); and
a rewiring layer (140) disposed on the first plastic package layer (130), wherein the rewiring layer is coupled to the first conduction structure (as shown).
Fig. 15 of Lee does not disclose a circuit board electrically interconnected with the chip package structure.
However, Lee discloses semiconductor package (Fig. 5, 2200) may be ultimately mounted on a mainboard (2500) of an electronic device. Further, Tsai disclose a chip package structure (Fig. 20, 302) and a circuit board (306 and ¶[0059]) electrically interconnected with the chip package structure, the circuit board is disposed on a lower surface of the first connection layer (210) in the chip package structure in order to provide a side-by-side multi-chip-module (SBS-MCM) that allows integrated circuit dies to communicate to form a complete system (¶[0056]).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use a circuit board as taught in Tsai in the device of Lee such that a circuit board electrically interconnected with the chip package structure because such a modification would provide a side-by-side multi-chip-module (SBS-MCM) that allows integrated circuit dies to communicate to form a complete system (¶[0056] of Tsai).
Regarding claim 20, Lee as modified discloses claim 18, Lee as modified discloses the chip package structure (110) includes a third conduction structure (170), and the circuit board is disposed on a lower surface of the first connection layer in the chip package structure ( as taught by Lee in view of Tsai – see claim 18).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PRIYA M RAMPERSAUD whose telephone number is (571)272-3464. The examiner can normally be reached Mon-Wed 9am-6pm.
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PRIYA M. RAMPERSAUD
Examiner
Art Unit 2897
/PRIYA M RAMPERSAUD/ Examiner, Art Unit 2897
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