DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Species #10, Figs. 11 and 12, claims 1-16 and 19-20 in the reply filed on 11/10/2025) is acknowledged. The traversal is on the ground(s) that claims 17-18 are not independent or distinct, since the withdrawn claims and the elected claims have relevance in design and effect, have the same search classes/subclasses, and involve the same technical field. This is found persuasive because examiner has reconsidered the closeness of the search classes/subclasses and technical field. Therefore, claims 17 and 18 are reinstated and all claims 1-20 are now active for examination on the merits as follows:
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3 and 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhai (US 2022/0246088) in view of Zhang et al. (US 20220335872).
As to claims 1, 19 and 20, Zhai discloses a display device (Fig. 13, and [0092] comprising a display panel (Fig. 1), comprising a pixel circuit (Fig. 2: driver circuit including a pulse-amplitude modulation (PAM) circuit 110 and a pulse-width modulation (PWM) circuit 120) and a light-emitting element (Fig. 2: light-emitting element 10, which may be a micro-LED, a mini-LED, a nano-LED[0035], a quantum dot light-emitting diode (QLED) or the like according to [0033]); wherein the pixel circuit comprises an amplitude modulation subcircuit (Fig. 2: pulse-amplitude modulation (PAM) circuit 110) and a pulse width modulation subcircuit (Fig. 2: pulse-width modulation (PWM) circuit 120); and the amplitude modulation subcircuit (Fig. 2, (110) and the pulse width modulation subcircuit (Fig. 2, (120) each comprises a drive transistor (Fig. 2, (Dr_PAM)(Dr_PWM)[0036]; and a working process of at least one of the amplitude modulation subcircuit or the pulse width modulation subcircuit comprises a bias stage(Fig. 2: signal at drain/source of drive transistor Dr_PAM or drive transistor Dr_PWM). However, Zhai does not specifically disclose a bias adjustment signal is provided to the drive transistor during the bias stage, and the bias adjustment signal is configured to adjust a bias state of the drive transistor.
Zhang discloses a bias adjustment signal is provided to the drive transistor during the bias stage, and the bias adjustment signal is configured to adjust a bias state of the drive transistor (Figs. 3, 6 and 7, and [0040, 0090, 0093]). It would have been obvious to one of ordinary skill in the art at the time of filing to have the bias adjustment signal, as taught by Zhang, in the device of Zhai, so that the bias state of the drive transistor in each brightness mode achieves a better adjustment effect, and further, the display uniformity of the display panel can be improved in each of the different brightness modes, and the display quality of the display panel is significantly improved [0040].
As to claim 2, further, Zhai discloses the working process of the amplitude modulation subcircuit (Fig. 2, (110) comprises a first data write stage (Fig. 2: data write unit 112) and a first bias stage (when the bias adjustment signal is used to adjust a bias state of the drive transistor (Fig. 2 (Dr_PAM); and wherein the amplitude modulation subcircuit (Fig. 2, (110) comprises a first data write module (Fig. 2: data write unit 112), and the first data write module is configured to write a first data signal during the first data write stage (Fig. 2, (DATA_PAM)[0036, 0038] (“The data signal terminal DATA_PAM receives the pulse-amplitude modulation data voltage Vdata_PAM”) and write a first bias adjustment signal during the first bias stage (Fig. 2: signal at drain/source of drive transistor Dr_PAM ). Further, transistors do always require bias adjustment signals to ensure their proper functioning and to avoid distortion or damage.
As to claim 3, further, Zhai discloses the working process of the pulse width modulation subcircuit (Fig. 2, (120) comprises a second data write stage (Fig. 2 data write unit 122) and a second bias stage; and wherein the pulse width modulation subcircuit (Fig. 2, (120) comprises a second data write module (Fig. 2, (120), and the second data write module is configured to write a second data signal during the second data write stage (Fig. 2: signal received by data signal terminal DATA_PAM; [0037, 0039] (“the data signal terminal DATA_PWM receives the pulse-width modulation data voltage Vdata_PWM”) and write a second bias adjustment signal during the second bias stage (Fig. 2: signal at drain/source of drive transistor Dr_PWM). Further, transistors do always require bias adjustment signals to ensure their proper functioning and to avoid distortion or damage.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhai (US 2022/0246088) in view of Zhang et al. (US 20220335872), as applied to claim 1 above, and further in view of Jiang et al. (2021/0407384).
As to claim 4, further, Zhai, as anticipated by Zhang, does not specifically disclose the bias adjustment signal comprises a first bias adjustment signal and a second bias adjustment signal, the first bias adjustment signal is configured to adjust a bias state of the first drive transistor, and the second bias adjustment signal is configured to adjust a bias state of the second drive transistor; and a voltage of the first bias adjustment signal is V1, a voltage of the second bias adjustment signal is V2, and V1# V2.
Jiang, further, discloses the bias adjustment signal comprises a first bias adjustment signal (Fig. 2, (Vx1) and a second bias adjustment signal (Fig. 2, (Vx2), the first bias adjustment signal is configured to adjust a bias state of the first drive transistor (Fig. 2, (MA2), and the second bias adjustment signal is configured to adjust a bias state of the second drive transistor (MB2)(see first paragraph in reference to Fig. 2); and a voltage of the first bias adjustment signal is V1 (Vx1), a voltage of the second bias adjustment signal is V2 (Vx2), and V1# V2 (Vx1 not equal to Vx2) (see first and second paragraphs in reference to Fig. 2). It would have been obvious to one of ordinary skill in the art at the time of filing to have two bias adjustment signals, as taught by Jiang, in the device of Zhai and Zhang, so that the size of the first current Ia and the second current Ib can be adjusted (second paragraph in reference to Fig. 2).
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhai (US 2022/0246088) in view of Zhang et al. (US 20220335872), as applied to claim 1 above, and further in view of Yuan et al. (2021/0407384).
As to claim 12, Zhai, as anticipated by Zhang, further, does not specifically disclose a number of bias stages of the amplitude modulation subcircuit within a target time period is al, a number of bias stages of the pulse width modulation subcircuit within the target time period is bl, and al <bl.
Yuan discloses a number of bias stages of the amplitude modulation subcircuit within a target time period is al, a number of bias stages of the pulse width modulation subcircuit within the target time period is bl, and al <bl. (Fig. 6 and [0077]). It would have been obvious to one of ordinary skill in the art at the time of filing to have two bias stages with different durations, as taught by Yuan, in the device of Zhai and Zhang, so as to fully achieve the bias effect [0077].
Allowable Subject Matter
Claims 5-11, and 13-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: Claims 4-18 are considered allowable since certain key features of the claimed invention are not taught or fairly suggested by the prior art. In claim 5, “the bias adjustment signal comprises a first bias adjustment signal and a second bias adjustment signal, the first bias adjustment signal is configured to adjust a bias state of the first drive transistor, and the second bias adjustment signal is configured to adjust a bias state of the second drive transistor; wherein a working cycle of the pixel circuit comprises at least one data write frame and at least one retention frame, and the at least one data write frame and the at least one retention frame each comprises at least one bias stage; and wherein a voltage of the first bias adjustment signal during the at least one data write frame isV11, a voltage of the first bias adjustment signal during the at least one retention frame is V12, and V11#V12; and/or a voltage of the second bias adjustment signal during the at least one data write frame is V21, a voltage of the second bias adjustment signal during the at least one retention frame is V22, and V21 # V22”. In claim 10, “the bias adjustment signal comprises a first bias adjustment signal and a second bias adjustment signal, the first bias adjustment signal is configured to adjust a bias state of the first drive transistor, and the second bias adjustment signal is configured to adjust a bias state of the second drive transistor; wherein a working cycle of the pixel circuit comprises at least one bias stage; and wherein a voltage of the first bias adjustment signal in an m-th working cycle is Vlm, a voltage of the first bias adjustment signal in an n-th working cycle is Vln, and Vlm = V and/or a voltage of the second bias adjustment signal in an m-th working cycle is V2m, a voltage of the second bias adjustment signal in an n-th working cycle is V2n, and V2m = V2n.”. In claim 11, “the bias adjustment signal comprises a first bias adjustment signal and a second bias adjustment signal, the first bias adjustment signal is configured to adjust a bias state of the first drive transistor, and the second bias adjustment signal is configured to adjust a bias state of the second drive transistor; wherein a working cycle of the pixel circuit comprises at least one bias stage; and wherein a voltage of the first bias adjustment signal in an x-th working cycle is Vix, a voltage of the first bias adjustment signal in a y-th working cycle is Vly, and Vlx#Vly;and/or a voltage of the second bias adjustment signal in an x-th working cycle is V2x, a voltage of the second bias adjustment signal in a y-th working cycle is V2y, and V2x # V2y”. In claim 13, “the bias adjustment signal comprises a first bias adjustment signal and a second bias adjustment signal, the first bias adjustment signal is configured to adjust a bias state of the first drive transistor, and the second bias adjustment signal is configured to adjust a bias state of the second drive transistor; wherein the display panel comprises a first brightness mode and a second brightness mode; and wherein a voltage of the first bias adjustment signal in the first brightness mode is V ilua voltage of the first bias adjustment signal in the second brightness mode is VlL, and Vilu#VlLa; and/or a voltage of the second bias adjustment signal in the first brightness mode is V2L1a voltage of the second bias adjustment signal in the second brightness mode is V2L2,and V2L1# V2L2”. In claim 15, “the bias adjustment signal comprises a first bias adjustment signal and a second bias adjustment signal, the first bias adjustment signal is configured to adjust a bias state of the first drive transistor, and the second bias adjustment signal is configured to adjust a bias state of the second drive transistor; wherein the display panel comprises a first refresh frequency and a second refresh frequency; and wherein a voltage of the first bias adjustment signal at the first refresh frequency is V1Fi, a voltage of the first bias adjustment signal at the second refresh frequency is V1F2, and V1F1#V1F2; and/or a voltage of the second bias adjustment signal at the first refresh frequency is V2F1, a voltage of the second bias adjustment signal at the second refresh frequency is V2F2, and V2F1 # V2F2”. In claim 17, “ the bias adjustment signal comprises a first bias adjustment signal and a second bias adjustment signal, the first bias adjustment signal is configured to adjust a bias state of the first drive transistor, and the second bias adjustment signal is configured to adjust a bias state of the second drive transistor…a voltage value of the first bias adjustment signal received by the first pixel circuit is V13, a voltage value of the second bias adjustment signal received by the first pixel circuit is V23, a voltage value of the first bias adjustment signal received by the second pixel circuit is V14, and a voltage value of the second bias adjustment signal received by the second pixel circuit is V24; and wherein V13 #V14 and/or V23 # V24”. The closest prior art of record, Zhai (US 2022/0246088), refer to above rejection for reference, singularly or in combination, fails to anticipate or render the above underlined limitations obvious, together with all the other limitations of the claims.
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/RICARDO OSORIO/Primary Examiner, Art Unit 2621