DETAILED ACTION
Response to Arguments
Applicant’s arguments with respect to claim(s) rejected in the prior office action have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant has amended the claims to clarify the routing of elements and respective outputs. The prior art lacks the first amplifier together with a first modulator in the first chip. It is noted, however, that it is common in the art to pair amplifiers with modulators in source elements. Therefore, a new rejection is cited below in view of US 2011/0150471 to Joyner et al.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 and 4-5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sugiyama (cited in prior office action) in view of US 2011/0150471 to Joyner et al.
Sugiyama discloses in the abstract and figure 10, An optical device, comprising:
a first chip (95) comprising a first polarized signal optical port, a second polarized signal optical port, and one or more optical elements coupled to the first polarized signal optical port and the second polarized signal optical port; and
a second chip (90A) comprising a first polarized signal optical port coupled to the first polarized signal optical port of the first chip, a second polarized signal optical port coupled to the second polarized signal optical port of the first chip, a multi-polarized signal optical port, and a polarization rotating and combining (PRC) element that couples the first polarized signal optical port and the second polarized signal optical port of the second chip to the multi-polarized signal optical port of the second chip (figure 10 depicts the process of the polarization rotator 125m beam combiner 126 function, as well as the TE and TM modes at the rotator 27 in figure 3);
wherein the first chip comprises a first semiconductor chip material; and
wherein the second chip comprises a second semiconductor chip material that is different than the first semiconductor chip material (Sugiyama claim 6).
As to claim 4, GaAlAs is used (paragraph 50).
As to claim 5, the device is configured to perform this function (figure 10 and paragraph 38).
However, Sugiyama fails to explicitly disclose a first and second optical amplifier paired with their respective modulators. It is noted that adding amplifiers to a source chip or source modulator is common in the art.
Joyner discloses such in figure 2 and paragraph 9, where a photo diode (PD1) is paired with both an amplifier (SOA) and modulator (MOD) in a first chip (CH2-1). Such prevents signal degredation before passing the signal to a rotator (ROT) and combiner (PBC).
It would have been obvious to one having ordinary skill in the art to either rearrange an amplifier to a first or second chip paired with the modulators or to add additional amplifiers as taught by Joyner in Sugiyama to prevent signal degradation.
Claim(s) 2-3 and 6-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sugiyama in view of Joyner and further in view of US 2016/0033728 to Kish et al.
Sugiyama in view of Joyner discloses the invention as claimed except for certain configurations, materials and additional ports.
Kish discloses these materials (applicant claims 2-3), configurations in Kish figure 6 (applicant claims 4-7). Kish also discloses the use of adhesives to bond components in paragraph 40 (relates to Applicant claims 17-18). Remaining claims similarly add ports and functions disclosed by both Sugiyama and Kish.
It would have been obvious to use known materials and to configure a semiconductor chip to use multiple functions as a matter of obvious design choice.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Eric K Wong whose telephone number is (571)272-2363. The examiner can normally be reached M-Tu, Th-F 8A-6P.
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ERIC K. WONG
Primary Examiner
Art Unit 2874
/Eric Wong/Primary Examiner, Art Unit 2874
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