Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Claims 1-20 pending.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 2-9, 12-19 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 2, the phrase “add the offset to the first chirp signal” renders the claim indefinite. It is unclear, e.g., whether this offset is added to the first chirp signal transmitted through the first antenna. Examiner’s best interpretation is that the offset is not added to the first chirp signal transmitted through the first antenna, but is a further description of the generation of the second chirp signal comprising adding an offset to the first chirp signal. The phrase “a coupling signal component coupled to the second antenna on the path of the first chip signal transmitted through the first antenna” further renders the claim indefinite. It is not clear how a signal component can be “coupled to” an antenna. It is further unclear how a signal component can be “coupled… on the path of the first chip signal.” Examiner’s best interpretation is that this coupling signal refers to a direct coupling signal between the first and second antennas. Appropriate correction is required. Claim 12 recites a similar limitation and is indefinite for similar reasons. Claims 3-9, 13-19 rejected as dependent.
Regarding claim 3, the phrase “mix the second chirp signal with the reception signal to lower the frequency of the third signal” renders the claim indefinite because the third signal is already generated by mixing the second chirp signal with the reception signal. The phrase “lower the frequency of the third signal” renders the claim indefinite. It is unclear to what the frequency of the third signal is lower than, e.g., it is unclear whether the frequency of the third signal is lower than it would have been without the added offset, lower than the frequency of another signal, lower than a threshold, etc. It is further unclear how “mix the second chirp signal with the reception signal… by mixing the second chirp signal with the reception signal” may occur. Claim 13 recites a similar limitation and is indefinite for similar reasons.
Regarding claim 12, “the chipset of claim 1” and “the signal generator” lack antecedent basis. Because of this, and because the claim appears to be a “chipset” claim corresponding to “electronic device” claim 2, Examiner’s best interpretation is that claim 12 is meant to depend from claim 11, which does recite a chipset and a single signal generator. This interpretation will be used in this Office Action for purposes of examination. Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-5, 7, 11, 12-15, 17 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 20210165088 A1 to Suzuki.
Regarding claim 1,
Suzuki teaches:
An electronic device comprising: (Fig. 10)
a first antenna; (Fig. 10 – transmitting antenna 13)
a second antenna; (Fig. 10 – receiving antenna 21 or 31)
a first signal generator configured to generate a first chirp signal; (Fig. 10 – chirp generator circuit 11a)
a second signal generator configured to generate a second chirp signal by adding an offset to the first chirp signal; (Fig. 10; [0075-77] – “the output of the delay circuit 5 is input as the reception chirp signal to the mixer 23a”) and
a processor operatively connected with the first signal generator and the second signal generator, (Fig. 10 – signal processing unit 4) wherein the processor is configured to:
control the first signal generator to transmit the first chirp signal through the first antenna; (Fig. 10 – transmitting antenna 13, transmission chirp signal 60)
control to receive a reception signal through a second antenna in association with the first chirp signal transmitted through the first antenna; (Fig. 10 – receiving antenna 21 or 31, received reflected wave 64)
control to mix the second chirp signal with the reception signal to generate a third signal; (Fig. 10 – mixer 32a or 33a; [0047] – “the mixer 23a perform mixing on the received signal received via the receiving antenna 21, thereby generating a frequency difference signal (i.e., a beat signal) between the received signal and the reception chirp signal.” [0075-77] – “the RF signal source 22 is omitted, and the output of the delay circuit 5 is input as the reception chirp signal to the mixer 23a.”) and
control to filter the third signal. (Fig. 10 – high-pass filter (HPF) 23b or 33b)
Regarding claim 2,
Suzuki teaches the invention as claimed and discussed above.
Suzuki further teaches:
The electronic device of claim 1, wherein the processor is configured to control the second signal generator to add the offset to the first chirp signal ([0076] – “A timing signal output from the timing control unit 42 to the delay circuit 5 provides the transmission chirp signal with the delay time τ as illustrated in the bottom diagram of FIG. 8”) for correcting, from the reception signal, a coupling signal component coupled to the second antenna on the path of the first chip signal transmitted through the first antenna. (Figs. 8-9; [0071-73] – “As illustrated in FIG. 9, the direct wave component is a low frequency component close to the DC component, and it is therefore difficult to separate the two in terms of frequency. On the other hand, when the output timing of the reception chirp signal is shifted from that of the transmission chirp signal as in the second embodiment, the frequency of the direct wave component increases.” Examiner notes that the broadest reasonable interpretation of “the offset… for correcting… a coupling signal component” includes any offset that results in a change to a coupling signal component.)
Regarding claim 3,
Suzuki teaches the invention as claimed and discussed above.
Suzuki further teaches:
The electronic device of claim 2, wherein the processor is configured to control to mix the second chirp signal with the reception signal to lower the frequency of the third signal ([0047] – “the mixer 23a perform mixing on the received signal received via the receiving antenna 21, thereby generating a frequency difference signal (i.e., a beat signal) between the received signal and the reception chirp signal.” See rejection under 35 U.S.C. § 112b.) for the coupling signal component to be removed from the reception signal by mixing the second chirp signal with the reception signal and for passing a reflection signal component of the reception signal upon filtering of the third signal, wherein the reflection signal component represents the first chirp signal transmitted through the first antenna and reflected by an external object. ([0047] – “To detect the target 50, a direct current component and a predetermined low-frequency component included in the beat signal are suppressed by the HPF 23b. The amplifier 23c amplifies the signal output from the HPF 23b. The ADC 23d converts the output of the amplifier 23c into a digital signal.” Suppressed low-frequency component may correspond to removed coupling signal.)
Regarding claim 4,
Suzuki teaches the invention as claimed and discussed above.
Suzuki further teaches:
The electronic device of claim 2, wherein the processor is configured to control to add the offset to the first chirp signal to generate the second chirp signal based on a time delay (Figs. 8-10; [0076] – “the delay time of the delay circuit 5 is controlled by the timing control unit 42 of the signal processing unit 4. A timing signal output from the timing control unit 42 to the delay circuit 5 provides the transmission chirp signal with the delay time τ”) or a frequency difference to the first chirp signal.
Regarding claim 5,
Suzuki teaches the invention as claimed and discussed above.
Suzuki further teaches:
The electronic device of claim 4, wherein the second signal generator comprises a delay circuit configured to delay the first chirp signal based on a propagation time of the reception signal to generate the second chirp signal. (Fig. 10; [0076-77] – “Needless to say, the transmission time due to the electrical wiring between the transmission module 1 and the reception modules 2A and 3A is taken into consideration in providing the delay time τ for the transmission chirp signal.” Transmission time of reflected wave 64 through reception module 2A/3A corresponds to a propagation time of the reception signal)
Regarding claim 7,
Suzuki teaches the invention as claimed and discussed above.
Suzuki further teaches:
The electronic device of claim 4, wherein the processor is configured to control the second signal generator to generate the second chirp signal based on a frequency difference between the reception signal and the first chirp signal. (In regard to claim 7, the limitation(s) recited is not required to be part of the claimed invention. Parent claim 4 teaches alternative limitations, i.e., "a time delay" is listed in the alternative with “a frequency difference”. If a parent claim includes alternative limitations, and the reference teaches one of them, further limitations to the other alternative(s) in dependent claims are not required limitations. See Ex parte Werner, Appeal 2019-001448, Application No. 15/109,888, March 23, 2020, 15 pages. Here, Suzuki teaches a time delay, as detailed in the rejection of claim 4. Claim 7 further limits another alternative/other alternatives, i.e., a frequency difference.)
Regarding claim 11,
Suzuki teaches:
A chipset comprising:
a signal generator; (Fig. 10 – chirp generator circuit 11a) and
circuitry configured to:
control the signal generator to transmit a first chirp signal through a first antenna (Fig. 10 – transmitting antenna 13, transmission chirp signal 60) and to generate a second chirp signal by applying an offset to the first chirp signal, (Fig. 10; [0075-77] – “the output of the delay circuit 5 is input as the reception chirp signal to the mixer 23a”)
receive a reception signal through a second antenna in association with the first chirp signal transmitted through the first antenna, (Fig. 10 – receiving antenna 21 or 31, received reflected wave 64)
mix the second chirp signal with the reception signal to generate a third signal, (Fig. 10 – mixer 32a or 33a; [0047] – “the mixer 23a perform mixing on the received signal received via the receiving antenna 21, thereby generating a frequency difference signal (i.e., a beat signal) between the received signal and the reception chirp signal.” [0075-77] – “the RF signal source 22 is omitted, and the output of the delay circuit 5 is input as the reception chirp signal to the mixer 23a.”) and
filter the third signal. (Fig. 10 – high-pass filter (HPF) 23b or 33b)
Regarding claim(s) 12-15, 17,
Claim(s) 12-15, 17 is/are chip set claims corresponding to electronic device claim(s) 2-5, 7, respectively. Accordingly, the Examiner’s remarks and application of the prior art with respect to claim(s) 12-15, 17 are substantially the same as those made above with respect to claim(s) 2-5, 7.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 6, 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20210165088 A1 to Suzuki in view of 3.3V ECL Programmable Delay Chip (cited in IDS).
Regarding claim 6,
Suzuki teaches the invention as claimed and discussed above.
Suzuki does not explicitly teach the additional elements of the claim.
3.3V ECL Programmable Delay Chip teaches:
The electronic device of claim 5, wherein the delay circuit comprises a plurality of delay cells, and wherein the processor is configured to control the delay circuit to pass the first chirp signal through a specified number of delay cells among the plurality of delay cells based on the propagation time. ([pg. 11] – “cascading of multiple EP195s… cascading multiple programmable delay chips will result in a larger programmable range”)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have applied 3.3V ECL Programmable Delay Chip’s known technique to Suzuki’s known method ready for improvement to yield predictable results. Such a finding is proper because (1) Suzuki teaches a base method of adding an offset based on propagation time via a delay circuit; (2) 3.3V ECL Programmable Delay Chip teaches a specific technique using a plurality of programmable delay chips to achieve a desired delay time; (3) one of ordinary skill in the art would have recognized that applying the known technique would have yielded predictable results and resulted in an improved system; and (4) no additional findings based on the Graham factual inquiries are necessary, in view of the facts of the case under consideration, to explain a conclusion of obviousness (See MPEP 2143).
Regarding claim(s) 16,
Claim(s) 16 is/are chip set claims corresponding to electronic device claim(s) 6, respectively. Accordingly, the Examiner’s remarks and application of the prior art with respect to claim(s) 16 are substantially the same as those made above with respect to claim(s) 6.
Claim(s) 8, 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20210165088 A1 to Suzuki in view of US 20080316090 A1 to Shirakawa.
Regarding claim 8,
Suzuki teaches the invention as claimed and discussed above.
Suzuki does not explicitly teach the additional elements of the claim.
Shirakawa teaches:
The electronic device of claim 7, wherein the processor is configured to generate a digital code corresponding to the second chirp signal based on a digital code ([0008-10] – “The mixer 132 multiplies the down-converted received signal and the PN code (or SS code for demodulation) which is delayed by a delay time .tau..sub.n by a delay circuit 130… the delay circuit 130 outputs the SS code to the mixer 132 while shifting the SS code by a predetermined multiple of one chip duration T.sub.c, such as 1/3 the chip duration T.sub.c, for example. Hence, the PN code having a predetermined delay time mT.sub.c is multiplied to the received signal in the mixer, and is integrated for the code period T.sub.f by the integrator 134.”) corresponding to the first chirp signal. ([0005] – “FIG. 1 is a system block diagram, that is, a simulation model, of a DSSS radar. The DSSS radar first generates a PN code having a suitable length and timing by a code generator 102, and uses this PN code as a system reference signal (or baseband signal) .nu..sub.TX(t) which characterizes the signal transmitted from this DSSS radar.”)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have applied Shirakawa’s known technique to Suzuki’s known method ready for improvement to yield predictable results. Such a finding is proper because (1) Suzuki teaches a base method of generating a second signal by adding an offset to the chirps used to generate a first signal; (2) Shirakwa teaches a specific technique of implementing the base method via code; (3) one of ordinary skill in the art would have recognized that applying the known technique would have yielded predictable results and resulted in an improved system; and (4) no additional findings based on the Graham factual inquiries are necessary, in view of the facts of the case under consideration, to explain a conclusion of obviousness (See MPEP 2143).
Regarding claim(s) 18,
Claim(s) 18 is/are chip set claims corresponding to electronic device claim(s) 8, respectively. Accordingly, the Examiner’s remarks and application of the prior art with respect to claim(s) 18 are substantially the same as those made above with respect to claim(s) 8.
Claim(s) 9, 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20210165088 A1 to Suzuki in view of US 20080316090 A1 to Shirakawa and further in view of US 10018716 B2 to Ferguson.
Regarding claim 9,
Suzuki in view of Shirakawa teaches the invention as claimed and discussed above.
Shirakawa further teaches:
The electronic device of claim 8, wherein the processor is configured to generate the digital code corresponding to the second chirp signal by adding an offset obtained from the chip index (lined through limitations correspond to limitations not taught by reference) of the reception signal to the first digital code corresponding to the first chirp signal. ([0008-10] – “The mixer 132 multiplies the down-converted received signal and the PN code (or SS code for demodulation) which is delayed by a delay time .tau..sub.n by a delay circuit 130… the delay circuit 130 outputs the SS code to the mixer 132 while shifting the SS code by a predetermined multiple of one chip duration T.sub.c, such as 1/3 the chip duration T.sub.c, for example. Hence, the PN code having a predetermined delay time mT.sub.c is multiplied to the received signal in the mixer, and is integrated for the code period T.sub.f by the integrator 134.”)
Ferguson teaches:
adding an offset obtained from the frequency of the reception signal ([col. 7, para 2] – “tuning the variable series capacitor 136, to adjust the peak-to-peak delay variation for signals with different frequencies, may change the delay in the LO delay line 108.”)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have applied Shirakawa’s known technique to Suzuki’s known method ready for improvement to yield predictable results. Such a finding is proper because (1) Suzuki teaches a base method of generating a second signal by adding an offset to the chirps used to generate a first signal and choosing chirp parameters including frequency, delay time, and shape of chirp; (2) Ferguson teaches a specific technique of offset adjustment according to frequency; (3) one of ordinary skill in the art would have recognized that applying the known technique would have yielded predictable results and resulted in an improved system; and (4) no additional findings based on the Graham factual inquiries are necessary, in view of the facts of the case under consideration, to explain a conclusion of obviousness (See MPEP 2143).
Regarding claim(s) 19,
Claim(s) 19 is/are chip set claims corresponding to electronic device claim(s) 9, respectively. Accordingly, the Examiner’s remarks and application of the prior art with respect to claim(s) 19 are substantially the same as those made above with respect to claim(s) 9.
Allowable Subject Matter
Claims 10, 20 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for indicating allowable subject matter: The closest prior art of record (US 20210165088 A1 to Suzuki; US 20080316090 A1 to Shirakawa; 3.3V ECL Programmable Delay Chip (cited in IDS)) neither teaches nor fairly renders obvious the combinations set forth in claims 10, 20. See analysis regarding claims 10 below. Claim(s) 20 recite similar limitation(s) to claims 10 and is/are indicated as allowable subject matter for similar reasons.
Regarding claim 10, the prior art of record does not teach, in combination with the remaining elements of the claim:
measure a frequency of the reception signal received through the second antenna, calculate the offset based on the measured frequency of the reception signal and store the calculated offset for generating the second chirp signal.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JULIANA CROSS whose telephone number is (571)272-8721. The examiner can normally be reached Mon-Fri 9am-5pm Pacific time.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Kelleher can be reached on (571) 272-7753. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JULIANA CROSS/Examiner, Art Unit 3648
/William Kelleher/Supervisory Patent Examiner, Art Unit 3648