Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Allowable Subject Matter
Claim 8, 11, 13, 19, 20, 23-26 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 2, 4, 6, 7, 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tomikawa et al. (US 20160105957 A1) hereafter referred to as Tomikawa in view of Ishigaki et al. (US 6191933 B1) hereafter referred to as Ishigaki
In regard to claim 1 Tomikawa teaches a method [“a first embodiment of the present invention is described based on FIG. 1-13” see Fig. 11, “FIG. 7A-7D are cross-sectional side views illustrating processes for manufacturing a wiring board with a built-in electronic component”] comprising:
providing a multi-layer ceramic [“A multilayer ceramic capacitor 17 (hereinafter, referred to as a “MLCC 17”) as an electronic component is accommodated in the cavity 16”] capacitor (MLCCs);
placing the multi-layer ceramic capacitors (MLCC) [“As illustrated in FIG. 7A, the MLCC 17 is accommodated in the cavity 16 using a mounter”] onto a base sheet [“tape 90 made of a PET film is affixed to the F surface (11F) of the core substrate 11 so as to close the cavity 16”];
forming a resin-based substrate [“As illustrated in FIG. 7B, a prepreg (a resin sheet of a B-stage formed by impregnating a core material with resin) as the first insulating resin layer 21 and a copper foil 37 are laminated on the conductor circuit layer 12 on the F surface (11F) of the core substrate 11, and then, the resulting substrate is hot-pressed. In doing so, spacing between the conductor circuit layers (12, 12) on the S surface (11S) of the core substrate 11 is filled with the prepreg, and a gap between the inner surface of the cavity 16 and the MLCC 17 is filled with thermosetting resin exuded from the prepreg”] by applying a resin on the multilayer ceramic capacitors (MLCCs) disposed on the base sheet;
removing the base sheet [“As illustrated in FIG. 7C, the tape 90 is removed” “As illustrated in FIG. 7D, a prepreg as the first insulating resin layer 21 and a copper foil 37 are laminated on the conductor circuit layer 12 on the F surface (11F) of the core substrate 11, and then, the resulting substrate is hot-pressed. In doing so, spacing between the conductor circuit layers (12, 12) on the F surface (11F) of the core substrate 11 is filled with the prepreg, and a gap between an inner surface of the cavity 16 and the MLCC 17 is filled with thermosetting resin exuded from the prepreg” “Instead of the prepreg, it is also possible to use a resin film that does not contain a core material as the first insulating resin layer 21”];
forming a redistribution layer (RDL) in [see Figs. 8, 9, 10 “first insulating resin layers (21, 21) and in the via holes (21H, 21H)” “electrolytic plating treatment is performed” “via conductors (21D, 21D) are formed” “On each of the pads 26, a nickel layer, a palladium layer and a gold layer are laminated in this order and a metal film 41 illustrated in FIG. 1 is formed. As a result, the wiring board 10 with a built-in electronic component is completed”] an insulating layer on the resin-based substrate;and
coupling an integrated circuit (IC) [“a CPU 80 having on a lower surface a group of pads that are positioned in the same way as the group of the small pads of the F surface (10F) of the wiring board 10 with a built-in electronic component is mounted on and is soldered to the group of the small solder bumps (27C) of each product region (R2), and a first package substrate (10P) is formed. Here, the pads of the CPU 80 are connected to the MLCC 17 via the via conductors (21D, 23D)”] to the resin-based substrate
but does not state that the MLCC are “plurality of”,
however this is common in the art, see Ishigaki Figs. 8-18, see Fig. 26 “FIG. 26 illustrates a combined ceramic capacitor constituted by combining a plurality of ceramic capacitor elements 110 to 150” “The plurality of ceramic capacitor elements 110 to 150 are combined with their terminal electrodes 11 aligned with one another and their terminal electrodes 12 aligned with one another to constitute a capacitor assembly. The metal plate terminals 2 and 3 are secured onto the terminal electrodes 11 and 12 provided at the two ends of the capacitor assembly via solders 4 and 5 respectively”.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Tomikawa to include that the MLCC are “plurality of”.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is to obtain more capacitance by utilizing a plurality of capacitors attached together.
In regard to claim 2 Tomikawa and Ishigaki as combined does not specifically teach wherein the resin comprises an epoxy.
However epoxy is standard in the art, see Tomikawa “As illustrated in FIG. 5A, a substrate as the core substrate 11 is prepared that is obtained by laminating a copper foil (11C) on each of both front and back surfaces of an insulating base material (11K) that is made of epoxy resin or BT (bismaleimide triazine) resin and a reinforcing material such as a glass cloth”.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Tomikawa to include wherein the resin comprises an epoxy.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is that epoxy is a strong material and known to give excellent results as insulation in packages.
In regard to claim 4 Tomikawa and Ishigaki as combined teaches wherein at least two MLCCs of the plurality of MLCCs are [see combination to obtain more capacitance by utilizing a plurality of capacitors attached together] electrically coupled to each other.
In regard to claim 6 Tomikawa and Ishigaki as combined teaches [see pads are where the solder is connected, “a CPU 80 having on a lower surface a group of pads that are positioned in the same way as the group of the small pads of the F surface (10F) of the wiring board 10 with a built-in electronic component is mounted on and is soldered to the group of the small solder bumps (27C) of each product region (R2), and a first package substrate (10P) is formed. Here, the pads of the CPU 80 are connected to the MLCC 17 via the via conductors (21D, 23D)”] further comprising forming at least one pad on the RDL.
In regard to claim 7 Tomikawa and Ishigaki as combined teaches [see solder connection, “a CPU 80 having on a lower surface a group of pads that are positioned in the same way as the group of the small pads of the F surface (10F) of the wiring board 10 with a built-in electronic component is mounted on and is soldered to the group of the small solder bumps (27C) of each product region (R2), and a first package substrate (10P) is formed. Here, the pads of the CPU 80 are connected to the MLCC 17 via the via conductors (21D, 23D)”] wherein the IC is coupled to the resin-based substrate by at least one solder bump or copper pillar on the at least one pad.
In regard to claim 10 Tomikawa and Ishigaki as combined teaches [see solder connection, “a CPU 80 having on a lower surface a group of pads that are positioned in the same way as the group of the small pads of the F surface (10F) of the wiring board 10 with a built-in electronic component is mounted on and is soldered to the group of the small solder bumps (27C) of each product region (R2), and a first package substrate (10P) is formed. Here, the pads of the CPU 80 are connected to the MLCC 17 via the via conductors (21D, 23D)”] wherein the IC is electrically coupled to at least one MLCC of the plurality of MLCCs.
Claim(s) 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tomikawa et al. (US 20160105957 A1) hereafter referred to as Tomikawa in view of Ishigaki et al. (US 6191933 B1) hereafter referred to as Ishigaki
In regard to claim 22 Tomikawa teaches a [“a first embodiment of the present invention is described based on FIG. 1-13” see Fig. 11, “Package on Package 83” “FIG. 7A-7D are cross-sectional side views illustrating processes for manufacturing a wiring board with a built-in electronic component”] package comprising:
a MLCC-based substrate comprising a [“As illustrated in FIG. 7B, a prepreg (a resin sheet of a B-stage formed by impregnating a core material with resin) as the first insulating resin layer 21 and a copper foil 37 are laminated on the conductor circuit layer 12 on the F surface (11F) of the core substrate 11, and then, the resulting substrate is hot-pressed. In doing so, spacing between the conductor circuit layers (12, 12) on the S surface (11S) of the core substrate 11 is filled with the prepreg, and a gap between the inner surface of the cavity 16 and the MLCC 17 is filled with thermosetting resin exuded from the prepreg”] multilayer ceramic capacitors (MLCCs) embedded in a resin,
wherein a bottom surface [“As illustrated in FIG. 7C, the tape 90 is removed” “As illustrated in FIG. 7D, a prepreg as the first insulating resin layer 21 and a copper foil 37 are laminated on the conductor circuit layer 12 on the F surface (11F) of the core substrate 11, and then, the resulting substrate is hot-pressed. In doing so, spacing between the conductor circuit layers (12, 12) on the F surface (11F) of the core substrate 11 is filled with the prepreg, and a gap between an inner surface of the cavity 16 and the MLCC 17 is filled with thermosetting resin exuded from the prepreg” “Instead of the prepreg, it is also possible to use a resin film that does not contain a core material as the first insulating resin layer 21”] of the MLCC- based substrate is defined by the resin;
a redistribution layer (RDL) in [see Figs. 8, 9, 10 “first insulating resin layers (21, 21) and in the via holes (21H, 21H)” “electrolytic plating treatment is performed” “via conductors (21D, 21D) are formed” “On each of the pads 26, a nickel layer, a palladium layer and a gold layer are laminated in this order and a metal film 41 illustrated in FIG. 1 is formed. As a result, the wiring board 10 with a built-in electronic component is completed”] an insulating layer on the MLCC- based substrate;
an integrated circuit (IC) disposed over [“a CPU 80 having on a lower surface a group of pads that are positioned in the same way as the group of the small pads of the F surface (10F) of the wiring board 10 with a built-in electronic component is mounted on and is soldered to the group of the small solder bumps (27C) of each product region (R2), and a first package substrate (10P) is formed. Here, the pads of the CPU 80 are connected to the MLCC 17 via the via conductors (21D, 23D)”] and coupled to the MLCC-based substrate
but does not state that the MLCC are “plurality of” and wherein each MLCC of the plurality of MLCCs directly contacts another MLCC,
however this is common in the art, see Ishigaki Figs. 8-18, see Fig. 26 “FIG. 26 illustrates a combined ceramic capacitor constituted by combining a plurality of ceramic capacitor elements 110 to 150” “The plurality of ceramic capacitor elements 110 to 150 are combined with their terminal electrodes 11 aligned with one another and their terminal electrodes 12 aligned with one another to constitute a capacitor assembly. The metal plate terminals 2 and 3 are secured onto the terminal electrodes 11 and 12 provided at the two ends of the capacitor assembly via solders 4 and 5 respectively”.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Tomikawa to include that the MLCC are “plurality of” and wherein each MLCC of the plurality of MLCCs directly contacts another MLCC.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is to obtain more capacitance by utilizing a plurality of capacitors attached together.
Claim(s) 27-30 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. (US 20210013162 A1) hereafter referred to as Zhang in view of Tomikawa et al. (US 20160105957 A1) hereafter referred to as Tomikawa
In regard to claim 27 Zhang teaches a method [“FIG. 2 is a cross-sectional view of a first preferred three-dimensional (3-D) module” “FIGS. 4A-4H illustrate the process flow of the first preferred 3-D module at various processing steps”] comprising:
providing a plurality [“second device level 210 includes a plurality of devices such as two MLCC capacitors 210x, 210y”] of multi-layer ceramic capacitors (MLCCs);
depositing a organic [“These devices 210x, 210y are surrounded and mechanically interconnected by a second structural material 212” see that 200 is similar to 100 see Fig. 4E “the structural material 112 is a low-k dielectric material” see Abstract low-k “a low-k dielectric (e.g. organic) material”] over the plurality of MLCCs to form a substrate;
forming a conductive pillar [see Fig. 2 “the inter-level connections 290 are vias, e.g. through-silicon vias (TSV) widely used in 3-D packaging”] through the substrate, wherein the conductive pillar extends through the organic [see Fig. 2] adjacent at least one of the plurality of MLCCs;
forming a redistribution layer (RDL) over the substrate [see Fig. 2 see that 290 connects to “second metallization layers 274” and also “first metallization layers 174” “Finally, the first and second sub-modules 100, 200 are vertically stacked via a glue layer 282 (FIG. 2). The sub-modules 100, 200 are electrically coupled though inter-level connections 290”], wherein a conductive feature of the RDL connects to the conductive pillar,
but does not state that the organic is resin.
However resin is a common material for insulating layers, see Tomikawa “As illustrated in FIG. 7C, the tape 90 is removed” “As illustrated in FIG. 7D, a prepreg as the first insulating resin layer 21 and a copper foil 37 are laminated on the conductor circuit layer 12 on the F surface (11F) of the core substrate 11, and then, the resulting substrate is hot-pressed. In doing so, spacing between the conductor circuit layers (12, 12) on the F surface (11F) of the core substrate 11 is filled with the prepreg, and a gap between an inner surface of the cavity 16 and the MLCC 17 is filled with thermosetting resin exuded from the prepreg” “Instead of the prepreg, it is also possible to use a resin film that does not contain a core material as the first insulating resin layer 21” “As illustrated in FIG. 5A, a substrate as the core substrate 11 is prepared that is obtained by laminating a copper foil (11C) on each of both front and back surfaces of an insulating base material (11K) that is made of epoxy resin or BT (bismaleimide triazine) resin and a reinforcing material such as a glass cloth”.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Zhang to include that the organic is resin.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is resin is a common material used to form insulating layers and known to be easy to use and gives good results as insulation in packages.
In regard to claim 28 Zhang and Tomikawa as combined teaches wherein another conductive feature of the RDL connects [see Zhang Fig. 2, see 210x and 210y have connections above] to a first MLCC of the plurality of MLCCs.
In regard to claim 29 Zhang and Tomikawa as combined teaches wherein the forming the RDL includes forming an insulating layer interfacing [see Fig. 4F “The first interconnect level 170 is disposed on the first device level 110. It includes a plurality of first dielectric layers 172, first metallization layers 174, first inter-layer vias 176 for electrically coupling first metallization layers 174”] a first surface of the substrate defined by the resin.
In regard to claim 30 Zhang and Tomikawa as combined teaches wherein a second surface of the substrate opposing [see the bottom surface is planar i.e. the bottom of the resin is the bottom surface plane] the first surface is defined by the resin.
Response to Arguments
Applicant's arguments filed 8/10/2026 have been fully considered but they are not persuasive.
Applicant’s arguments with respect to claim(s) 1-30 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SITARAMARAO S YECHURI whose telephone number is (571)272-8764. The examiner can normally be reached M-F 8:00-4:30 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt D Hanley can be reached at 571-270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SITARAMARAO S YECHURI/ Primary Examiner, Art Unit 2893
