CTNF 18/600,443 CTNF 88242 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Objections 07-29-01 AIA Claim 22 objected to because of the following informalities: Claim 22 recites “forming” in a structure claim . Appropriate correction is required. Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-23-aia AIA The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. 07-21-aia AIA Claim (s) 1-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nad et al. (US 20250218982 A1) hereafter referred to as Nad in view of Lee et al. (US 20190378795 A1) hereafter referred to as Lee. Lee is also provided as evidence . In regard to claim 1 Nad teaches a method [see Fig. 31, see paragraph 0081] comprising: forming a MLCC-based substrate [“more than one MLCC 210 may be stacked in the cavity 214 of an integrated circuit component 3100, as shown in FIG. 31” “the cavity 214 may only have MLCCs 210 embedded within it”] by forming a filler [see paragraph 0059 “The volume of the cavity 214 that is not taken up by the power components 208, 210 may be filled with any suitable filler material 224. For example, the filler material 224 may be prepreg, Ajinomoto build-up film (ABF), photoimageable dielectric, an inorganic dielectric material, an organic dielectric material, an oxide, a nitride, silicon dioxide, silicon nitride, polymer, epoxy, polyimide, polymer composites with inorganic fillers, and/or the like. The filler material 224 may be applied using any suitable approach, such as compression molding, vacuum lamination, hot press, chemical vapor deposition, physical vapor deposition, and/or the like”] on a plurality of multilayer ceramic capacitors (MLCCs), wherein each MLCC of the plurality of MLCCs [“power components 208, 210 may be attached together in any suitable manner, such as by using an adhesive 212, such as die attach film 212. Additionally or alternatively, the power components 208, 210 may be attached together using, e.g., glue epoxy, bump bonding, hybrid bonding, fusion bonding, thermocompression bonding, wafer on wafer bonding, wafer-on-wafer hybrid bonding, solder with underfill, and/or the like”] directly contacts another MLCC; forming a redistribution layer [“the circuit board 102 is a multi-layer circuit board 102 with build-up layers 204, 206 above and below the substrate core 202. The build-up layers 204, 206 may have any suitable number of layers, such as 1-10 layers each” “circuit board 102 includes traces 218 and vias 220. The traces 218 and vias 220 may be made of any suitable conductive material, such as copper or aluminum” “electrodes for the capacitor may be coupled to traces 218 or pads 218 defined in the build-up layers 204, 206” “pads 218 and vias 220 in the build-up layers 204, 206” “build-up layers 204, 206 may be created using any suitable set of techniques, such as electroplating, electroless plating, photolithography, etching, etc” see by “circuit board” Nad means metal and dielectric, see “circuit board 3602 may be a printed circuit board (PCB) including multiple metal (or interconnect) layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias”] (RDL) in an insulating layer on the MLCC-based substrate; coupling an integrated circuit [“In an illustrative embodiment, the die 104 above the power components 208, 210 is a processor die and other dies 106 may be memory dies communicatively coupled to the processor die 104”] (IC) to the MLCC-based substrate, but does not state that the filler is resin. However Nad uses “filler material 224 may be prepreg, Ajinomoto build-up film (ABF), photoimageable dielectric, an inorganic dielectric material, an organic dielectric material, an oxide, a nitride, silicon dioxide, silicon nitride, polymer, epoxy, polyimide, polymer composites with inorganic fillers, and/or the like” see Nad paragraph 0116 “an epoxy resin, a fiberglass-reinforced epoxy resin, an epoxy resin with inorganic fillers”, see that prepreg, Ajinomoto build-up film (ABF), polyimide usually contain resin, see evidence of Lee see paragraph 0032 “insulating material may include thermosetting resins (e.g., epoxy resin), thermoplastic resins (e.g., polyimide), or composite resins (e.g., prepreg, Ajinomoto build-up film (ABF)”. Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Nad to include that the filler is resin. Thus it would be obvious to combine the references to arrive at the claimed invention. The motivation is that epoxy resin, polyimide, prepreg, Ajinomoto build-up film (ABF) are known to give good results in resin form to form insulation layers. See that by “circuit board” Nad means metal and dielectric, see “circuit board 3602 may be a printed circuit board (PCB) including multiple metal (or interconnect) layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias” thus the claim limitation “in an insulating layer” is satisfied, however for the sake of completeness, the Examiner is also providing a 103 rejection. See Lee teaches see Fig. 2 see paragraph 0032 “mold layer 50 may be formed of or include an insulating resin (e.g., epoxy molding compound (EMC))” “A first upper insulating layer 52 may be provided on the mold top surface 50a” “Redistribution vias 54 may penetrate the first upper insulating layer 52 and the mold layer 50, and may be used to electrically connect the redistribution patterns 56 to the third connection conductive patterns 11c” “first upper insulating layer 52 and the second upper insulating layer 58 may independently include at least one of thermosetting resins (e.g., epoxy resin), thermoplastic resins (e.g., polyimide), ABF, or Photo-Imageable Dielectric (PID) resin” . Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Nad to include that “in an insulating layer”. Thus it would be obvious to combine the references to arrive at the claimed invention. The motivation is standard circuit layer of conductor and dielectric is known to give good results as interconnection layer for electronic devices. In regard to claim 2 Nad and Lee as combined teaches [see claim 1 “epoxy resin”] wherein the resin comprises an epoxy. In regard to claim 3 Nad and Lee as combined teaches [see combination, see Lee polyimide] wherein the insulating layer comprises a polyimide or an oxide. In regard to claim 4 Nad and Lee as combined does not specifically teach in Fig. 31 that wherein at least two MLCCs of the plurality of MLCCs are electrically coupled to each other. However see paragraph 0081 “In some embodiments, the MLCCs 210 may be connected by plating 238 of the cavity 214. In other embodiments, the MLCCs 210 may be connected through side mounts 3202 that are mated with the MLCCs 210 before the MLCCs 210 are inserted into the cavity 214 of an integrated circuit component 3200, as shown in FIG. 32” “Additionally or alternatively, the TSVs 3002 may allow for the power components 208, 210 to be connected together, such as by connecting DTCs 208, 210 together in parallel or series”. Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Nad to include that wherein at least two MLCCs of the plurality of MLCCs are electrically coupled to each other. Thus it would be obvious to combine the references to arrive at the claimed invention. The motivation is to adjust the capacitance of the circuit as desired. In regard to claim 5 Nad and Lee as combined in claim 4 does not specifically teach wherein the plurality of MLCCs have a same voltage rating. However note that “connecting DTCs 208, 210 together in parallel” implies that they must have the same voltage rating, because otherwise the combination would have the lower of the two voltage rating. Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Nad to include wherein the plurality of MLCCs have a same voltage rating. The motivation is to obtain best reliability by avoiding dissimilar voltage rating for placing parallel components. In regard to claim 6 Nad and Lee as combined teaches [see Nad Fig. 31 “dies 104, 106 may be connected to contact pads or vias 220 on the circuit board 102 through solder balls 222”] further comprising forming at least one pad on the RDL. In regard to claim 7 Nad and Lee as combined teaches [see Nad Fig. 31 “dies 104, 106 may be connected to contact pads or vias 220 on the circuit board 102 through solder balls 222”] wherein the IC is coupled to the MLCC-based substrate by at least one solder bump or copper pillar on the at least one pad. In regard to claim 8 Nad and Lee as combined teaches wherein the RDL comprises [see combination Lee the RDL has conductive and dielectric, thus a dielectric can be called as passivation, see Nad Fig. 31 the pad connects to 222, see combination Lee see in Lee the pad is on 52 and is exposed by an opening in 58] a first passivation layer and the at least one pad is on the first passivation layer. In regard to claim 9 Nad and Lee as combined teaches wherein the RDL comprises a second passivation layer [see combination Lee the RDL has conductive and dielectric, thus a dielectric can be called as passivation, see Nad Fig. 31 the pad connects to 222, see combination Lee see in Lee the pad is on 52 and is exposed by an opening in 58] and the at least one pad is between the first passivation layer and the second passivation layer. In regard to claim 10 Nad and Lee as combined does not specifically teach in Fig. 31 wherein the IC is electrically coupled to at least one MLCC of the plurality of MLCCs. However see “The DTC 208 may be connected to the die 104, the dies 106, a component connected to the circuit board 102, etc., through various connections in the integrated circuit component 100, such as traces 218, vias 220, through holes 216, etc” “in an illustrative embodiment, the power component 208 is a DTC and the power component 210 is an MLCC. Additionally or alternatively, in some embodiments, one or both of the power components 208, 210 may be any suitable power component, such as a DTC, MLCC, a magnetic inductor array 208, 210, and/or the like”. Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Nad to include wherein the IC is electrically coupled to at least one MLCC of the plurality of MLCCs. The motivation is to use the capacitance of the MLCC in electrical connection to the die to provide capacitance. In regard to claim 11 Nad and Lee as combined does not specifically teach in Fig. 31 wherein coupling the IC to the MLCC-based substrate comprises thermo-compression bonding. However see Nad paragraph 0058 “The power components 208, 210 may be attached together in any suitable manner, such as by using an adhesive 212, such as die attach film 212. Additionally or alternatively, the power components 208, 210 may be attached together using, e.g., glue epoxy, bump bonding, hybrid bonding, fusion bonding, thermocompression bonding, wafer on wafer bonding, wafer-on-wafer hybrid bonding, solder with underfill, and/or the like”. Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Nad to include wherein coupling the IC to the MLCC-based substrate comprises thermo-compression bonding. The motivation is to obtain tighter, stronger connections by bonding which are known to give excellent electrical connectivity. In regard to claim 12 Nad and Lee as combined does not specifically teach in Fig. 31 wherein coupling the IC to the MLCC-based substrate comprises hybrid bonding. However see Nad paragraph 0058 “The power components 208, 210 may be attached together in any suitable manner, such as by using an adhesive 212, such as die attach film 212. Additionally or alternatively, the power components 208, 210 may be attached together using, e.g., glue epoxy, bump bonding, hybrid bonding, fusion bonding, thermocompression bonding, wafer on wafer bonding, wafer-on-wafer hybrid bonding, solder with underfill, and/or the like”. Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Nad to include wherein coupling the IC to the MLCC-based substrate comprises hybrid bonding. The motivation is to obtain tighter, stronger connections by bonding which are known to give excellent electrical connectivity. In regard to claim 13 Nad and Lee as combined does not specifically teach wherein the hybrid bonding is between at least one plug of the IC and at least one plug embedded in the insulating layer. However the Examiner notes that hybrid bonding is a standard technique, see that in Nad Fig. 31 “The dies 104, 106 may be connected to contact pads or vias 220 on the circuit board 102 through solder balls 22”, thus there are interconnects inside the die which are connected to the solder, see Nad teaches this can be “bump bonding, hybrid bonding, fusion bonding, thermocompression bonding, wafer on wafer bonding, wafer-on-wafer hybrid bonding” see Nad understands metal interconnections, “circuit board 102 includes traces 218 and vias 220. The traces 218 and vias 220 may be made of any suitable conductive material, such as copper or aluminum”, see use of posts “The integrated circuit device 3400 may include additional or alternate structures to route the electrical signals from the interconnect layers 3406-3410; for example, the conductive contacts 3436 may include other analogous features (e.g., posts) that route the electrical signals to external components”. See Lee paragraph 0047 “The first semiconductor package 100 may be electrically connected to the second semiconductor package 180 through package connecting elements 170. Each of the package connecting elements 170 may be or include at least one of a solder ball, a conductive bump, or a conductive pillar” see examples of 170 in the figures of Lee. Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Nad to include wherein the hybrid bonding is between at least one plug of the IC and at least one plug embedded in the insulating layer. Thus it would be obvious to combine the references to arrive at the claimed invention. The motivation is that such connections are strong and tight and known to give excellent electrical conductivity. In regard to claim 14 Nad and Lee as combined does not specifically teach wherein coupling the IC to the MLCC-based substrate comprises connecting the IC to the MLCC-based substrate with a wire. However wire bonding is a well-known and standard technique, which is easy to perform and gives good electrical connectivity. See Lee paragraph 0003 “a semiconductor chip which is mounted on the PCB and is electrically connected to the PCB by bonding wires or bumps” “The second chip conductive pads 152 may be connected to some of the second substrate upper conductive patterns 126 through wires 165”, see Fig. 6. Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Nad to include wherein coupling the IC to the MLCC-based substrate comprises connecting the IC to the MLCC-based substrate with a wire. Thus it would be obvious to combine the references to arrive at the claimed invention. The motivation is that wire bonding is a well-known and standard technique, which is easy to perform and gives good electrical connectivity. In regard to claim 15 Nad and Lee as combined does not specifically teach further comprising grinding the IC to 50 µm. However see Nad paragraph 0063 “In some embodiments, wafer-level thinning may be performed in block 304, leading to a thinner wafer 500, as shown in FIG. 6. Additionally or alternatively, in other embodiments, the DTCs 208, 210 may be thinned after dicing or the DTCs 208, 210 may not be thinned” see paragraphs 0049-0054 discussion of suitable thickness, see wafer level thinning “forming a plurality of power components on a semiconductor wafer; thinning the semiconductor wafer; and dicing the semiconductor wafer to form the first power component”. “wherein a difference between a thickness of the first power component and a thickness of the second power component is less than five micrometers”. Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Nad to include further comprising grinding the IC. The motivation is to make a thinner electronic component and to match thicknesses of 104, 106 etc. Nad and Lee as combined does not teach “to 50 µm”. See sample dimensions “power components 208, 210 may have any suitable dimensions, such as a height of 25 micrometers to 3 millimeters and a length and/or width of 0.1-20 millimeters”. It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to use “to 50 µm” , since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. In regard to claim 16 Nad and Lee as combined does not specifically teach in Fig. 31 further comprising forming a bump on a side of the MLCC-based substrate that is opposite to a side of the RDL. However see Fig. 28 “In another possible embodiment, an integrated circuit component 2700 may include a die 104 mounted on the bottom side of the circuit board 102, as shown in FIG. 2” see “solder balls 222”, see Fig. 36. See Lee Fig. 2 “Outer terminals (or alternatively, external connection terminals) 94 may be attached to the substrate lower conductive patterns 86 of the package substrate 90. The outer terminals 94 may be solder balls” “Referring to FIG. 12, in a semiconductor package 100f according to the present example embodiment, each of first connecting elements 64a may include a first conductive pillar 61a and a first conductive bump 63a” “first conductive bump 63a may be formed of or include at least one of tin or lead”. See Fig. 5 see “first connecting element 64a may penetrate the second lower insulating layer 74 and contact the first lower redistribution pattern 70a. The second connecting element 64b may penetrate the second lower insulating layer 74 and contact the second lower redistribution pattern 70b. The under-fill layer 92 may be interposed between the second lower insulating layer 74 and the package substrate 90”, see Fig. 6 see number of stacked units, see “Referring to FIG. 11, in a semiconductor package 100e according to the present example embodiment, a package substrate 90a may be provided to have a multi-layered PCB structure”. Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Nad to include further comprising forming a bump on a side of the MLCC-based substrate that is opposite to a side of the RDL. Thus it would be obvious to combine the references to arrive at the claimed invention. The motivation is to make external connections for example to other components to form larger circuits to perform more work. In regard to claim 17 Nad and Lee as combined further comprising coupling the MLCC-based substrate [see combination claim 16 see Lee “Referring to FIG. 11, in a semiconductor package 100e according to the present example embodiment, a package substrate 90a may be provided to have a multi-layered PCB structure”] to a printed circuit board (PCB) by the bump. In regard to claim 18 Nad and Lee as combined does not specifically teach further comprising coupling the MLCC-based substrate to a printed circuit board (PCB) by a wire. However wire bonding is a well-known and standard technique, which is easy to perform and gives good electrical connectivity. See Lee paragraph 0003 “a semiconductor chip which is mounted on the PCB and is electrically connected to the PCB by bonding wires or bumps” “The second chip conductive pads 152 may be connected to some of the second substrate upper conductive patterns 126 through wires 165”, see Fig. 6. Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Nad to include further comprising coupling the MLCC-based substrate to a printed circuit board (PCB) by a wire. Thus it would be obvious to combine the references to arrive at the claimed invention. The motivation is that wire bonding is a well-known and standard technique, which is easy to perform and gives good electrical connectivity. In regard to claim 19 Nad and Lee as combined does not specifically teach comprising forming an underfill between the IC and the MLCC-based substrate. However underfill is common in the art, see Nad “the power components 208, 210 may be attached together using, e.g., glue epoxy, bump bonding, hybrid bonding, fusion bonding, thermocompression bonding, wafer on wafer bonding, wafer-on-wafer hybrid bonding, solder with underfill, and/or the like”. See Lee Fig. 4P see “under-fill layer 92 may be interposed between the lower insulating layer 62 and the package substrate 90. The under-fill layer 92 may be provided between the package substrate 90 and the semiconductor chip 40 and between the package substrate 90 and the connection substrate 25”. Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Nad to include comprising forming an underfill between the IC and the MLCC-based substrate. Thus it would be obvious to combine the references to arrive at the claimed invention. The motivation is underfill gives good strength, good electrical isolation for good electrical connections . 07-21-aia AIA Claim (s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nad and Lee as combined and further in view of Gandhi et al. (US 20210134757 A1) hereafter referred to as Gandhi In regard to claim 20 Nad and Lee as combined does not specifically teach in Fig. 31 wherein the IC is configured to transfer heat directly to a heat sink. See Nad paragraph 0082 “It should be appreciated that the integrated circuit component 100 and other integrated circuit components described herein may have additional components not shown, such as additional semiconductor dies, active component, passive components, heat management components such as integrated heat spreaders and heat sinks, etc”. See Gandhi Fig. 1 “An optional cover (not shown) maybe disposed over the top surface 142 of the IC dies 106, 126. When a cover or other heat sink is present over the IC dies 106, thermal interface material (TIM) may be disposed between the top surface 142 of the IC dies 106, 126 and the bottom surface of the cover to enhance heat transfer therebetween. In one example, the TIM may be a thermal gel or thermal epoxy, such as, packaging component attach adhesives. In some implementations, a separate heat sink may be disposed over and in contact with the cover”. Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Nad to include wherein the IC is configured to transfer heat directly to a heat sink. Thus it would be obvious to combine the references to arrive at the claimed invention. The motivation is to remove heat in order to cool the integrated circuit so as to improve its performance . 07-21-aia AIA Claim (s) 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nad and Lee as combined and further in view of Jeng et al. (US 20140217610 A1) hereafter referred to as Jeng In regard to claim 21 Nad and Lee as combined does not specifically teach further comprising cutting the MLCC-based substrate. See Nad uses dicing see paragraph 0063, 0237 “In block 308, the wafer 500 is diced to form DTCs 208, as shown in FIG. 7” “In block 314, a substrate core 202 is prepared, such as by dicing, polishing, etc., as shown in FIG. 8” “forming a plurality of power components on a semiconductor wafer; thinning the semiconductor wafer; and dicing the semiconductor wafer to form the first power component”. See Jeng paragraph 0035 “It should be noted that the interposer 202 illustrates an interposer prior to dicing to form separate packages. In FIG. 2, lines 216 illustrate boundaries, e.g., scribe lines, at which the interposer 202 may be diced upon completion” “FIG. 9 illustrates the structure illustrated in FIG. 8 after the interposer 202 has been diced”. Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Nad to include further comprising cutting the MLCC-based substrate. Thus it would be obvious to combine the references to arrive at the claimed invention. The motivation is that using larger structures followed by dicing is a common way to do mass production to reduce cost and increase manufacturing volume . 07-21-aia AIA Claim (s) 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nad et al. (US 20250218982 A1) hereafter referred to as Nad in view of Lee et al. (US 20190378795 A1) hereafter referred to as Lee. Lee is also provided as evidence . In regard to claim 22 Nad teaches a package [see Fig. 31, see paragraph 0081] comprising: a MLCC-based substrate [“more than one MLCC 210 may be stacked in the cavity 214 of an integrated circuit component 3100, as shown in FIG. 31” “the cavity 214 may only have MLCCs 210 embedded within it”] comprising a plurality of multilayer ceramic capacitors (MLCCs) embedded [see paragraph 0059 “The volume of the cavity 214 that is not taken up by the power components 208, 210 may be filled with any suitable filler material 224. For example, the filler material 224 may be prepreg, Ajinomoto build-up film (ABF), photoimageable dielectric, an inorganic dielectric material, an organic dielectric material, an oxide, a nitride, silicon dioxide, silicon nitride, polymer, epoxy, polyimide, polymer composites with inorganic fillers, and/or the like. The filler material 224 may be applied using any suitable approach, such as compression molding, vacuum lamination, hot press, chemical vapor deposition, physical vapor deposition, and/or the like”] in a filler, wherein each MLCC of the plurality of MLCCs directly contacts [“power components 208, 210 may be attached together in any suitable manner, such as by using an adhesive 212, such as die attach film 212. Additionally or alternatively, the power components 208, 210 may be attached together using, e.g., glue epoxy, bump bonding, hybrid bonding, fusion bonding, thermocompression bonding, wafer on wafer bonding, wafer-on-wafer hybrid bonding, solder with underfill, and/or the like”] another MLCC; forming a redistribution layer [“the circuit board 102 is a multi-layer circuit board 102 with build-up layers 204, 206 above and below the substrate core 202. The build-up layers 204, 206 may have any suitable number of layers, such as 1-10 layers each” “circuit board 102 includes traces 218 and vias 220. The traces 218 and vias 220 may be made of any suitable conductive material, such as copper or aluminum” “electrodes for the capacitor may be coupled to traces 218 or pads 218 defined in the build-up layers 204, 206” “pads 218 and vias 220 in the build-up layers 204, 206” “build-up layers 204, 206 may be created using any suitable set of techniques, such as electroplating, electroless plating, photolithography, etching, etc” see by “circuit board” Nad means metal and dielectric, see “circuit board 3602 may be a printed circuit board (PCB) including multiple metal (or interconnect) layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias”] (RDL) in an insulating layer on the MLCC-based substrate; an integrated circuit (IC) coupled [“In an illustrative embodiment, the die 104 above the power components 208, 210 is a processor die and other dies 106 may be memory dies communicatively coupled to the processor die 104”] to the MLCC-based substrate, but does not state that the filler is a resin. However Nad uses “filler material 224 may be prepreg, Ajinomoto build-up film (ABF), photoimageable dielectric, an inorganic dielectric material, an organic dielectric material, an oxide, a nitride, silicon dioxide, silicon nitride, polymer, epoxy, polyimide, polymer composites with inorganic fillers, and/or the like” see Nad paragraph 0116 “an epoxy resin, a fiberglass-reinforced epoxy resin, an epoxy resin with inorganic fillers”, see that prepreg, Ajinomoto build-up film (ABF), polyimide usually contain resin, see evidence of Lee see paragraph 0032 “insulating material may include thermosetting resins (e.g., epoxy resin), thermoplastic resins (e.g., polyimide), or composite resins (e.g., prepreg, Ajinomoto build-up film (ABF)”. Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Nad to include that the filler is resin. Thus it would be obvious to combine the references to arrive at the claimed invention. The motivation is that epoxy resin, polyimide, prepreg, Ajinomoto build-up film (ABF) are known to give good results in resin form to form insulation layers. See that by “circuit board” Nad means metal and dielectric, see “circuit board 3602 may be a printed circuit board (PCB) including multiple metal (or interconnect) layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias” thus the claim limitation “in an insulating layer” is satisfied, however for the sake of completeness, the Examiner is also providing a 103 rejection. See Lee teaches see Fig. 2 see paragraph 0032 “mold layer 50 may be formed of or include an insulating resin (e.g., epoxy molding compound (EMC))” “A first upper insulating layer 52 may be provided on the mold top surface 50a” “Redistribution vias 54 may penetrate the first upper insulating layer 52 and the mold layer 50, and may be used to electrically connect the redistribution patterns 56 to the third connection conductive patterns 11c” “first upper insulating layer 52 and the second upper insulating layer 58 may independently include at least one of thermosetting resins (e.g., epoxy resin), thermoplastic resins (e.g., polyimide), ABF, or Photo-Imageable Dielectric (PID) resin” . Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Nad to include that “in an insulating layer”. Thus it would be obvious to combine the references to arrive at the claimed invention. The motivation is standard circuit layer of conductor and dielectric is known to give good results as interconnection layer for electronic devices. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to SITARAMARAO S YECHURI whose telephone number is (571)272-8764. The examiner can normally be reached M-F 8:00-4:30 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt D Hanley can be reached at 571-270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SITARAMARAO S YECHURI/ Primary Examiner, Art Unit 2893 Application/Control Number: 18/600,443 Page 2 Art Unit: 2893 Application/Control Number: 18/600,443 Page 3 Art Unit: 2893 Application/Control Number: 18/600,443 Page 4 Art Unit: 2893 Application/Control Number: 18/600,443 Page 5 Art Unit: 2893 Application/Control Number: 18/600,443 Page 6 Art Unit: 2893
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