DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Claims 1-20 are pending.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Mandai et al., US 11476372 B1 (“Mandai”).
Regarding claim 1, Mandai teaches a system of generating histogram data (Fig. 15, electronic device 1500), the system comprising circuitry to:
emit a first series of light pulses, and for each light pulse, receive first data from a plurality of SPADs (Fig.3 and [35], The SPAD-based photon detector 300 may be a 3D image sensor or depth sensor of the device described with reference to FIGS. 1A-1B. [36] The SPAD-based photon detector 300 includes an emitter/transmitter (Tx) 302, and a detector/receiver (Rx) 304 [...] the emitter 302 may be operated to emit a pulse of electromagnetic radiation in each of a set of time intervals. In some embodiments, the pulses may be emitted at a PRI. The detector 304 may include an array of pixels, each including a SPAD);
for the first series of light pulses, bin the received first SPAD data in a histogram memory (Fig. 4 and [40], Upon one or a small number of photons impinging on the SPAD 402, an avalanche may occur within the SPAD 402 and the SPAD 402 may generate an avalanche timing output signal. [41] Upon the SPAD's generation of the avalanche timing output signal, the TDC 414 may latch a current timing reference in the sequence of timing references. [42] The latched timing reference may serve as an index or address for addressing one of a number of memory locations 420 (or memory addresses, or histogram counts (HCs)) in a memory 418. Also, see Fig. 14, block 1402);
transfer at least a portion of the binned first SPAD data to a second memory (Fig. 4 and [44], A readout circuit 424 may be coupled to the memory 418. In some embodiments, the readout circuit 424 may be configured to shift a set of counts into a buffer 426, which buffer 426 may be read while a next set of counts is being collected);
emit a second series of light pulses, and for each light pulse, receive second data from the plurality of SPADs (Fig. 5 and [47], As described with reference to FIGS. 2 and 3, a SPAD-based depth sensor may include an electromagnetic radiation source that may emit, in response to be configured by a processor, a sequence of electromagnetic radiation pulses 502. The pulses of electromagnetic radiation 502 may in some cases be equally spaced in time, and may be separated by a regular time interval 504 (e.g., a PRI). In other cases, the pulses 502 may be emitted at select times. [49] A portion or all of the photons in the pulse 502 may reflect toward a SPAD of the depth sensor as a reflected pulse 508. Upon one or a small number of photons being received by (or arriving at) the SPAD, the SPAD may experience an avalanche condition and generate an avalanche timing output signal in response to the avalanche condition);
for the second series of light pulses, bin the received second SPAD data in the histogram memory (Fig. 5 and [49], Upon receipt of the avalanche timing output signal, a TDC may capture (e.g., latch) a current time reference in the sequence of time references. The captured (e.g., latched) time reference may be used to update the histogram 500. [50] The histogram 500 may include a set of memory locations (e.g., memory addresses or bins) that store a respective set of counts. Each count may represent a number of time intervals, in a set of time intervals, in which the SPAD received one or more photons at a particular time of arrival (or range of times of arrival) and experienced an avalanche condition. Also, see Fig. 14, block 1402);
transfer at least a portion of the binned second SPAD data to the second memory (Fig. 4 and [44], A readout circuit 424 may be coupled to the memory 418. In some embodiments, the readout circuit 424 may be configured to shift a set of counts into a buffer 426, which buffer 426 may be read while a next set of counts is being collected);
combine the transferred binned first SPAD data and the transferred binned second SPAD data (Figs 7-9 and [58], Example way to reduce the area or cost of a histogram memory […] a set of time intervals for which a histogram is built is divided into two or more subsets of time intervals, and a mapping of time references to memory locations is phase shifted from one subset of time intervals to another. [65] FIG. 9 shows a first set of counts 900 read after the first subset of time intervals 700, a second set of counts 902 read after the second subset of time intervals 702. [68] The sets of counts 900-906 may be received and combined (e.g., averaged) by a processor to build a moving average histogram 914 of photon ToAs detected by a SPAD); and
generate an image using the combined SPAD data (Fig. 15 and [105], an electronic device 1500 that includes a SPAD-based photon detector, such as a SPAD-based photon detector, 3D image sensor, or depth sensor).
Regarding claim 2, Mandai teaches the system of claim 1, wherein binning the received second SPAD data in the histogram memory following the second series of light pulses comprises phase shifting the binning of the received second SPAD data into the histogram memory ([58] With reference to FIGS. 7-9, a set of time intervals for which a histogram is built is divided into two or more subsets of time intervals, and a mapping of time references to memory locations is phase shifted from one subset of time intervals to another).
Regarding claim 3, Mandai teaches the system of claim 2, wherein phase shifting the binning of the received second SPAD data is done by phase shifting a clock for the histogram memory by 90 degrees ([58] By way of example, FIGS. 7-9 show four subsets of time intervals. [63] By adjusting the reset or initialization of the counter, for example, the phase of the sequence of time references can be shifted, and the different phase mappings (or phase offsets) described herein inherently occur).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4-7, and 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Mandai et al., US 11476372 B1 (“Mandai”) in view of Zellinger et al., US 10620315 B2 (“Zellinger”).
Regarding claim 4, Mandai teaches the system of claim 2. However, Mandai does not expressly disclose: wherein transferring at least a portion of the binned first SPAD data to the second memory comprises detecting a first peak in the binned first SPAD data, windowing the detected first peak, and transferring the windowed first peak to the second memory, and wherein transferring at least a portion of the binned second SPAD data to the second memory comprises detecting a second peak in the accumulated second SPAD data, windowing the detected second peak, and transferring the windowed second peak to the second memory.
Zellinger teaches a Ladar system and method wherein transferring at least a portion of the binned first SPAD data to the second memory comprises detecting a first peak in the binned first SPAD data, windowing the detected first peak, and transferring the windowed first peak to the second memory (Fig. 1 and [25], The output from the ROIC 130 for each frame may be a 3-dimensional array, referred to herein as the “ROIC output array”. [28] The ROIC output array may be subsequently processed, e.g., by a processing circuit 140. The subsequent processing may include, for example, employing a “chipping” algorithm [...] The input to the chipping algorithm, for each frame, may be a one-dimensional array of sums over the bin-slices of the frame, referred to herein as the “range histogram” or “range histogram array” for the frame (and illustrated, for example, in FIG. 6); the output of the chipping algorithm may be referred to as a “chipped range histogram” or “chipped range histogram array”. [29] The set of ROIC output arrays may be represented (conceptually, or in a memory of the processing circuit 140) as a four-dimensional array, referred to herein as a frame set array, with, e.g., the first two dimensions being pixel coordinates, the third dimension being bin number, and the fourth dimension being frame number. Chipping may be performed before the frame set array is formed. [69] In some embodiments, the chipping operation includes forming a preliminary range estimate, and selecting a set of bins centered on the preliminary range estimate. In one embodiment, a coarse range histogram may be formed [...] A subset of the original range histogram may then be selected, centered on the peak found using the coarse range histogram), and
wherein transferring at least a portion of the binned second SPAD data to the second memory comprises detecting a second peak in the accumulated second SPAD data, windowing the detected second peak, and transferring the windowed second peak to the second memory ([31] In some embodiments, the ladar system may be used to estimate the range to the target. In this case, each bin slice (or a portion of each bin slice, corresponding to the approximate location of the image of the target on the photodiode array 120) from a chip may be summed, to form a two-dimensional array referred to herein as a range versus frame array. Equivalently, the chipped range histograms may be stacked to form a two-dimensional array in which each column is a chipped range histogram for a respective frame).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the SPAD- based photon detector device and method disclosed by Mandai, by incorporating the histogram chipping algorithm as part of the processor and/or the read out circuit, such that histogram peaks can be detected and windowed, as taught by Zellinger. This is simply an obvious variation in the system design that is known and predictable in the art. “Known work in one field of endeavor may prompt variations of it for use in either the same field or a different one based on design incentives or other market forces if the variations are predictable to one of ordinary skill in the art” (MPEP 2141.III KSR Rationale F).
Regarding claim 5, Mandai and Zellinger teach the system of claim 4. Zellinger further teaches wherein combining the transferred binned first SPAD data and the transferred binned second SP AD data further comprises aligning the windowed first peak with the windowed second peak ([41] For each tentative range rate, an adjusted range versus frame array may be formed by shifting each frame of the range versus frame array in the range bin direction by an amount equal, or approximately equal, to the product of the tentative range rate and the frame period. In forming the range rate adjusted range versus frame array, a rectangular array may be formed by padding columns with zeros, or cropping the chipped range histograms, as the chipped range histograms are shifted).
Regarding claim 6, Mandai and Zellinger teach the system of claim 5. Zellinger further teaches wherein windowed first peak is aligned with the windowed second peak using line-fitting ([73] In some embodiments, background subtraction may be performed as a preliminary step before performing chipping, e.g., as described above. A range histogram may be fitted to an exponential background model (in which the background is modeled as being proportional to exp(a+br)). The fit may be performed via a linear regression to the logarithm of the range histogram).
Regarding claim 7, Mandai and Zellinger teach the system of claim 5. Zellinger further teaches wherein windowed first peak is aligned with the windowed second peak using linear interpolation ([41] Interpolation may be used to generate an interpolated shifted frame, that approximates the effect of shifting the frame by a non-integer number of bins […] The sum along the frame direction of the range versus frame array then forms the range rate adjusted collapsed histogram).
Regarding claim 9, Mandai and Zellinger teach the system of claim 5. Mandai further teaches: further comprising:
before transferring at least a portion of the binned first SPAD data to the second memory, transferring the binned first SPAD data to a third memory ([98] The operations at block 1408 may be performed after the first subset of time intervals and before a second subset of time intervals, and may result in a first set of histogram counts being read from the set of memory addresses […] The operations at block 1408 may be performed, for example, by a readout circuit and/or processor described herein. [106] The processor 1504 may be a microprocessor, a central processing unit (CPU), an application-specific integrated circuit (ASIC), a digital signal processor (DSP), a controller, or any combination of such devices), and
before transferring at least a portion of the binned second SPAD data to the second memory, transferring the binned second SPAD data to the third memory ([98] When the operations at block 1402 are performed for a second subset of time intervals, the operations at block 1408 may be performed after the second subset of time intervals (and in some cases, before a third subset of time intervals), and may result in a second set of histogram counts being read from the set of memory addresses).
Regarding claim 10, Mandai and Zellinger teach the system of claim 9. Zellinger further teaches wherein the second memory is on a field programmable gate array and the third memory is a memory coupled to a digital signal processor ([76] The term “processing circuit” is used herein to include any combination of hardware, firmware, and software, employed to process data or digital signals. Processing circuit hardware may include, for example, application specific integrated circuits (ASICs), general purpose or special purpose central processing units (CPUs), digital signal processors (DSPs), graphics processing units (GPUs), and programmable logic devices such as field programmable gate arrays (FPGAs) [...] A processing circuit may contain other processing circuits; for example, a processing circuit may include two processing circuits, an FPGA and a CPU).
Claims 11-14 are rejected under 35 U.S.C. 103 as being unpatentable over Mandai et al., US 11476372 B1 (“Mandai”) in view of Zellinger et al., US 10620315 B2 (“Zellinger”).
Regarding claim 11, Mandai teaches a system of generating histogram data (Fig. 15, electronic device 1500), the system comprising circuitry to:
emit a first series of light pulses, and for each light pulse, receive data from a plurality of SPADs (Fig.3 and [35], The SPAD-based photon detector 300 may be a 3D image sensor or depth sensor of the device described with reference to FIGS. 1A-1B. [36] The SPAD-based photon detector 300 includes an emitter/transmitter (Tx) 302, and a detector/receiver (Rx) 304 [...] the emitter 302 may be operated to emit a pulse of electromagnetic radiation in each of a set of time intervals. In some embodiments, the pulses may be emitted at a PRI. The detector 304 may include an array of pixels, each including a SPAD);
for the first series of light pulses, bin the received SPAD data in a histogram memory (Fig. 4 and [40], Upon one or a small number of photons impinging on the SPAD 402, an avalanche may occur within the SPAD 402 and the SPAD 402 may generate an avalanche timing output signal. [41] Upon the SPAD's generation of the avalanche timing output signal, the TDC 414 may latch a current timing reference in the sequence of timing references. [42] The latched timing reference may serve as an index or address for addressing one of a number of memory locations 420 (or memory addresses, or histogram counts (HCs)) in a memory 418. Also, see Fig. 14, block 1402);
emit a second series of light pulses, and for each light pulse, receive data from the plurality of SPADs (Fig. 5 and [47], As described with reference to FIGS. 2 and 3, a SPAD-based depth sensor may include an electromagnetic radiation source that may emit, in response to be configured by a processor, a sequence of electromagnetic radiation pulses 502. The pulses of electromagnetic radiation 502 may in some cases be equally spaced in time, and may be separated by a regular time interval 504 (e.g., a PRI). In other cases, the pulses 502 may be emitted at select times. [49] A portion or all of the photons in the pulse 502 may reflect toward a SPAD of the depth sensor as a reflected pulse 508. Upon one or a small number of photons being received by (or arriving at) the SPAD, the SPAD may experience an avalanche condition and generate an avalanche timing output signal in response to the avalanche condition);
for the second series of light pulses, bin the received SPAD data in the histogram memory (Fig. 5 and [49], Upon receipt of the avalanche timing output signal, a TDC may capture (e.g., latch) a current time reference in the sequence of time references. The captured (e.g., latched) time reference may be used to update the histogram 500. [50] The histogram 500 may include a set of memory locations (e.g., memory addresses or bins) that store a respective set of counts. Each count may represent a number of time intervals, in a set of time intervals, in which the SPAD received one or more photons at a particular time of arrival (or range of times of arrival) and experienced an avalanche condition. Also, see Fig. 14, block 1402);
Mandai does not expressly disclose detect a first peak in the accumulated SPAD data; window the detected first peak; transfer the windowed first peak to a second memory; detect a second peak in the binned SPAD data; window the detected second peak; transfer the windowed second peak to the second memory;
combine the windowed first peak with the windowed second peak; and generate an image using the combined windowed first peak and the windowed second peak.
Zellinger teaches a Ladar system and method for range estimation that detect a first peak in the accumulated SPAD data; window the detected first peak (Fig. 1 and [25], The output from the ROIC 130 for each frame may be a 3-dimensional array, referred to herein as the “ROIC output array”. [28] The ROIC output array may be subsequently processed, e.g., by a processing circuit 140. The subsequent processing may include, for example, employing a “chipping” algorithm [...] The input to the chipping algorithm, for each frame, may be a one-dimensional array of sums over the bin-slices of the frame, referred to herein as the “range histogram” or “range histogram array” for the frame (and illustrated, for example, in FIG. 6); the output of the chipping algorithm may be referred to as a “chipped range histogram” or “chipped range histogram array”. [29] The set of ROIC output arrays may be represented (conceptually, or in a memory of the processing circuit 140) as a four-dimensional array, referred to herein as a frame set array, with, e.g., the first two dimensions being pixel coordinates, the third dimension being bin number, and the fourth dimension being frame number. Chipping may be performed before the frame set array is formed. [69] In some embodiments, the chipping operation includes forming a preliminary range estimate, and selecting a set of bins centered on the preliminary range estimate. In one embodiment, a coarse range histogram may be formed [...] A subset of the original range histogram may then be selected, centered on the peak found using the coarse range histogram);
transfer the windowed first peak to a second memory ([29] The set of ROIC output arrays may be represented (conceptually, or in a memory of the processing circuit 140) as a four-dimensional array, referred to herein as a frame set array. Chipping may be performed before the frame set array is formed);
detect a second peak in the binned SPAD data; window the detected second peak ([31] In some embodiments, the ladar system may be used to estimate the range to the target. In this case, each bin slice (or a portion of each bin slice, corresponding to the approximate location of the image of the target on the photodiode array 120) from a chip may be summed, to form a two-dimensional array referred to herein as a range versus frame array. Equivalently, the chipped range histograms may be stacked to form a two-dimensional array in which each column is a chipped range histogram for a respective frame);
transfer the windowed second peak to the second memory ([29] The set of ROIC output arrays may be represented (conceptually, or in a memory of the processing circuit 140) as a four-dimensional array, referred to herein as a frame set array. Chipping may be performed before the frame set array is formed);
combine the windowed first peak with the windowed second peak ([31] The chipped range histograms may be stacked to form a two-dimensional array in which each column is a chipped range histogram for a respective frame); and
generate an image using the combined windowed first peak and the windowed second peak ([75] Embodiments of the present invention may be used to estimate the range and range rate of a target, to estimate the cross-range velocity and angular velocity of the target, and to generate images of the target).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the SPAD- based photon detector device and method disclosed by Mandai, by incorporating the histogram chipping algorithm as part of the processor and/or the read out circuit, such that histogram peaks can be detected, windowed and combined to estimate the range and range rate, and generate accurate images of the target after compensating for the target motion, as taught by Zellinger. This is simply an obvious variation in the system design that is known and predictable in the art. “Known work in one field of endeavor may prompt variations of it for use in either the same field or a different one based on design incentives or other market forces if the variations are predictable to one of ordinary skill in the art” (MPEP 2141.III KSR Rationale F).
Regarding claim 12, Mandai in view of Zellinger teach the system of claim 11. Mandi further teaches wherein binning the received SPAD data in the histogram memory following the second series of light pulses comprises phase shifting the binning of the received data into the histogram memory ([58] With reference to FIGS. 7-9, a set of time intervals for which a histogram is built is divided into two or more subsets of time intervals, and a mapping of time references to memory locations is phase shifted from one subset of time intervals to another).
Regarding claim 13, Mandai in view of Zellinger teach the system of claim 12. Mandai further teaches wherein phase shifting the binning of the received SPAD data is done by phase shifting a clock for the histogram memory by 90 degrees ([58] By way of example, FIGS. 7-9 show four subsets of time intervals. [63] By adjusting the reset or initialization of the counter, for example, the phase of the sequence of time references can be shifted, and the different phase mappings (or phase offsets) described herein inherently occur).
Regarding claim 14, Mandai in view of Zellinger teach the system of claim 13. Zellinger further teaches wherein combining the windowed first peak with the windowed second peak comprises utilizing line-fitting ([73] In some embodiments, background subtraction may be performed as a preliminary step before performing chipping, e.g., as described above. A range histogram may be fitted to an exponential background model (in which the background is modeled as being proportional to exp(a+br)). The fit may be performed via a linear regression to the logarithm of the range histogram).
Claims 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Mandai et al., US 11476372 B1 (“Mandai”) in view of Zellinger et al., US 10620315 B2 (“Zellinger”).
Regarding claim 16, Mandai teaches a system for generating histogram data (Fig. 15, electronic device 1500), the system comprising circuitry to:
emit a first series of light pulses, and for each light pulse, receive data from a plurality of SPADs (Fig.3 and [35] The SPAD-based photon detector 300 may be a 3D image sensor or depth sensor of the device described with reference to FIGS. 1A-1B. [36] The SPAD-based photon detector 300 includes an emitter/transmitter (Tx) 302, and a detector/receiver (Rx) 304 [...] the emitter 302 may be operated to emit a pulse of electromagnetic radiation in each of a set of time intervals. In some embodiments, the pulses may be emitted at a PRI. The detector 304 may include an array of pixels, each including a SPAD);
for the first series of light pulses, bin the received SPAD data in a histogram memory (Fig. 4 and [40] Upon one or a small number of photons impinging on the SPAD 402, an avalanche may occur within the SPAD 402 and the SPAD 402 may generate an avalanche timing output signal. [41] Upon the SPAD's generation of the avalanche timing output signal, the TDC 414 may latch a current timing reference in the sequence of timing references. [42] The latched timing reference may serve as an index or address for addressing one of a number of memory locations 420 (or memory addresses, or histogram counts (HCs)) in a memory 418. Also, see Fig. 14, block 1402);
transfer the binned SPAD data to a second memory (Fig. 4 and [44], A readout circuit 424 may be coupled to the memory 418. In some embodiments, the readout circuit 424 may be configured to shift a set of counts into a buffer 426, which buffer 426 may be read while a next set of counts is being collected);
emit a second series of light pulses, and for each light pulse, receive data from the plurality of SPADs (Fig. 5 and [47], As described with reference to FIGS. 2 and 3, a SPAD-based depth sensor may include an electromagnetic radiation source that may emit, in response to be configured by a processor, a sequence of electromagnetic radiation pulses 502. The pulses of electromagnetic radiation 502 may in some cases be equally spaced in time, and may be separated by a regular time interval 504 (e.g., a PRI). In other cases, the pulses 502 may be emitted at select times. [49] A portion or all of the photons in the pulse 502 may reflect toward a SPAD of the depth sensor as a reflected pulse 508. Upon one or a small number of photons being received by (or arriving at) the SPAD, the SPAD may experience an avalanche condition and generate an avalanche timing output signal in response to the avalanche condition);
for the second series of light pulses, bin the received SPAD data in the histogram memory (Fig. 5 and [49], Upon receipt of the avalanche timing output signal, a TDC may capture (e.g., latch) a current time reference in the sequence of time references. The captured (e.g., latched) time reference may be used to update the histogram 500. [50] The histogram 500 may include a set of memory locations (e.g., memory addresses or bins) that store a respective set of counts. Each count may represent a number of time intervals, in a set of time intervals, in which the SPAD received one or more photons at a particular time of arrival (or range of times of arrival) and experienced an avalanche condition. Also, see Fig. 14, block 1402);
transfer the binned SPAD data to the second memory (Fig. 4 and [44], A readout circuit 424 may be coupled to the memory 418. In some embodiments, the readout circuit 424 may be configured to shift a set of counts into a buffer 426, which buffer 426 may be read while a next set of counts is being collected);
Mandai does not expressly disclose: detect a first peak in the transferred SPAD data; window the detected first peak and storing the windowed first peak; detect a second peak in the transferred SPAD data; window the detected second peak and storing the windowed second peak; combine the windowed first peak with the windowed second peak; and generate an image using the combined windowed first peak and the windowed second peak.
Zellinger teaches detect a first peak in the transferred SPAD data; window the detected first peak and storing the windowed first peak (Fig. 1 and [25], The output from the ROIC 130 for each frame may be a 3-dimensional array, referred to herein as the “ROIC output array”. [28] The ROIC output array may be subsequently processed, e.g., by a processing circuit 140. The subsequent processing may include, for example, employing a “chipping” algorithm [...] The input to the chipping algorithm, for each frame, may be a one-dimensional array of sums over the bin-slices of the frame, referred to herein as the “range histogram” or “range histogram array” for the frame (and illustrated, for example, in FIG. 6); the output of the chipping algorithm may be referred to as a “chipped range histogram” or “chipped range histogram array”. [29] The set of ROIC output arrays may be represented (conceptually, or in a memory of the processing circuit 140) as a four-dimensional array, referred to herein as a frame set array, with, e.g., the first two dimensions being pixel coordinates, the third dimension being bin number, and the fourth dimension being frame number. Chipping may be performed before the frame set array is formed. [69] In some embodiments, the chipping operation includes forming a preliminary range estimate, and selecting a set of bins centered on the preliminary range estimate. In one embodiment, a coarse range histogram may be formed [...] A subset of the original range histogram may then be selected, centered on the peak found using the coarse range histogram);
detect a second peak in the transferred SPAD data; window the detected second peak and storing the windowed second peak ([31] In some embodiments, the ladar system may be used to estimate the range to the target. In this case, each bin slice (or a portion of each bin slice, corresponding to the approximate location of the image of the target on the photodiode array 120) from a chip may be summed, to form a two-dimensional array referred to herein as a range versus frame array. Equivalently, the chipped range histograms may be stacked to form a two-dimensional array in which each column is a chipped range histogram for a respective frame);
combine the windowed first peak with the windowed second peak ([31] The chipped range histograms may be stacked to form a two-dimensional array in which each column is a chipped range histogram for a respective frame); and
generate an image using the combined windowed first peak and the windowed second peak ([75] Embodiments of the present invention may be used to estimate the range and range rate of a target, to estimate the cross-range velocity and angular velocity of the target, and to generate images of the target).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the SPAD- based photon detector device and method disclosed by Mandai, by incorporating the histogram chipping algorithm as part of the processor and/or the read out circuit, such that histogram peaks can be detected, windowed and combined to estimate the range and range rate, and generate accurate images of the target after compensating for the target motion, as taught by Zellinger. This is simply an obvious variation in the system design that is known and predictable in the art. “Known work in one field of endeavor may prompt variations of it for use in either the same field or a different one based on design incentives or other market forces if the variations are predictable to one of ordinary skill in the art” (MPEP 2141.III KSR Rationale F).
Regarding claim 17, Mandai in view of Zellinger teach the system of claim 16. Mandai further teaches wherein binning the received SPAD data in the histogram memory following the second series of light pulses comprises phase shifting the binning of the received SPAD data into the histogram memory ([58] With reference to FIGS. 7-9, a set of time intervals for which a histogram is built is divided into two or more subsets of time intervals, and a mapping of time references to memory locations is phase shifted from one subset of time intervals to another).
Regarding claim 18, Mandai in view of Zellinger teach the system of claim 17. Mandai further teaches wherein phase shifting the binning of the received SPAD data is done by phase shifting a clock for the histogram memory by 90 degrees ([58] By way of example, FIGS. 7-9 show four subsets of time intervals. [63] By adjusting the reset or initialization of the counter, for example, the phase of the sequence of time references can be shifted, and the different phase mappings (or phase offsets) described herein inherently occur).
Regarding claim 19, Mandai in view of Zellinger teach the system of claim 18. Zellinger further teaches wherein combining the windowed first peak with the windowed second peak comprises utilizing line-fitting ([73] In some embodiments, background subtraction may be performed as a preliminary step before performing chipping, e.g., as described above. A range histogram may be fitted to an exponential background model (in which the background is modeled as being proportional to exp(a+br)). The fit may be performed via a linear regression to the logarithm of the range histogram).
Regarding claim 20, Mandai in view of Zellinger teach the system of claim 19. Zellinger further teaches further comprising, before combining the windowed first peak with the windowed second peak, transferring the windowed first peak and the windowed second peak to a third memory ([30] Certain elements of the processing described herein as being performed in the processing circuit 140 may equally well be performed in the ROIC 130, and vice versa. System design requirements including power and heat management, and the bandwidths of interfaces between elements of the system, may influence where various processing operations are performed. [76] The term “processing circuit” is used herein to include any combination of hardware, firmware, and software, employed to process data or digital signals. Processing circuit hardware may include, for example, application specific integrated circuits (ASICs), general purpose or special purpose central processing units (CPUs), digital signal processors (DSPs), graphics processing units (GPUs), and programmable logic devices such as field programmable gate arrays (FPGAs) [...] A processing circuit may contain other processing circuits; for example, a processing circuit may include two processing circuits, an FPGA and a CPU).
Claims 8 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Mandai et al., US 11476372 B1 (“Mandai”) in view of Zellinger et al., US 10620315 B2 (“Zellinger”), further in view of Finkelstein et al., US 11467286 B2 (“Finkelstein”).
Regarding claim 8, Mandai in view of Zellinger teach the system of claim 5. However, the combination does not expressly teach wherein the first series of light pulses are emitted at a first power and the second series of light pulses are emitted at a second power, the first power different than the second power.
Finkelstein teaches systems and methods for high resolution Lidar wherein the first series of light pulses are emitted at a first power and the second series of light pulses are emitted at a second power, the first power different than the second power ([71] In some embodiments, the number of laser cycles for a distant time gate is larger than the number of laser cycles for a closer time gate, or vice versa. [72] More generally, the number of laser cycles allocated per time gate/corresponding subframe may be varied so to provide more laser cycles for dimmer (lower-reflectivity) targets, or more laser cycles for brighter (higher-reflectivity) targets).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the SPAD- based Lidar system and method disclosed by Mandai and Zellinger, by adding the capability to vary the number of laser cycles (average power) emitted by the transmitter, and allocated for each subframe, such that power can be adjusted based on the target distance and/or reflectivity, as taught by Finkelstein. This is simply an obvious variation in the system design that is known and predictable in the art. “Known work in one field of endeavor may prompt variations of it for use in either the same field or a different one based on design incentives or other market forces if the variations are predictable to one of ordinary skill in the art” (MPEP 2141.III KSR Rationale F).
Regarding claim 15, Mandai in view of Zellinger teach the system of claim 14. Claim 15 is rejected for the same reasons as claim 8.
Conclusion
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/KHALIL ALI AHMAD/Examiner, Art Unit 3645
/YUQING XIAO/Supervisory Patent Examiner, Art Unit 3645
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