DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 8, 10-11 and 16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Balteanu et al. (US 20230023111 A1).
PNG
media_image1.png
532
964
media_image1.png
Greyscale
Fig. 5B of Balteanu reproduced for ease of reference.
Regarding Claim 1, Balteanu teaches (in Fig. 5B) a bias circuit (213) connected to a first transistor (common source FET 211) configured to amplify an input RF signal (RFIN).
Balteanu teaches the bias circuit is configured to provide a bias voltage (cascode bias voltage VCAS) to a second transistor (cascode FET 212) that amplifies an output RF signal of the first transistor.
Balteanu teaches a current source (reference current source 215) configured to receive a power supply voltage (VDD) and generate a reference current (IREF).
Balteanu further teaches a current-to-voltage conversion circuit (voltage bias circuit 222) configured to convert the reference current into the bias voltage and provide the bias voltage to a control terminal (gate) of the second transistor.
Regarding Claim 2, Balteanu teaches that the current source comprises a trimmable PTAT (Proportional To Absolute Temperature) current source 382 generating a PTAT current (IPTAT), wherein the magnitude of the reference current inherently increases as temperature increases.
Regarding Claim 3, Balteanu teaches a voltage bias circuit 242 comprising parallel paths to convert current to voltage using selectable elements, specifically a first gain control switch 253 and a second gain control switch 254 connected in parallel with biasing FETs to ground to route the current.
Regarding Claim 10, Balteanu teaches a low noise amplifier (LNA 230) comprising a common source transistor (FET 211) configured to amplify an input RF signal (RFIN) and output an amplified RF signal.
Balteanu teaches a common gate transistor (cascode FET 212) connected to the common source transistor with a cascode structure, configured to operate based on a bias voltage (VCAS) input to a control terminal, and configured to amplify and output the signal of the common source transistor.
Balteanu teaches a bias circuit (213) configured to generate a reference current (IREF) from a power supply voltage (VDD) and generate the bias voltage with the reference current.
Regarding Claim 11, Balteanu teaches the bias circuit comprises a current source and current-to-voltage conversion circuit providing bias to the common gate transistor.
Balteanu teaches the current source comprises a PTAT current source 382 that increases the magnitude of the reference current as temperature increases.
Regarding Claim 16, Balteanu teaches the current-to-voltage conversion circuit (voltage bias circuit 242) includes a plurality of resistors (first biasing resistor 251, second biasing resistor 252) connected between the current source and ground, where the bias voltage is generated by at least some of the plurality of resistors.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 3-7, 9, 12-15 are rejected under 35 U.S.C. 103 as being unpatentable over Balteanu in view of Klaren et al. US 2021/0013841 A1).
Regarding Claim 3, Balteanu teaches a bias circuit with a PTAT current source that increases reference current as temperature increases.
Balteanu, however, does not explicitly detail a third transistor connected to the power supply and a second terminal to ground through a resistor, and a fourth transistor in a current mirror structure, where the resistance value decreases as temperature increases.
Klaren, in a similar field of endeavor, teaches bias current variations driven by temperature effects (PVT) can be compensated using specific reference current generation techniques, such as utilizing a bandgap voltage reference across a resistor (Rcomp, §0056-§0058) .
It would be obvious to a person having ordinary skill in the art (PHOSITA) to modify the PTAT current source of Balteanu to incorporate Klaren's specific transistor current mirror and resistor topology, substituting an NTC (negative temperature coefficient) resistor to realize the PTAT profile.
The motivation for this modification is to stabilize the circuit against temperature fluctuations and maintain consistent RF performance metrics, as taught by Klaren.
Regarding Claim 4, Balteanu teaches a current mirror and bias circuit.
Balteanu, however, does not explicitly teach an operational amplifier with a reference voltage applied to a first terminal to control the current mirror transistors.
Klaren teaches using an operational amplifier (op-amp 502) in a closed-loop control circuit to force node voltages to match a reference voltage drop across a resistor, thereby controlling the gates of mirror transistors.
It would be obvious to a PHOSITA to modify Balteanu's current mirror to include the operational amplifier feedback loop of Klaren.
The motivation is to ensure exact matching of drain/source voltages and improve bias current mirroring accuracy regardless of supply variations, as explicitly taught by Klaren.
Regarding Claim 5, Balteanu teaches a current source and current mirror topology.
Balteanu, however, does not teach the specific 5th, 6th, and 7th transistor cascoded arrangement on the current mirror.
Klaren teaches extending bias circuits with stacked or cascoded devices to handle practical supply voltages and improve output resistance.
It would be obvious to a PHOSITA to modify Balteanu's current source to include the 5th, 6th, and 7th transistors in a cascode arrangement as taught by Klaren.
The motivation is to compensate for the poor output resistance characteristics of silicon-based CMOS devices with short channel lengths, as taught by Klaren.
Regarding Claim 6, Balteanu teaches a current source and current mirroring circuit. Balteanu, however, does not teach a diode-connected 6th transistor and 7th transistor configuration.
Klaren teaches using diode-connected reference FETs (e.g., connecting gate to drain) in a bias reference circuit to provide precise voltage offsets and mirroring.
It would be obvious to a PHOSITA to modify Balteanu's current mirror to utilize the diode-connected transistor configurations of Klaren.
The motivation is to simplify the control loop and force the drain voltages of the reference stack to match the amplifier stack, improving current mirroring accuracy as taught by Klaren.
Regarding Claim 7, Balteanu teaches a current-to-voltage conversion circuit.
Balteanu, however, does not explicitly teach a plurality of resistors connected in series with switches between the current source and the control terminal.
Klaren teaches a switchable resistance de-coupling network (DCN 256x) utilizing series-connected resistors and switches to programmatically set bias levels to a control terminal.
It would be obvious to a PHOSITA to modify the current-to-voltage conversion circuit of Balteanu to incorporate Klaren's switchable series resistor network.
The motivation is to allow for dynamically changing bias and performance during operation via digital programming, as taught by Klaren.
Regarding Claim 9, Balteanu teaches a current-to-voltage conversion circuit.
Balteanu, however, does not teach a plurality of diodes connected in series with switches.
Klaren teaches utilizing diode-connected devices to provide voltage offsets in bias circuits.
It would be obvious to a PHOSITA to modify Balteanu's bias network to use a plurality of diode-connected devices and switches in place of standard resistors.
The motivation is to accommodate arbitrary variations in supply voltage while providing precise, switchable voltage stepping, as derived from Klaren's teachings on offset matching.
Regarding Claim 12, Balteanu teaches an LNA bias circuit with a PTAT current source.
Balteanu, however, does not detail a third and fourth transistor in a current mirror structure paired with a resistor whose value decreases as temperature increases.
Klaren teaches stabilizing bias current variations caused by temperature effects using a bandgap voltage reference across a resistor.
It would be obvious to a PHOSITA to implement the PTAT current source of Balteanu using Klaren's transistor current mirror and an NTC resistor.
To stabilize the LNA circuit against temperature fluctuations and maintain consistent RF performance metrics, as taught by Klaren.
Regarding Claim 13, Balteanu teaches a current mirror biasing an LNA.
Balteanu, however, does not teach an operational amplifier receiving a reference voltage to control the current mirror.
Klaren teaches an operational amplifier (op-amp 502) in a closed-loop control circuit to force node voltages to match a reference voltage drop, controlling mirror transistors.
It would be obvious to modify Balteanu's LNA current mirror to include the operational amplifier feedback loop of Klaren to ensure exact matching of drain/source voltages and improve bias current mirroring accuracy regardless of LNA supply variations, as taught by Klaren.
Regarding Claim 14, Balteanu teaches a current source and mirror topology for an LNA.
Balteanu, however, does not teach the specific 5th, 6th, and 7th transistor cascoded arrangement.
Klaren teaches extending bias circuits with stacked/cascoded devices to handle practical supply voltages.
It would be obvious to modify Balteanu's current source to include the 5th, 6th, and 7th transistors in a cascode arrangement as taught by Klaren to compensate for poor output resistance characteristics of silicon-based CMOS devices with short channel lengths, improving the LNA bias, as taught by Klaren.
Regarding Claim 15, Balteanu teaches an LNA current mirroring circuit.
Balteanu, however, does not teach a diode-connected 6th transistor and 7th transistor configuration.
Klaren teaches using diode-connected reference FETs in a bias reference circuit for precise voltage offsets.
It would be obvious to modify Balteanu's LNA current mirror to utilize the diode-connected transistor configurations of Klaren to simplify the LNA control loop and force the drain voltages of the reference stack to match the amplifier stack, improving current mirroring accuracy as taught by Klaren.
Conclusion
The prior arts, Su et al. (US 2014/0043102 A1), DING et al. (US 2015/0280672 A1, TANAKA et al. (US 2020/0195210 A1) and DING (US 2020/0313626 A1) made of record and not relied upon is considered pertinent to applicant's disclosure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HAFIZUR RAHMAN whose telephone number is (571)270-0659. The examiner can normally be reached M-F: 10-6.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Han can be reached on (571) 272-2078. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/HAFIZUR RAHMAN/Primary Examiner, Art Unit 2843.
Prosecution Insights